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Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<10>(0h200)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = and(_T_19, _T_24)
node _T_26 = or(UInt<1>(0h0), _T_25)
node _T_27 = and(_T_18, _T_26)
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(UInt<1>(0h0), _T_33)
node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<10>(0h200)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = and(_T_34, _T_39)
node _T_41 = or(UInt<1>(0h0), _T_40)
node _T_42 = and(UInt<1>(0h0), _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_42, UInt<1>(0h1), "") : assert_3
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(is_aligned, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_56, UInt<1>(0h1), "") : assert_7
node _T_60 = not(io.in.a.bits.mask)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_61, UInt<1>(0h1), "") : assert_8
node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_69 :
node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_71 = and(UInt<1>(0h0), _T_70)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<10>(0h200)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = and(_T_73, _T_78)
node _T_80 = or(UInt<1>(0h0), _T_79)
node _T_81 = and(_T_72, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_81, UInt<1>(0h1), "") : assert_10
node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_87 = and(_T_85, _T_86)
node _T_88 = or(UInt<1>(0h0), _T_87)
node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h200)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = and(_T_88, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = and(UInt<1>(0h0), _T_95)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_103, UInt<1>(0h1), "") : assert_13
node _T_107 = asUInt(reset)
node _T_108 = eq(_T_107, UInt<1>(0h0))
when _T_108 :
node _T_109 = eq(is_aligned, UInt<1>(0h0))
when _T_109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_110, UInt<1>(0h1), "") : assert_15
node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_114, UInt<1>(0h1), "") : assert_16
node _T_118 = not(io.in.a.bits.mask)
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_119, UInt<1>(0h1), "") : assert_17
node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_123, UInt<1>(0h1), "") : assert_18
node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_127 :
node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = or(UInt<1>(0h0), _T_130)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_131, UInt<1>(0h1), "") : assert_19
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<10>(0h200)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = and(_T_138, _T_143)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = asUInt(reset)
node _T_147 = eq(_T_146, UInt<1>(0h0))
when _T_147 :
node _T_148 = eq(_T_145, UInt<1>(0h0))
when _T_148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_145, UInt<1>(0h1), "") : assert_20
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_155, UInt<1>(0h1), "") : assert_23
node _T_159 = eq(io.in.a.bits.mask, mask)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_159, UInt<1>(0h1), "") : assert_24
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_163, UInt<1>(0h1), "") : assert_25
node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_170 = and(_T_168, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<10>(0h200)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = and(_T_175, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_183, UInt<1>(0h1), "") : assert_26
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(is_aligned, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_193, UInt<1>(0h1), "") : assert_29
node _T_197 = eq(io.in.a.bits.mask, mask)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_197, UInt<1>(0h1), "") : assert_30
node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_201 :
node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_203 = and(UInt<1>(0h0), _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_207 = and(_T_205, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<10>(0h200)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = and(_T_208, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(_T_204, _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_216, UInt<1>(0h1), "") : assert_31
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(is_aligned, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_226, UInt<1>(0h1), "") : assert_34
node _T_230 = not(mask)
node _T_231 = and(io.in.a.bits.mask, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_232, UInt<1>(0h1), "") : assert_35
node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_236 :
node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_238 = and(UInt<1>(0h0), _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<10>(0h200)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = and(_T_240, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = and(_T_239, _T_247)
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_248, UInt<1>(0h1), "") : assert_36
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(is_aligned, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_258, UInt<1>(0h1), "") : assert_39
node _T_262 = eq(io.in.a.bits.mask, mask)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_262, UInt<1>(0h1), "") : assert_40
node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_266 :
node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_268 = and(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<10>(0h200)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_T_269, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_278, UInt<1>(0h1), "") : assert_41
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_288, UInt<1>(0h1), "") : assert_44
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_292, UInt<1>(0h1), "") : assert_45
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_296 :
node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_298 = and(UInt<1>(0h0), _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<10>(0h200)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = and(_T_300, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = and(_T_299, _T_307)
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_308, UInt<1>(0h1), "") : assert_46
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_318, UInt<1>(0h1), "") : assert_49
node _T_322 = eq(io.in.a.bits.mask, mask)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_322, UInt<1>(0h1), "") : assert_50
node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_326, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_330, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_334 :
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_338, UInt<1>(0h1), "") : assert_54
node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_342, UInt<1>(0h1), "") : assert_55
node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_346, UInt<1>(0h1), "") : assert_56
node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_350, UInt<1>(0h1), "") : assert_57
node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_354 :
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(sink_ok, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_361, UInt<1>(0h1), "") : assert_60
node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_365, UInt<1>(0h1), "") : assert_61
node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_369, UInt<1>(0h1), "") : assert_62
node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_373, UInt<1>(0h1), "") : assert_63
node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_378 = or(UInt<1>(0h1), _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_378, UInt<1>(0h1), "") : assert_64
node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_382 :
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(sink_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_389, UInt<1>(0h1), "") : assert_67
node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_393, UInt<1>(0h1), "") : assert_68
node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_397, UInt<1>(0h1), "") : assert_69
node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_402 = or(_T_401, io.in.d.bits.corrupt)
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_402, UInt<1>(0h1), "") : assert_70
node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_407 = or(UInt<1>(0h1), _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_407, UInt<1>(0h1), "") : assert_71
node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_411 :
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_415, UInt<1>(0h1), "") : assert_73
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_419, UInt<1>(0h1), "") : assert_74
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = or(UInt<1>(0h1), _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_424, UInt<1>(0h1), "") : assert_75
node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_428 :
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_432, UInt<1>(0h1), "") : assert_77
node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_437 = or(_T_436, io.in.d.bits.corrupt)
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_437, UInt<1>(0h1), "") : assert_78
node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_442 = or(UInt<1>(0h1), _T_441)
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_442, UInt<1>(0h1), "") : assert_79
node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_450, UInt<1>(0h1), "") : assert_81
node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_454, UInt<1>(0h1), "") : assert_82
node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_459 = or(UInt<1>(0h1), _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_459, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_463, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_467, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_471, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_475 = eq(a_first, UInt<1>(0h0))
node _T_476 = and(io.in.a.valid, _T_475)
when _T_476 :
node _T_477 = eq(io.in.a.bits.opcode, opcode)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_477, UInt<1>(0h1), "") : assert_87
node _T_481 = eq(io.in.a.bits.param, param)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_481, UInt<1>(0h1), "") : assert_88
node _T_485 = eq(io.in.a.bits.size, size)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_485, UInt<1>(0h1), "") : assert_89
node _T_489 = eq(io.in.a.bits.source, source)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_489, UInt<1>(0h1), "") : assert_90
node _T_493 = eq(io.in.a.bits.address, address)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_493, UInt<1>(0h1), "") : assert_91
node _T_497 = and(io.in.a.ready, io.in.a.valid)
node _T_498 = and(_T_497, a_first)
when _T_498 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_499 = eq(d_first, UInt<1>(0h0))
node _T_500 = and(io.in.d.valid, _T_499)
when _T_500 :
node _T_501 = eq(io.in.d.bits.opcode, opcode_1)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_501, UInt<1>(0h1), "") : assert_92
node _T_505 = eq(io.in.d.bits.param, param_1)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_505, UInt<1>(0h1), "") : assert_93
node _T_509 = eq(io.in.d.bits.size, size_1)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_509, UInt<1>(0h1), "") : assert_94
node _T_513 = eq(io.in.d.bits.source, source_1)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_513, UInt<1>(0h1), "") : assert_95
node _T_517 = eq(io.in.d.bits.sink, sink)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_517, UInt<1>(0h1), "") : assert_96
node _T_521 = eq(io.in.d.bits.denied, denied)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_521, UInt<1>(0h1), "") : assert_97
node _T_525 = and(io.in.d.ready, io.in.d.valid)
node _T_526 = and(_T_525, d_first)
when _T_526 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_527 = and(io.in.a.valid, a_first_1)
node _T_528 = and(_T_527, UInt<1>(0h1))
when _T_528 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_529 = and(io.in.a.ready, io.in.a.valid)
node _T_530 = and(_T_529, a_first_1)
node _T_531 = and(_T_530, UInt<1>(0h1))
when _T_531 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_532 = dshr(inflight, io.in.a.bits.source)
node _T_533 = bits(_T_532, 0, 0)
node _T_534 = eq(_T_533, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_534, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_538 = and(io.in.d.valid, d_first_1)
node _T_539 = and(_T_538, UInt<1>(0h1))
node _T_540 = eq(d_release_ack, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
when _T_541 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_542 = and(io.in.d.ready, io.in.d.valid)
node _T_543 = and(_T_542, d_first_1)
node _T_544 = and(_T_543, UInt<1>(0h1))
node _T_545 = eq(d_release_ack, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
when _T_546 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_551 = dshr(inflight, io.in.d.bits.source)
node _T_552 = bits(_T_551, 0, 0)
node _T_553 = or(_T_552, same_cycle_resp)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_553, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_559 = or(_T_557, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_559, UInt<1>(0h1), "") : assert_100
node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_563, UInt<1>(0h1), "") : assert_101
else :
node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_569, UInt<1>(0h1), "") : assert_102
node _T_573 = eq(io.in.d.bits.size, a_size_lookup)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_573, UInt<1>(0h1), "") : assert_103
node _T_577 = and(io.in.d.valid, d_first_1)
node _T_578 = and(_T_577, a_first_1)
node _T_579 = and(_T_578, io.in.a.valid)
node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(d_release_ack, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
node _T_584 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_585 = or(_T_584, io.in.a.ready)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_585, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_94
node _T_589 = orr(inflight)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_592 = or(_T_590, _T_591)
node _T_593 = lt(watchdog, plusarg_reader.out)
node _T_594 = or(_T_592, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_594, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_598 = and(io.in.a.ready, io.in.a.valid)
node _T_599 = and(io.in.d.ready, io.in.d.valid)
node _T_600 = or(_T_598, _T_599)
when _T_600 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_601 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_604 = and(_T_602, _T_603)
node _T_605 = and(_T_601, _T_604)
when _T_605 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_607 = and(_T_606, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_610 = and(_T_608, _T_609)
node _T_611 = and(_T_607, _T_610)
when _T_611 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_612 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_614, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_618 = and(io.in.d.valid, d_first_2)
node _T_619 = and(_T_618, UInt<1>(0h1))
node _T_620 = and(_T_619, d_release_ack_1)
when _T_620 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_621 = and(io.in.d.ready, io.in.d.valid)
node _T_622 = and(_T_621, d_first_2)
node _T_623 = and(_T_622, UInt<1>(0h1))
node _T_624 = and(_T_623, d_release_ack_1)
when _T_624 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_625 = and(io.in.d.valid, d_first_2)
node _T_626 = and(_T_625, UInt<1>(0h1))
node _T_627 = and(_T_626, d_release_ack_1)
when _T_627 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_628 = dshr(inflight_1, io.in.d.bits.source)
node _T_629 = bits(_T_628, 0, 0)
node _T_630 = or(_T_629, same_cycle_resp_1)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_630, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_634, UInt<1>(0h1), "") : assert_108
else :
node _T_638 = eq(io.in.d.bits.size, c_size_lookup)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_638, UInt<1>(0h1), "") : assert_109
node _T_642 = and(io.in.d.valid, d_first_2)
node _T_643 = and(_T_642, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_644 = and(_T_643, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_646 = and(_T_644, _T_645)
node _T_647 = and(_T_646, d_release_ack_1)
node _T_648 = eq(c_probe_ack, UInt<1>(0h0))
node _T_649 = and(_T_647, _T_648)
when _T_649 :
node _T_650 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_651 = or(_T_650, _WIRE_23.ready)
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_651, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_95
node _T_655 = orr(inflight_1)
node _T_656 = eq(_T_655, UInt<1>(0h0))
node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_658 = or(_T_656, _T_657)
node _T_659 = lt(watchdog_1, plusarg_reader_1.out)
node _T_660 = or(_T_658, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_660, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_665 = and(io.in.d.ready, io.in.d.valid)
node _T_666 = or(_T_664, _T_665)
when _T_666 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_598; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_14 :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit_14( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_8 :
input clock : Clock
input reset : Reset
output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}}
invalidate io.tilelink.e.bits.sink
invalidate io.tilelink.e.valid
invalidate io.tilelink.e.ready
invalidate io.tilelink.d.bits.corrupt
invalidate io.tilelink.d.bits.data
invalidate io.tilelink.d.bits.denied
invalidate io.tilelink.d.bits.sink
invalidate io.tilelink.d.bits.source
invalidate io.tilelink.d.bits.size
invalidate io.tilelink.d.bits.param
invalidate io.tilelink.d.bits.opcode
invalidate io.tilelink.d.valid
invalidate io.tilelink.d.ready
invalidate io.tilelink.c.bits.corrupt
invalidate io.tilelink.c.bits.data
invalidate io.tilelink.c.bits.address
invalidate io.tilelink.c.bits.source
invalidate io.tilelink.c.bits.size
invalidate io.tilelink.c.bits.param
invalidate io.tilelink.c.bits.opcode
invalidate io.tilelink.c.valid
invalidate io.tilelink.c.ready
invalidate io.tilelink.b.bits.corrupt
invalidate io.tilelink.b.bits.data
invalidate io.tilelink.b.bits.mask
invalidate io.tilelink.b.bits.address
invalidate io.tilelink.b.bits.source
invalidate io.tilelink.b.bits.size
invalidate io.tilelink.b.bits.param
invalidate io.tilelink.b.bits.opcode
invalidate io.tilelink.b.valid
invalidate io.tilelink.b.ready
invalidate io.tilelink.a.bits.corrupt
invalidate io.tilelink.a.bits.data
invalidate io.tilelink.a.bits.mask
invalidate io.tilelink.a.bits.address
invalidate io.tilelink.a.bits.source
invalidate io.tilelink.a.bits.size
invalidate io.tilelink.a.bits.param
invalidate io.tilelink.a.bits.opcode
invalidate io.tilelink.a.valid
invalidate io.tilelink.a.ready
inst a of TLAToNoC_8
connect a.clock, clock
connect a.reset, reset
inst c of TLCToNoC_8
connect c.clock, clock
connect c.reset, reset
inst d of TLDFromNoC_8
connect d.clock, clock
connect d.reset, reset
connect a.io.protocol, io.tilelink.a
connect c.io.protocol, io.tilelink.c
connect io.tilelink.d.bits, d.io.protocol.bits
connect io.tilelink.d.valid, d.io.protocol.valid
connect d.io.protocol.ready, io.tilelink.d.ready
connect io.flits.a.bits, a.io.flit.bits
connect io.flits.a.valid, a.io.flit.valid
connect a.io.flit.ready, io.flits.a.ready
connect io.flits.c.bits, c.io.flit.bits
connect io.flits.c.valid, c.io.flit.valid
connect c.io.flit.ready, io.flits.c.ready
connect d.io.flit, io.flits.d | module TLMasterACDToNoC_8( // @[Tilelink.scala:72:7]
input clock, // @[Tilelink.scala:72:7]
input reset, // @[Tilelink.scala:72:7]
output io_tilelink_a_ready, // @[Tilelink.scala:79:14]
input io_tilelink_a_valid, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14]
input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14]
input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14]
input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14]
output io_tilelink_c_ready, // @[Tilelink.scala:79:14]
input io_tilelink_c_valid, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14]
input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14]
input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14]
input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14]
input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14]
input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14]
input io_tilelink_d_ready, // @[Tilelink.scala:79:14]
output io_tilelink_d_valid, // @[Tilelink.scala:79:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14]
output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14]
output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14]
output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14]
input io_flits_a_ready, // @[Tilelink.scala:79:14]
output io_flits_a_valid, // @[Tilelink.scala:79:14]
output io_flits_a_bits_head, // @[Tilelink.scala:79:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:79:14]
output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14]
input io_flits_c_ready, // @[Tilelink.scala:79:14]
output io_flits_c_valid, // @[Tilelink.scala:79:14]
output io_flits_c_bits_head, // @[Tilelink.scala:79:14]
output io_flits_c_bits_tail, // @[Tilelink.scala:79:14]
output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14]
output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14]
output io_flits_d_ready, // @[Tilelink.scala:79:14]
input io_flits_d_valid, // @[Tilelink.scala:79:14]
input io_flits_d_bits_head, // @[Tilelink.scala:79:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:79:14]
input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14]
);
wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17]
TLAToNoC_8 a ( // @[Tilelink.scala:88:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:88:17]
TLCToNoC_8 c ( // @[Tilelink.scala:89:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (_c_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_c_bits_egress_id)
); // @[Tilelink.scala:89:17]
TLDFromNoC_1 d ( // @[Tilelink.scala:90:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14]
); // @[Tilelink.scala:90:17]
assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus :
output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst pbus_clock_groups of ClockGroupAggregator_pbus
inst clockGroup of ClockGroup_1
inst fixedClockNode of FixedClockBroadcast_2
inst broadcast of BundleBridgeNexus_NoOutput_1
inst fixer of TLFIFOFixer_1
connect fixer.clock, childClock
connect fixer.reset, childReset
inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u
connect in_xbar.clock, childClock
connect in_xbar.reset, childReset
inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s7k1z3u
connect out_xbar.clock, childClock
connect out_xbar.reset, childReset
inst buffer of TLBuffer_a29d64s7k1z3u
connect buffer.clock, childClock
connect buffer.reset, childReset
inst atomics of TLAtomicAutomata_pbus
connect atomics.clock, childClock
connect atomics.reset, childReset
inst buffer_1 of TLBuffer_a29d64s7k1z3u_1
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg
connect coupler_to_bootaddressreg.clock, childClock
connect coupler_to_bootaddressreg.reset, childReset
inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0
connect coupler_to_device_named_uart_0.clock, childClock
connect coupler_to_device_named_uart_0.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_9
connect monitor.clock, childClock
connect monitor.reset, childReset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect clockGroup.auto.in, pbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect out_xbar.auto.anon_in, fixer.auto.anon_out
connect atomics.auto.in, in_xbar.auto.anon_out
connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0
connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1
connect fixer.auto.anon_in, buffer.auto.out
connect buffer.auto.in, atomics.auto.out
connect in_xbar.auto.anon_in, buffer_1.auto.out
connect buffer_1.auto.in, bus_xingOut
connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d
connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits
connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid
connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready
connect bus_xingIn, auto.bus_xing_in
connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in
connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1
connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d
connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits
connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid
connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready
regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000)
node pad = or(bootAddrReg, UInt<64>(0h0))
node _oldBytes_T = bits(pad, 7, 0)
node _oldBytes_T_1 = bits(pad, 15, 8)
node _oldBytes_T_2 = bits(pad, 23, 16)
node _oldBytes_T_3 = bits(pad, 31, 24)
node _oldBytes_T_4 = bits(pad, 39, 32)
node _oldBytes_T_5 = bits(pad, 47, 40)
node _oldBytes_T_6 = bits(pad, 55, 48)
node _oldBytes_T_7 = bits(pad, 63, 56)
wire oldBytes : UInt<8>[8]
connect oldBytes[0], _oldBytes_T
connect oldBytes[1], _oldBytes_T_1
connect oldBytes[2], _oldBytes_T_2
connect oldBytes[3], _oldBytes_T_3
connect oldBytes[4], _oldBytes_T_4
connect oldBytes[5], _oldBytes_T_5
connect oldBytes[6], _oldBytes_T_6
connect oldBytes[7], _oldBytes_T_7
wire newBytes : UInt<8>[8]
connect newBytes, oldBytes
wire _valids_WIRE : UInt<1>[8]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
wire valids : UInt<1>[8]
connect valids, _valids_WIRE
node _T = or(valids[0], valids[1])
node _T_1 = or(_T, valids[2])
node _T_2 = or(_T_1, valids[3])
node _T_3 = or(_T_2, valids[4])
node _T_4 = or(_T_3, valids[5])
node _T_5 = or(_T_4, valids[6])
node _T_6 = or(_T_5, valids[7])
when _T_6 :
node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0])
node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2])
node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo)
node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4])
node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6])
node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo)
node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo)
connect bootAddrReg, _bootAddrReg_T
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(nodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, nodeIn.a.bits.data
connect in.bits.mask, nodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h0))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[8]
wire out_wivalid : UInt<1>[8]
wire out_roready : UInt<1>[8]
wire out_woready : UInt<1>[8]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 7, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 7, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 7, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 7, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_2 = bits(out_front.bits.data, 7, 0)
connect valids[0], out_f_woready
when out_f_woready :
connect newBytes[0], _out_T_2
node _out_T_3 = eq(out_rimask, UInt<1>(0h0))
node _out_T_4 = eq(out_wimask, UInt<1>(0h0))
node _out_T_5 = eq(out_romask, UInt<1>(0h0))
node _out_T_6 = eq(out_womask, UInt<1>(0h0))
node _out_T_7 = or(oldBytes[0], UInt<8>(0h0))
node _out_T_8 = bits(_out_T_7, 7, 0)
node _out_rimask_T_1 = bits(out_frontMask, 15, 8)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 15, 8)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 15, 8)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 15, 8)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_9 = bits(out_front.bits.data, 15, 8)
connect valids[1], out_f_woready_1
when out_f_woready_1 :
connect newBytes[1], _out_T_9
node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_12 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_13 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_8, UInt<8>(0h0))
node out_prepend = cat(oldBytes[1], _out_prepend_T)
node _out_T_14 = or(out_prepend, UInt<16>(0h0))
node _out_T_15 = bits(_out_T_14, 15, 0)
node _out_rimask_T_2 = bits(out_frontMask, 23, 16)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 23, 16)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 23, 16)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 23, 16)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_16 = bits(out_front.bits.data, 23, 16)
connect valids[2], out_f_woready_2
when out_f_woready_2 :
connect newBytes[2], _out_T_16
node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_19 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_20 = eq(out_womask_2, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0))
node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1)
node _out_T_21 = or(out_prepend_1, UInt<24>(0h0))
node _out_T_22 = bits(_out_T_21, 23, 0)
node _out_rimask_T_3 = bits(out_frontMask, 31, 24)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 31, 24)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 31, 24)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 31, 24)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
node _out_T_23 = bits(out_front.bits.data, 31, 24)
connect valids[3], out_f_woready_3
when out_f_woready_3 :
connect newBytes[3], _out_T_23
node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_26 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_27 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0))
node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2)
node _out_T_28 = or(out_prepend_2, UInt<32>(0h0))
node _out_T_29 = bits(_out_T_28, 31, 0)
node _out_rimask_T_4 = bits(out_frontMask, 39, 32)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 39, 32)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 39, 32)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 39, 32)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_30 = bits(out_front.bits.data, 39, 32)
connect valids[4], out_f_woready_4
when out_f_woready_4 :
connect newBytes[4], _out_T_30
node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_33 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_34 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0))
node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3)
node _out_T_35 = or(out_prepend_3, UInt<40>(0h0))
node _out_T_36 = bits(_out_T_35, 39, 0)
node _out_rimask_T_5 = bits(out_frontMask, 47, 40)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 47, 40)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 47, 40)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 47, 40)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_37 = bits(out_front.bits.data, 47, 40)
connect valids[5], out_f_woready_5
when out_f_woready_5 :
connect newBytes[5], _out_T_37
node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_40 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_41 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0))
node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4)
node _out_T_42 = or(out_prepend_4, UInt<48>(0h0))
node _out_T_43 = bits(_out_T_42, 47, 0)
node _out_rimask_T_6 = bits(out_frontMask, 55, 48)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 55, 48)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 55, 48)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 55, 48)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_44 = bits(out_front.bits.data, 55, 48)
connect valids[6], out_f_woready_6
when out_f_woready_6 :
connect newBytes[6], _out_T_44
node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_47 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_48 = eq(out_womask_6, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0))
node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5)
node _out_T_49 = or(out_prepend_5, UInt<56>(0h0))
node _out_T_50 = bits(_out_T_49, 55, 0)
node _out_rimask_T_7 = bits(out_frontMask, 63, 56)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 63, 56)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 63, 56)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 63, 56)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_51 = bits(out_front.bits.data, 63, 56)
connect valids[7], out_f_woready_7
when out_f_woready_7 :
connect newBytes[7], _out_T_51
node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_54 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_55 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0))
node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6)
node _out_T_56 = or(out_prepend_6, UInt<64>(0h0))
node _out_T_57 = bits(_out_T_56, 63, 0)
node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[7], _out_rifireMux_T_3
connect out_rivalid[6], _out_rifireMux_T_3
connect out_rivalid[5], _out_rifireMux_T_3
connect out_rivalid[4], _out_rifireMux_T_3
connect out_rivalid[3], _out_rifireMux_T_3
connect out_rivalid[2], _out_rifireMux_T_3
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rifireMux_WIRE : UInt<1>[1]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[7], _out_wifireMux_T_4
connect out_wivalid[6], _out_wifireMux_T_4
connect out_wivalid[5], _out_wifireMux_T_4
connect out_wivalid[4], _out_wifireMux_T_4
connect out_wivalid[3], _out_wifireMux_T_4
connect out_wivalid[2], _out_wifireMux_T_4
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wifireMux_WIRE : UInt<1>[1]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[7], _out_rofireMux_T_3
connect out_roready[6], _out_rofireMux_T_3
connect out_roready[5], _out_rofireMux_T_3
connect out_roready[4], _out_rofireMux_T_3
connect out_roready[3], _out_rofireMux_T_3
connect out_roready[2], _out_rofireMux_T_3
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rofireMux_WIRE : UInt<1>[1]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[7], _out_wofireMux_T_4
connect out_woready[6], _out_wofireMux_T_4
connect out_woready[5], _out_wofireMux_T_4
connect out_woready[4], _out_wofireMux_T_4
connect out_woready[3], _out_wofireMux_T_4
connect out_woready[2], _out_wofireMux_T_4
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wofireMux_WIRE : UInt<1>[1]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE : UInt<1>[1]
connect _out_out_bits_data_WIRE[0], _out_T_1
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0])
node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE_1 : UInt<64>[1]
connect _out_out_bits_data_WIRE_1[0], _out_T_57
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, nodeIn.a.valid
connect nodeIn.a.ready, in.ready
connect nodeIn.d.valid, out.valid
connect out.ready, nodeIn.d.ready
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate nodeIn_d_bits_d.data
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
connect nodeIn.d.bits.data, out.bits.data
node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module PeripheryBus_pbus( // @[ClockDomain.scala:14:9]
input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire nodeIn_d_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17]
wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [6:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [6:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29]
wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [6:0] in_xbar__addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar__requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar__requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] in_xbar_requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] in_xbar__beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar__beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar__portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar_portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] in_xbar__portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar_portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46]
wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73]
wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46]
wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73]
wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73]
wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_31; // @[FIFOFixer.scala:79:27]
reg fixer_flight_32; // @[FIFOFixer.scala:79:27]
reg fixer_flight_33; // @[FIFOFixer.scala:79:27]
reg fixer_flight_34; // @[FIFOFixer.scala:79:27]
reg fixer_flight_35; // @[FIFOFixer.scala:79:27]
reg fixer_flight_36; // @[FIFOFixer.scala:79:27]
reg fixer_flight_37; // @[FIFOFixer.scala:79:27]
reg fixer_flight_38; // @[FIFOFixer.scala:79:27]
reg fixer_flight_39; // @[FIFOFixer.scala:79:27]
reg fixer_flight_40; // @[FIFOFixer.scala:79:27]
reg fixer_flight_41; // @[FIFOFixer.scala:79:27]
reg fixer_flight_42; // @[FIFOFixer.scala:79:27]
reg fixer_flight_43; // @[FIFOFixer.scala:79:27]
reg fixer_flight_44; // @[FIFOFixer.scala:79:27]
reg fixer_flight_45; // @[FIFOFixer.scala:79:27]
reg fixer_flight_46; // @[FIFOFixer.scala:79:27]
reg fixer_flight_47; // @[FIFOFixer.scala:79:27]
reg fixer_flight_48; // @[FIFOFixer.scala:79:27]
reg fixer_flight_49; // @[FIFOFixer.scala:79:27]
reg fixer_flight_50; // @[FIFOFixer.scala:79:27]
reg fixer_flight_51; // @[FIFOFixer.scala:79:27]
reg fixer_flight_52; // @[FIFOFixer.scala:79:27]
reg fixer_flight_53; // @[FIFOFixer.scala:79:27]
reg fixer_flight_54; // @[FIFOFixer.scala:79:27]
reg fixer_flight_55; // @[FIFOFixer.scala:79:27]
reg fixer_flight_56; // @[FIFOFixer.scala:79:27]
reg fixer_flight_57; // @[FIFOFixer.scala:79:27]
reg fixer_flight_58; // @[FIFOFixer.scala:79:27]
reg fixer_flight_59; // @[FIFOFixer.scala:79:27]
reg fixer_flight_60; // @[FIFOFixer.scala:79:27]
reg fixer_flight_61; // @[FIFOFixer.scala:79:27]
reg fixer_flight_62; // @[FIFOFixer.scala:79:27]
reg fixer_flight_63; // @[FIFOFixer.scala:79:27]
reg fixer_flight_64; // @[FIFOFixer.scala:79:27]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [6:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [6:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [6:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34]
wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34]
wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}]
wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24]
wire [7:0] newBytes_0; // @[RegField.scala:152:31]
wire [7:0] newBytes_1; // @[RegField.scala:152:31]
wire [7:0] newBytes_2; // @[RegField.scala:152:31]
wire [7:0] newBytes_3; // @[RegField.scala:152:31]
wire [7:0] newBytes_4; // @[RegField.scala:152:31]
wire [7:0] newBytes_5; // @[RegField.scala:152:31]
wire [7:0] newBytes_6; // @[RegField.scala:152:31]
wire [7:0] newBytes_7; // @[RegField.scala:152:31]
wire out_f_woready; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire valids_0; // @[RegField.scala:153:29]
wire valids_1; // @[RegField.scala:153:29]
wire valids_2; // @[RegField.scala:153:29]
wire valids_3; // @[RegField.scala:153:29]
wire valids_4; // @[RegField.scala:153:29]
wire valids_5; // @[RegField.scala:153:29]
wire valids_6; // @[RegField.scala:153:29]
wire valids_7; // @[RegField.scala:153:29]
wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52]
wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52]
wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52]
wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52]
wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52]
wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52]
wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24]
wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35]
bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27]
bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34]
end
always @(posedge)
FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_pbus_out_i1_o2_a29d64s7k1z3u out_xbar ( // @[PeripheryBus.scala:57:30]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (fixer_auto_anon_out_a_ready),
.auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_valid (fixer_auto_anon_out_d_valid),
.auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode),
.auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size),
.auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source),
.auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data),
.auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27]
); // @[PeripheryBus.scala:57:30]
TLBuffer_a29d64s7k1z3u buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29]
.auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9]
.auto_out_a_valid (fixer_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (fixer_auto_anon_in_d_ready),
.auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9]
); // @[Buffer.scala:75:28]
TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (in_xbar_auto_anon_out_a_ready),
.auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (in_xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_atomics_auto_out_a_valid),
.auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_atomics_auto_out_a_bits_param),
.auto_out_a_bits_size (_atomics_auto_out_a_bits_size),
.auto_out_a_bits_source (_atomics_auto_out_a_bits_source),
.auto_out_a_bits_address (_atomics_auto_out_a_bits_address),
.auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask),
.auto_out_a_bits_data (_atomics_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt),
.auto_out_d_ready (_atomics_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28]
); // @[AtomicAutomata.scala:289:29]
TLBuffer_a29d64s7k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (bus_xingOut_a_ready),
.auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (bus_xingOut_d_valid),
.auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode),
.auto_in_d_bits_param (bus_xingOut_d_bits_param),
.auto_in_d_bits_size (bus_xingOut_d_bits_size),
.auto_in_d_bits_source (bus_xingOut_d_bits_source),
.auto_in_d_bits_sink (bus_xingOut_d_bits_sink),
.auto_in_d_bits_denied (bus_xingOut_d_bits_denied),
.auto_in_d_bits_data (bus_xingOut_d_bits_data),
.auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt),
.auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9]
.auto_out_a_valid (in_xbar_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (in_xbar_auto_anon_in_d_ready),
.auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9]
.auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9]
.auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9]
.auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9]
.auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9]
.auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9]
.auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9]
.auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9]
.auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9]
); // @[Buffer.scala:75:28]
TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_a_valid (nodeIn_a_valid),
.auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode),
.auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param),
.auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size),
.auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source),
.auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address),
.auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask),
.auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data),
.auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt),
.auto_fragmenter_anon_out_d_ready (nodeIn_d_ready),
.auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0),
.auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0),
.auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0),
.auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0),
.auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0),
.auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0),
.auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0),
.auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0),
.auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0),
.auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0),
.auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLMonitor_9 monitor ( // @[Nodes.scala:27:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_45 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_45(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e5_s11_2 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<23>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 22, 22)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 21, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 35, 12)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 12, 11)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 33, 13)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 11, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 12, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 23, 8)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 10, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 0)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[3]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 10, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec[0])
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<5>(0h10)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 2, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 0, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_5, 1, 1)
node _CDom_reduced4SigExtra_T_8 = cat(_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7)
node _CDom_reduced4SigExtra_T_9 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_8)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_9)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 25, 25)
node _notCDom_absSigSum_T = bits(sigSum, 24, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 24, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[13]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 24, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = mux(_notCDom_normDistReduced2_T_1, UInt<4>(0hb), UInt<4>(0hc))
node _notCDom_normDistReduced2_T_14 = mux(_notCDom_normDistReduced2_T_2, UInt<4>(0ha), _notCDom_normDistReduced2_T_13)
node _notCDom_normDistReduced2_T_15 = mux(_notCDom_normDistReduced2_T_3, UInt<4>(0h9), _notCDom_normDistReduced2_T_14)
node _notCDom_normDistReduced2_T_16 = mux(_notCDom_normDistReduced2_T_4, UInt<4>(0h8), _notCDom_normDistReduced2_T_15)
node _notCDom_normDistReduced2_T_17 = mux(_notCDom_normDistReduced2_T_5, UInt<3>(0h7), _notCDom_normDistReduced2_T_16)
node _notCDom_normDistReduced2_T_18 = mux(_notCDom_normDistReduced2_T_6, UInt<3>(0h6), _notCDom_normDistReduced2_T_17)
node _notCDom_normDistReduced2_T_19 = mux(_notCDom_normDistReduced2_T_7, UInt<3>(0h5), _notCDom_normDistReduced2_T_18)
node _notCDom_normDistReduced2_T_20 = mux(_notCDom_normDistReduced2_T_8, UInt<3>(0h4), _notCDom_normDistReduced2_T_19)
node _notCDom_normDistReduced2_T_21 = mux(_notCDom_normDistReduced2_T_9, UInt<2>(0h3), _notCDom_normDistReduced2_T_20)
node _notCDom_normDistReduced2_T_22 = mux(_notCDom_normDistReduced2_T_10, UInt<2>(0h2), _notCDom_normDistReduced2_T_21)
node _notCDom_normDistReduced2_T_23 = mux(_notCDom_normDistReduced2_T_11, UInt<1>(0h1), _notCDom_normDistReduced2_T_22)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_12, UInt<1>(0h0), _notCDom_normDistReduced2_T_23)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 25, 10)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 5, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 1)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[4]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 6, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_reducedVec[1], notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_reducedVec[3], notCDom_reduced4SigExtra_reducedVec[2])
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 3, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 1, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 0, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_6, 1, 1)
node _notCDom_reduced4SigExtra_T_9 = cat(_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8)
node _notCDom_reduced4SigExtra_T_10 = bits(_notCDom_reduced4SigExtra_T_5, 2, 2)
node _notCDom_reduced4SigExtra_T_11 = cat(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10)
node _notCDom_reduced4SigExtra_T_12 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_11)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_12)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 13, 12)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e5_s11_2( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47]
wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43]
wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}]
wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22]
wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20]
wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73]
wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41]
wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70]
wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70]
wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46]
wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}]
wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70]
wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11]
wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29]
wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_5 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_261
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_5( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_261 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_4 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}}
inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_4
connect divSqrtRawFN.clock, clock
connect divSqrtRawFN.reset, reset
connect io.inReady, divSqrtRawFN.io.inReady
connect divSqrtRawFN.io.inValid, io.inValid
connect divSqrtRawFN.io.sqrtOp, io.sqrtOp
node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10)
node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3)
node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4)
node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3)
node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T)
connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1
node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3)
node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1)
connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2
connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero
node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16)
connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T
node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp)
connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T
node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T)
node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0)
node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2)
connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3
connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig
connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp
connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign
connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero
connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf
connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN
node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10)
node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3)
node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4)
node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3)
node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T)
connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1
node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3)
node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1)
connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2
connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero
node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16)
connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T
node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp)
connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T
node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T)
node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0)
node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2)
connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3
connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig
connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp
connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign
connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero
connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf
connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN
connect divSqrtRawFN.io.roundingMode, io.roundingMode
connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div
connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt
connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut
connect io.invalidExc, divSqrtRawFN.io.invalidExc
connect io.infiniteExc, divSqrtRawFN.io.infiniteExc
connect io.rawOut, divSqrtRawFN.io.rawOut | module DivSqrtRecFMToRaw_small_e5_s11_4( // @[DivSqrtRecFN_small.scala:422:5]
input clock, // @[DivSqrtRecFN_small.scala:422:5]
input reset, // @[DivSqrtRecFN_small.scala:422:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:426:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:426:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16]
input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16]
input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16]
output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16]
output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5]
wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5]
wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
DivSqrtRawFN_small_e5_s11_4 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_rawOutValid_div (io_rawOutValid_div_0),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),
.io_roundingModeOut (io_roundingModeOut_0),
.io_invalidExc (io_invalidExc_0),
.io_infiniteExc (io_infiniteExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (io_rawOut_sig_0)
); // @[DivSqrtRecFN_small.scala:446:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = or(_T_667, _T_672)
node _T_699 = or(_T_698, _T_677)
node _T_700 = or(_T_699, _T_682)
node _T_701 = or(_T_700, _T_687)
node _T_702 = or(_T_701, _T_692)
node _T_703 = or(_T_702, _T_697)
node _T_704 = and(_T_662, _T_703)
node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = and(_T_705, _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = or(_T_720, _T_725)
node _T_727 = and(_T_715, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_704)
node _T_729 = or(_T_728, _T_711)
node _T_730 = or(_T_729, _T_727)
node _T_731 = and(_T_658, _T_730)
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_731, UInt<1>(0h1), "") : assert_36
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(is_aligned, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_741, UInt<1>(0h1), "") : assert_39
node _T_745 = eq(io.in.a.bits.mask, mask)
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_745, UInt<1>(0h1), "") : assert_40
node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_749 :
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_754 = and(_T_752, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = or(_T_764, _T_769)
node _T_796 = or(_T_795, _T_774)
node _T_797 = or(_T_796, _T_779)
node _T_798 = or(_T_797, _T_784)
node _T_799 = or(_T_798, _T_789)
node _T_800 = or(_T_799, _T_794)
node _T_801 = and(_T_759, _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_811 = and(_T_809, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = or(_T_817, _T_822)
node _T_824 = and(_T_812, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_801)
node _T_826 = or(_T_825, _T_808)
node _T_827 = or(_T_826, _T_824)
node _T_828 = and(_T_755, _T_827)
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_828, UInt<1>(0h1), "") : assert_41
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(is_aligned, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_838, UInt<1>(0h1), "") : assert_44
node _T_842 = eq(io.in.a.bits.mask, mask)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_842, UInt<1>(0h1), "") : assert_45
node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_846 :
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = or(UInt<1>(0h0), _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = and(_T_856, _T_861)
node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = or(_T_868, _T_873)
node _T_900 = or(_T_899, _T_878)
node _T_901 = or(_T_900, _T_883)
node _T_902 = or(_T_901, _T_888)
node _T_903 = or(_T_902, _T_893)
node _T_904 = or(_T_903, _T_898)
node _T_905 = and(_T_863, _T_904)
node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_908 = and(_T_906, _T_907)
node _T_909 = or(UInt<1>(0h0), _T_908)
node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_911 = cvt(_T_910)
node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000)))
node _T_913 = asSInt(_T_912)
node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0)))
node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = or(_T_914, _T_919)
node _T_921 = and(_T_909, _T_920)
node _T_922 = or(UInt<1>(0h0), _T_862)
node _T_923 = or(_T_922, _T_905)
node _T_924 = or(_T_923, _T_921)
node _T_925 = and(_T_852, _T_924)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_925, UInt<1>(0h1), "") : assert_46
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(is_aligned, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_935, UInt<1>(0h1), "") : assert_49
node _T_939 = eq(io.in.a.bits.mask, mask)
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_939, UInt<1>(0h1), "") : assert_50
node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_943, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_947, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_951 :
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_955, UInt<1>(0h1), "") : assert_54
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_959, UInt<1>(0h1), "") : assert_55
node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_963, UInt<1>(0h1), "") : assert_56
node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_967, UInt<1>(0h1), "") : assert_57
node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_971 :
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(sink_ok, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_978, UInt<1>(0h1), "") : assert_60
node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_982, UInt<1>(0h1), "") : assert_61
node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_986, UInt<1>(0h1), "") : assert_62
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_990, UInt<1>(0h1), "") : assert_63
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = or(UInt<1>(0h1), _T_994)
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_995, UInt<1>(0h1), "") : assert_64
node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_999 :
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(sink_ok, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67
node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68
node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = or(_T_1018, io.in.d.bits.corrupt)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70
node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1024 = or(UInt<1>(0h1), _T_1023)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71
node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73
node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74
node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1041 = or(UInt<1>(0h1), _T_1040)
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75
node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1045 :
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79
node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1092 = eq(a_first, UInt<1>(0h0))
node _T_1093 = and(io.in.a.valid, _T_1092)
when _T_1093 :
node _T_1094 = eq(io.in.a.bits.opcode, opcode)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87
node _T_1098 = eq(io.in.a.bits.param, param)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88
node _T_1102 = eq(io.in.a.bits.size, size)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89
node _T_1106 = eq(io.in.a.bits.source, source)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90
node _T_1110 = eq(io.in.a.bits.address, address)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91
node _T_1114 = and(io.in.a.ready, io.in.a.valid)
node _T_1115 = and(_T_1114, a_first)
when _T_1115 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1116 = eq(d_first, UInt<1>(0h0))
node _T_1117 = and(io.in.d.valid, _T_1116)
when _T_1117 :
node _T_1118 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92
node _T_1122 = eq(io.in.d.bits.param, param_1)
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93
node _T_1126 = eq(io.in.d.bits.size, size_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94
node _T_1130 = eq(io.in.d.bits.source, source_1)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95
node _T_1134 = eq(io.in.d.bits.sink, sink)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96
node _T_1138 = eq(io.in.d.bits.denied, denied)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97
node _T_1142 = and(io.in.d.ready, io.in.d.valid)
node _T_1143 = and(_T_1142, d_first)
when _T_1143 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1144 = and(io.in.a.valid, a_first_1)
node _T_1145 = and(_T_1144, UInt<1>(0h1))
when _T_1145 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1146 = and(io.in.a.ready, io.in.a.valid)
node _T_1147 = and(_T_1146, a_first_1)
node _T_1148 = and(_T_1147, UInt<1>(0h1))
when _T_1148 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1149 = dshr(inflight, io.in.a.bits.source)
node _T_1150 = bits(_T_1149, 0, 0)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1155 = and(io.in.d.valid, d_first_1)
node _T_1156 = and(_T_1155, UInt<1>(0h1))
node _T_1157 = eq(d_release_ack, UInt<1>(0h0))
node _T_1158 = and(_T_1156, _T_1157)
when _T_1158 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1159 = and(io.in.d.ready, io.in.d.valid)
node _T_1160 = and(_T_1159, d_first_1)
node _T_1161 = and(_T_1160, UInt<1>(0h1))
node _T_1162 = eq(d_release_ack, UInt<1>(0h0))
node _T_1163 = and(_T_1161, _T_1162)
when _T_1163 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1164 = and(io.in.d.valid, d_first_1)
node _T_1165 = and(_T_1164, UInt<1>(0h1))
node _T_1166 = eq(d_release_ack, UInt<1>(0h0))
node _T_1167 = and(_T_1165, _T_1166)
when _T_1167 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1168 = dshr(inflight, io.in.d.bits.source)
node _T_1169 = bits(_T_1168, 0, 0)
node _T_1170 = or(_T_1169, same_cycle_resp)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100
node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101
else :
node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1186 = or(_T_1184, _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102
node _T_1190 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103
node _T_1194 = and(io.in.d.valid, d_first_1)
node _T_1195 = and(_T_1194, a_first_1)
node _T_1196 = and(_T_1195, io.in.a.valid)
node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = eq(d_release_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1202 = or(_T_1201, io.in.a.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104
node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1207 = orr(a_set_wo_ready)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
node _T_1209 = or(_T_1206, _T_1208)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_95
node _T_1213 = orr(inflight)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1216 = or(_T_1214, _T_1215)
node _T_1217 = lt(watchdog, plusarg_reader.out)
node _T_1218 = or(_T_1216, _T_1217)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1222 = and(io.in.a.ready, io.in.a.valid)
node _T_1223 = and(io.in.d.ready, io.in.d.valid)
node _T_1224 = or(_T_1222, _T_1223)
when _T_1224 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1225 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = and(_T_1225, _T_1228)
when _T_1229 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1231 = and(_T_1230, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = and(_T_1231, _T_1234)
when _T_1235 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1237 = bits(_T_1236, 0, 0)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1242 = and(io.in.d.valid, d_first_2)
node _T_1243 = and(_T_1242, UInt<1>(0h1))
node _T_1244 = and(_T_1243, d_release_ack_1)
when _T_1244 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1245 = and(io.in.d.ready, io.in.d.valid)
node _T_1246 = and(_T_1245, d_first_2)
node _T_1247 = and(_T_1246, UInt<1>(0h1))
node _T_1248 = and(_T_1247, d_release_ack_1)
when _T_1248 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1249 = and(io.in.d.valid, d_first_2)
node _T_1250 = and(_T_1249, UInt<1>(0h1))
node _T_1251 = and(_T_1250, d_release_ack_1)
when _T_1251 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1252 = dshr(inflight_1, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp_1)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109
else :
node _T_1262 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110
node _T_1266 = and(io.in.d.valid, d_first_2)
node _T_1267 = and(_T_1266, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1268 = and(_T_1267, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1270 = and(_T_1268, _T_1269)
node _T_1271 = and(_T_1270, d_release_ack_1)
node _T_1272 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1275 = or(_T_1274, _WIRE_23.ready)
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111
node _T_1279 = orr(c_set_wo_ready)
when _T_1279 :
node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_96
node _T_1284 = orr(inflight_1)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1287 = or(_T_1285, _T_1286)
node _T_1288 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1294 = and(io.in.d.ready, io.in.d.valid)
node _T_1295 = or(_T_1293, _T_1294)
when _T_1295 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28]
wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59]
wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51]
wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59]
wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71]
wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [31:0] address; // @[Monitor.scala:391:22]
wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35]
assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28]
assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a21d64s7k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_27
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a21d64s7k1z3u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a21d64s7k1z3u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a21d64s7k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_27 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a21d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a21d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_data (auto_out_d_bits_data),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_24 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_48
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_24
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_2 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _T_3 = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _T_6 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _T_8 = or(_T, _T_1)
node _T_9 = or(_T_8, _T_2)
node _T_10 = or(_T_9, _T_3)
node _T_11 = or(_T_10, _T_4)
node _T_12 = or(_T_11, _T_5)
node _T_13 = or(_T_12, _T_6)
node _T_14 = or(_T_13, _T_7)
node _T_15 = eq(_T_14, UInt<1>(0h0))
node _T_16 = and(io.in.valid, _T_15)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_17, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0h9)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0he), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hd), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hb), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0h8), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<3>(0h4), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<3>(0h7), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0h9))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_21 = and(io.in.ready, io.in.valid)
node _T_22 = and(_T_21, io.in.bits.head)
node _T_23 = and(_T_22, at_dest)
when _T_23 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_24 = eq(UInt<5>(0h1b), io.in.bits.egress_id)
when _T_24 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_25 = eq(UInt<5>(0h1c), io.in.bits.egress_id)
when _T_25 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_26 = eq(UInt<5>(0h1d), io.in.bits.egress_id)
when _T_26 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_27 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_28 = and(route_q.io.enq.valid, _T_27)
node _T_29 = eq(_T_28, UInt<1>(0h0))
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_49
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_24
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_33 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_34 = and(vcalloc_q.io.enq.valid, _T_33)
node _T_35 = eq(_T_34, UInt<1>(0h0))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_35, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_24( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h8; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_19 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hE : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hD : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hB : 4'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, 1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T, 1'h0}; // @[Mux.scala:30:73]
wire [2:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_19[2:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_5, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _GEN_1 = {_GEN_0[2:1], _GEN_0[0] | _route_buffer_io_enq_bits_flow_egress_node_id_T_6} | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_7}}; // @[Mux.scala:30:73]
wire [3:0] _GEN_2 = {_route_buffer_io_enq_bits_flow_egress_node_T_19[3], _GEN_1}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_2 == 4'h9; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_2 != 4'h9; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module BoomIOMSHR_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, mem_access : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_ack : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}, clock
reg grant_word : UInt<64>, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
wire size : UInt<2>
connect size, req.uop.mem_size
node _get_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _get_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc))
node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1)
node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2)
node _get_legal_T_4 = xor(req.addr, UInt<1>(0h0))
node _get_legal_T_5 = cvt(_get_legal_T_4)
node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h80110000)))
node _get_legal_T_7 = asSInt(_get_legal_T_6)
node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0)))
node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8)
node _get_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size)
node _get_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6))
node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11)
node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12)
node _get_legal_T_14 = xor(req.addr, UInt<17>(0h10000))
node _get_legal_T_15 = cvt(_get_legal_T_14)
node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h80110000)))
node _get_legal_T_17 = asSInt(_get_legal_T_16)
node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0)))
node _get_legal_T_19 = xor(req.addr, UInt<21>(0h100000))
node _get_legal_T_20 = cvt(_get_legal_T_19)
node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h80100000)))
node _get_legal_T_22 = asSInt(_get_legal_T_21)
node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0)))
node _get_legal_T_24 = xor(req.addr, UInt<32>(0h80000000))
node _get_legal_T_25 = cvt(_get_legal_T_24)
node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h80000000)))
node _get_legal_T_27 = asSInt(_get_legal_T_26)
node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0)))
node _get_legal_T_29 = or(_get_legal_T_18, _get_legal_T_23)
node _get_legal_T_30 = or(_get_legal_T_29, _get_legal_T_28)
node _get_legal_T_31 = and(_get_legal_T_13, _get_legal_T_30)
node _get_legal_T_32 = or(UInt<1>(0h0), _get_legal_T_9)
node get_legal = or(_get_legal_T_32, _get_legal_T_31)
wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect get.opcode, UInt<3>(0h4)
connect get.param, UInt<1>(0h0)
connect get.size, req.uop.mem_size
connect get.source, UInt<4>(0h9)
connect get.address, req.addr
node _get_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0)
node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount)
node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0)
node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1))
node get_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2)
node get_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit)
node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2)
node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T)
node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit)
node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2)
node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1)
node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1)
node get_a_mask_sub_bit = bits(req.addr, 1, 1)
node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2)
node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T)
node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2)
node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1)
node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2)
node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2)
node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2)
node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3)
node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0)
node get_a_mask_bit = bits(req.addr, 0, 0)
node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0))
node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit)
node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq)
node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T)
node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit)
node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1)
node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1)
node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit)
node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2)
node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2)
node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit)
node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3)
node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3)
node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit)
node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4)
node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4)
node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit)
node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5)
node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5)
node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit)
node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6)
node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6)
node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit)
node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7)
node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7)
node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc)
node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2)
node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo)
node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4)
node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6)
node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo)
node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo)
connect get.mask, _get_a_mask_T
invalidate get.data
connect get.corrupt, UInt<1>(0h0)
node _put_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _put_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc))
node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1)
node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2)
node _put_legal_T_4 = xor(req.addr, UInt<1>(0h0))
node _put_legal_T_5 = cvt(_put_legal_T_4)
node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h80110000)))
node _put_legal_T_7 = asSInt(_put_legal_T_6)
node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0)))
node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8)
node _put_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size)
node _put_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6))
node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11)
node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12)
node _put_legal_T_14 = xor(req.addr, UInt<17>(0h10000))
node _put_legal_T_15 = cvt(_put_legal_T_14)
node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h80110000)))
node _put_legal_T_17 = asSInt(_put_legal_T_16)
node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0)))
node _put_legal_T_19 = xor(req.addr, UInt<21>(0h100000))
node _put_legal_T_20 = cvt(_put_legal_T_19)
node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h80100000)))
node _put_legal_T_22 = asSInt(_put_legal_T_21)
node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0)))
node _put_legal_T_24 = xor(req.addr, UInt<32>(0h80000000))
node _put_legal_T_25 = cvt(_put_legal_T_24)
node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h80000000)))
node _put_legal_T_27 = asSInt(_put_legal_T_26)
node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0)))
node _put_legal_T_29 = or(_put_legal_T_18, _put_legal_T_23)
node _put_legal_T_30 = or(_put_legal_T_29, _put_legal_T_28)
node _put_legal_T_31 = and(_put_legal_T_13, _put_legal_T_30)
node _put_legal_T_32 = or(UInt<1>(0h0), _put_legal_T_9)
node put_legal = or(_put_legal_T_32, _put_legal_T_31)
wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect put.opcode, UInt<1>(0h0)
connect put.param, UInt<1>(0h0)
connect put.size, req.uop.mem_size
connect put.source, UInt<4>(0h9)
connect put.address, req.addr
node _put_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0)
node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount)
node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0)
node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1))
node put_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2)
node put_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit)
node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2)
node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T)
node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit)
node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2)
node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1)
node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1)
node put_a_mask_sub_bit = bits(req.addr, 1, 1)
node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2)
node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T)
node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2)
node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1)
node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2)
node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2)
node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2)
node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3)
node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0)
node put_a_mask_bit = bits(req.addr, 0, 0)
node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0))
node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit)
node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq)
node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T)
node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit)
node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1)
node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1)
node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit)
node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2)
node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2)
node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit)
node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3)
node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3)
node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit)
node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4)
node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4)
node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit)
node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5)
node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5)
node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit)
node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6)
node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6)
node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit)
node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7)
node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7)
node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc)
node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2)
node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo)
node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4)
node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6)
node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo)
node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo)
connect put.mask, _put_a_mask_T
connect put.data, req.data
connect put.corrupt, UInt<1>(0h0)
wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE.corrupt, UInt<1>(0h0)
connect _atomics_WIRE.data, UInt<64>(0h0)
connect _atomics_WIRE.mask, UInt<8>(0h0)
connect _atomics_WIRE.address, UInt<32>(0h0)
connect _atomics_WIRE.source, UInt<4>(0h0)
connect _atomics_WIRE.size, UInt<4>(0h0)
connect _atomics_WIRE.param, UInt<3>(0h0)
connect _atomics_WIRE.opcode, UInt<3>(0h0)
node _atomics_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_1 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1)
node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2)
node _atomics_legal_T_4 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_5 = cvt(_atomics_legal_T_4)
node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6)
node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_9 = and(_atomics_legal_T_3, _atomics_legal_T_8)
node atomics_legal = or(UInt<1>(0h0), _atomics_legal_T_9)
wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a.opcode, UInt<2>(0h3)
connect atomics_a.param, UInt<3>(0h3)
connect atomics_a.size, req.uop.mem_size
connect atomics_a.source, UInt<4>(0h9)
connect atomics_a.address, req.addr
node _atomics_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0)
node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount)
node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0)
node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2)
node atomics_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit)
node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2)
node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T)
node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit)
node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2)
node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1)
node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1)
node atomics_a_mask_sub_bit = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2)
node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T)
node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2)
node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1)
node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2)
node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2)
node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2)
node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3)
node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0)
node atomics_a_mask_bit = bits(req.addr, 0, 0)
node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0))
node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq)
node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T)
node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1)
node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1)
node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2)
node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2)
node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3)
node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3)
node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4)
node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4)
node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5)
node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5)
node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6)
node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6)
node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7)
node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7)
node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc)
node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2)
node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo)
node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4)
node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6)
node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo)
node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo)
connect atomics_a.mask, _atomics_a_mask_T
connect atomics_a.data, req.data
connect atomics_a.corrupt, UInt<1>(0h0)
node _atomics_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_11 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_12 = and(_atomics_legal_T_10, _atomics_legal_T_11)
node _atomics_legal_T_13 = or(UInt<1>(0h0), _atomics_legal_T_12)
node _atomics_legal_T_14 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_15 = cvt(_atomics_legal_T_14)
node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16)
node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_19 = and(_atomics_legal_T_13, _atomics_legal_T_18)
node atomics_legal_1 = or(UInt<1>(0h0), _atomics_legal_T_19)
wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_1.opcode, UInt<2>(0h3)
connect atomics_a_1.param, UInt<3>(0h0)
connect atomics_a_1.size, req.uop.mem_size
connect atomics_a_1.source, UInt<4>(0h9)
connect atomics_a_1.address, req.addr
node _atomics_a_mask_sizeOH_T_3 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0)
node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1)
node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0)
node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2)
node atomics_a_mask_sub_sub_bit_1 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1)
node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1)
node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2)
node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1)
node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1)
node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3)
node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1)
node atomics_a_mask_sub_bit_1 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1)
node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4)
node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1)
node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5)
node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1)
node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6)
node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1)
node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7)
node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0)
node atomics_a_mask_bit_1 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0))
node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8)
node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8)
node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9)
node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9)
node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10)
node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10)
node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11)
node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11)
node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12)
node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12)
node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13)
node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13)
node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14)
node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14)
node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15)
node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15)
node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8)
node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10)
node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1)
node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12)
node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14)
node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1)
node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1)
connect atomics_a_1.mask, _atomics_a_mask_T_1
connect atomics_a_1.data, req.data
connect atomics_a_1.corrupt, UInt<1>(0h0)
node _atomics_legal_T_20 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_21 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_22 = and(_atomics_legal_T_20, _atomics_legal_T_21)
node _atomics_legal_T_23 = or(UInt<1>(0h0), _atomics_legal_T_22)
node _atomics_legal_T_24 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_25 = cvt(_atomics_legal_T_24)
node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26)
node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_29 = and(_atomics_legal_T_23, _atomics_legal_T_28)
node atomics_legal_2 = or(UInt<1>(0h0), _atomics_legal_T_29)
wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_2.opcode, UInt<2>(0h3)
connect atomics_a_2.param, UInt<3>(0h1)
connect atomics_a_2.size, req.uop.mem_size
connect atomics_a_2.source, UInt<4>(0h9)
connect atomics_a_2.address, req.addr
node _atomics_a_mask_sizeOH_T_6 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0)
node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2)
node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0)
node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_2 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2)
node atomics_a_mask_sub_sub_bit_2 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2)
node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2)
node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4)
node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2)
node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2)
node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5)
node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1)
node atomics_a_mask_sub_bit_2 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2)
node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8)
node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2)
node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9)
node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2)
node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10)
node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2)
node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11)
node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0)
node atomics_a_mask_bit_2 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0))
node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16)
node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16)
node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17)
node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17)
node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18)
node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18)
node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19)
node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19)
node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20)
node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20)
node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21)
node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21)
node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22)
node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22)
node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23)
node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23)
node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16)
node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18)
node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2)
node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20)
node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22)
node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2)
node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2)
connect atomics_a_2.mask, _atomics_a_mask_T_2
connect atomics_a_2.data, req.data
connect atomics_a_2.corrupt, UInt<1>(0h0)
node _atomics_legal_T_30 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_31 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_32 = and(_atomics_legal_T_30, _atomics_legal_T_31)
node _atomics_legal_T_33 = or(UInt<1>(0h0), _atomics_legal_T_32)
node _atomics_legal_T_34 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_35 = cvt(_atomics_legal_T_34)
node _atomics_legal_T_36 = and(_atomics_legal_T_35, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_37 = asSInt(_atomics_legal_T_36)
node _atomics_legal_T_38 = eq(_atomics_legal_T_37, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_39 = and(_atomics_legal_T_33, _atomics_legal_T_38)
node atomics_legal_3 = or(UInt<1>(0h0), _atomics_legal_T_39)
wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_3.opcode, UInt<2>(0h3)
connect atomics_a_3.param, UInt<3>(0h2)
connect atomics_a_3.size, req.uop.mem_size
connect atomics_a_3.source, UInt<4>(0h9)
connect atomics_a_3.address, req.addr
node _atomics_a_mask_sizeOH_T_9 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0)
node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3)
node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0)
node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_3 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2)
node atomics_a_mask_sub_sub_bit_3 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3)
node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3)
node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6)
node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3)
node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3)
node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7)
node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1)
node atomics_a_mask_sub_bit_3 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3)
node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12)
node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3)
node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13)
node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3)
node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14)
node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3)
node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15)
node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0)
node atomics_a_mask_bit_3 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0))
node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24)
node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24)
node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25)
node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25)
node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26)
node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26)
node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27)
node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27)
node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28)
node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28)
node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29)
node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29)
node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30)
node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30)
node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31)
node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31)
node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24)
node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26)
node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3)
node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28)
node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30)
node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3)
node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3)
connect atomics_a_3.mask, _atomics_a_mask_T_3
connect atomics_a_3.data, req.data
connect atomics_a_3.corrupt, UInt<1>(0h0)
node _atomics_legal_T_40 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_41 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_42 = and(_atomics_legal_T_40, _atomics_legal_T_41)
node _atomics_legal_T_43 = or(UInt<1>(0h0), _atomics_legal_T_42)
node _atomics_legal_T_44 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_45 = cvt(_atomics_legal_T_44)
node _atomics_legal_T_46 = and(_atomics_legal_T_45, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_47 = asSInt(_atomics_legal_T_46)
node _atomics_legal_T_48 = eq(_atomics_legal_T_47, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_49 = and(_atomics_legal_T_43, _atomics_legal_T_48)
node atomics_legal_4 = or(UInt<1>(0h0), _atomics_legal_T_49)
wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_4.opcode, UInt<2>(0h2)
connect atomics_a_4.param, UInt<3>(0h4)
connect atomics_a_4.size, req.uop.mem_size
connect atomics_a_4.source, UInt<4>(0h9)
connect atomics_a_4.address, req.addr
node _atomics_a_mask_sizeOH_T_12 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0)
node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4)
node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0)
node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_4 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2)
node atomics_a_mask_sub_sub_bit_4 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4)
node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4)
node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8)
node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4)
node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4)
node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9)
node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1)
node atomics_a_mask_sub_bit_4 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4)
node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16)
node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4)
node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17)
node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4)
node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18)
node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4)
node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19)
node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0)
node atomics_a_mask_bit_4 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0))
node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32)
node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32)
node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33)
node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33)
node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34)
node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34)
node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35)
node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35)
node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36)
node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36)
node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37)
node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37)
node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38)
node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38)
node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39)
node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39)
node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32)
node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34)
node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4)
node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36)
node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38)
node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4)
node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4)
connect atomics_a_4.mask, _atomics_a_mask_T_4
connect atomics_a_4.data, req.data
connect atomics_a_4.corrupt, UInt<1>(0h0)
node _atomics_legal_T_50 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_51 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_52 = and(_atomics_legal_T_50, _atomics_legal_T_51)
node _atomics_legal_T_53 = or(UInt<1>(0h0), _atomics_legal_T_52)
node _atomics_legal_T_54 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_55 = cvt(_atomics_legal_T_54)
node _atomics_legal_T_56 = and(_atomics_legal_T_55, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_57 = asSInt(_atomics_legal_T_56)
node _atomics_legal_T_58 = eq(_atomics_legal_T_57, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_59 = and(_atomics_legal_T_53, _atomics_legal_T_58)
node atomics_legal_5 = or(UInt<1>(0h0), _atomics_legal_T_59)
wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_5.opcode, UInt<2>(0h2)
connect atomics_a_5.param, UInt<3>(0h0)
connect atomics_a_5.size, req.uop.mem_size
connect atomics_a_5.source, UInt<4>(0h9)
connect atomics_a_5.address, req.addr
node _atomics_a_mask_sizeOH_T_15 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0)
node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5)
node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0)
node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_5 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2)
node atomics_a_mask_sub_sub_bit_5 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5)
node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5)
node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10)
node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5)
node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5)
node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11)
node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1)
node atomics_a_mask_sub_bit_5 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5)
node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20)
node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5)
node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21)
node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5)
node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22)
node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5)
node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23)
node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0)
node atomics_a_mask_bit_5 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0))
node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40)
node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40)
node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41)
node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41)
node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42)
node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42)
node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43)
node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43)
node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44)
node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44)
node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45)
node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45)
node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46)
node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46)
node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47)
node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47)
node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40)
node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42)
node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5)
node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44)
node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46)
node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5)
node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5)
connect atomics_a_5.mask, _atomics_a_mask_T_5
connect atomics_a_5.data, req.data
connect atomics_a_5.corrupt, UInt<1>(0h0)
node _atomics_legal_T_60 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_61 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_62 = and(_atomics_legal_T_60, _atomics_legal_T_61)
node _atomics_legal_T_63 = or(UInt<1>(0h0), _atomics_legal_T_62)
node _atomics_legal_T_64 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_65 = cvt(_atomics_legal_T_64)
node _atomics_legal_T_66 = and(_atomics_legal_T_65, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_67 = asSInt(_atomics_legal_T_66)
node _atomics_legal_T_68 = eq(_atomics_legal_T_67, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_69 = and(_atomics_legal_T_63, _atomics_legal_T_68)
node atomics_legal_6 = or(UInt<1>(0h0), _atomics_legal_T_69)
wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_6.opcode, UInt<2>(0h2)
connect atomics_a_6.param, UInt<3>(0h1)
connect atomics_a_6.size, req.uop.mem_size
connect atomics_a_6.source, UInt<4>(0h9)
connect atomics_a_6.address, req.addr
node _atomics_a_mask_sizeOH_T_18 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0)
node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6)
node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0)
node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_6 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2)
node atomics_a_mask_sub_sub_bit_6 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6)
node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6)
node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12)
node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6)
node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6)
node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13)
node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1)
node atomics_a_mask_sub_bit_6 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6)
node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24)
node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6)
node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25)
node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6)
node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26)
node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6)
node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27)
node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0)
node atomics_a_mask_bit_6 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0))
node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48)
node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48)
node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49)
node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49)
node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50)
node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50)
node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51)
node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51)
node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52)
node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52)
node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53)
node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53)
node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54)
node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54)
node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55)
node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55)
node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48)
node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50)
node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6)
node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52)
node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54)
node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6)
node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6)
connect atomics_a_6.mask, _atomics_a_mask_T_6
connect atomics_a_6.data, req.data
connect atomics_a_6.corrupt, UInt<1>(0h0)
node _atomics_legal_T_70 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_71 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_72 = and(_atomics_legal_T_70, _atomics_legal_T_71)
node _atomics_legal_T_73 = or(UInt<1>(0h0), _atomics_legal_T_72)
node _atomics_legal_T_74 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_75 = cvt(_atomics_legal_T_74)
node _atomics_legal_T_76 = and(_atomics_legal_T_75, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_77 = asSInt(_atomics_legal_T_76)
node _atomics_legal_T_78 = eq(_atomics_legal_T_77, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_79 = and(_atomics_legal_T_73, _atomics_legal_T_78)
node atomics_legal_7 = or(UInt<1>(0h0), _atomics_legal_T_79)
wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_7.opcode, UInt<2>(0h2)
connect atomics_a_7.param, UInt<3>(0h2)
connect atomics_a_7.size, req.uop.mem_size
connect atomics_a_7.source, UInt<4>(0h9)
connect atomics_a_7.address, req.addr
node _atomics_a_mask_sizeOH_T_21 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0)
node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7)
node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0)
node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_7 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2)
node atomics_a_mask_sub_sub_bit_7 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7)
node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7)
node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14)
node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7)
node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7)
node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15)
node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1)
node atomics_a_mask_sub_bit_7 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7)
node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28)
node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7)
node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29)
node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7)
node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30)
node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7)
node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31)
node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0)
node atomics_a_mask_bit_7 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0))
node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56)
node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56)
node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57)
node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57)
node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58)
node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58)
node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59)
node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59)
node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60)
node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60)
node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61)
node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61)
node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62)
node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62)
node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63)
node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63)
node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56)
node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58)
node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7)
node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60)
node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62)
node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7)
node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7)
connect atomics_a_7.mask, _atomics_a_mask_T_7
connect atomics_a_7.data, req.data
connect atomics_a_7.corrupt, UInt<1>(0h0)
node _atomics_legal_T_80 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_81 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_82 = and(_atomics_legal_T_80, _atomics_legal_T_81)
node _atomics_legal_T_83 = or(UInt<1>(0h0), _atomics_legal_T_82)
node _atomics_legal_T_84 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_85 = cvt(_atomics_legal_T_84)
node _atomics_legal_T_86 = and(_atomics_legal_T_85, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_87 = asSInt(_atomics_legal_T_86)
node _atomics_legal_T_88 = eq(_atomics_legal_T_87, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_89 = and(_atomics_legal_T_83, _atomics_legal_T_88)
node atomics_legal_8 = or(UInt<1>(0h0), _atomics_legal_T_89)
wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_8.opcode, UInt<2>(0h2)
connect atomics_a_8.param, UInt<3>(0h3)
connect atomics_a_8.size, req.uop.mem_size
connect atomics_a_8.source, UInt<4>(0h9)
connect atomics_a_8.address, req.addr
node _atomics_a_mask_sizeOH_T_24 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0)
node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8)
node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0)
node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_8 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2)
node atomics_a_mask_sub_sub_bit_8 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8)
node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8)
node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16)
node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8)
node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8)
node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17)
node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1)
node atomics_a_mask_sub_bit_8 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8)
node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32)
node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8)
node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33)
node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8)
node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34)
node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8)
node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35)
node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0)
node atomics_a_mask_bit_8 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0))
node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64)
node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64)
node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65)
node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65)
node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66)
node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66)
node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67)
node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67)
node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68)
node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68)
node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69)
node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69)
node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70)
node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70)
node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71)
node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71)
node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64)
node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66)
node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8)
node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68)
node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70)
node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8)
node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8)
connect atomics_a_8.mask, _atomics_a_mask_T_8
connect atomics_a_8.data, req.data
connect atomics_a_8.corrupt, UInt<1>(0h0)
node _atomics_T = eq(UInt<3>(0h4), req.uop.mem_cmd)
node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE)
node _atomics_T_2 = eq(UInt<4>(0h9), req.uop.mem_cmd)
node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1)
node _atomics_T_4 = eq(UInt<4>(0ha), req.uop.mem_cmd)
node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3)
node _atomics_T_6 = eq(UInt<4>(0hb), req.uop.mem_cmd)
node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5)
node _atomics_T_8 = eq(UInt<4>(0h8), req.uop.mem_cmd)
node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7)
node _atomics_T_10 = eq(UInt<4>(0hc), req.uop.mem_cmd)
node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9)
node _atomics_T_12 = eq(UInt<4>(0hd), req.uop.mem_cmd)
node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11)
node _atomics_T_14 = eq(UInt<4>(0he), req.uop.mem_cmd)
node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13)
node _atomics_T_16 = eq(UInt<4>(0hf), req.uop.mem_cmd)
node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15)
node _T = eq(state, UInt<2>(0h0))
node _T_1 = neq(req.uop.mem_cmd, UInt<3>(0h7))
node _T_2 = or(_T, _T_1)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:441 assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_mem_access_valid_T = eq(state, UInt<2>(0h1))
connect io.mem_access.valid, _io_mem_access_valid_T
node _io_mem_access_bits_T = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _io_mem_access_bits_T_1 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _io_mem_access_bits_T_2 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _io_mem_access_bits_T_3 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _io_mem_access_bits_T_4 = or(_io_mem_access_bits_T, _io_mem_access_bits_T_1)
node _io_mem_access_bits_T_5 = or(_io_mem_access_bits_T_4, _io_mem_access_bits_T_2)
node _io_mem_access_bits_T_6 = or(_io_mem_access_bits_T_5, _io_mem_access_bits_T_3)
node _io_mem_access_bits_T_7 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _io_mem_access_bits_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _io_mem_access_bits_T_9 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _io_mem_access_bits_T_10 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _io_mem_access_bits_T_11 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _io_mem_access_bits_T_12 = or(_io_mem_access_bits_T_7, _io_mem_access_bits_T_8)
node _io_mem_access_bits_T_13 = or(_io_mem_access_bits_T_12, _io_mem_access_bits_T_9)
node _io_mem_access_bits_T_14 = or(_io_mem_access_bits_T_13, _io_mem_access_bits_T_10)
node _io_mem_access_bits_T_15 = or(_io_mem_access_bits_T_14, _io_mem_access_bits_T_11)
node _io_mem_access_bits_T_16 = or(_io_mem_access_bits_T_6, _io_mem_access_bits_T_15)
node _io_mem_access_bits_T_17 = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _io_mem_access_bits_T_18 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _io_mem_access_bits_T_19 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _io_mem_access_bits_T_20 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _io_mem_access_bits_T_21 = or(_io_mem_access_bits_T_17, _io_mem_access_bits_T_18)
node _io_mem_access_bits_T_22 = or(_io_mem_access_bits_T_21, _io_mem_access_bits_T_19)
node _io_mem_access_bits_T_23 = or(_io_mem_access_bits_T_22, _io_mem_access_bits_T_20)
node _io_mem_access_bits_T_24 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _io_mem_access_bits_T_25 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _io_mem_access_bits_T_26 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _io_mem_access_bits_T_27 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _io_mem_access_bits_T_28 = or(_io_mem_access_bits_T_24, _io_mem_access_bits_T_25)
node _io_mem_access_bits_T_29 = or(_io_mem_access_bits_T_28, _io_mem_access_bits_T_26)
node _io_mem_access_bits_T_30 = or(_io_mem_access_bits_T_29, _io_mem_access_bits_T_27)
node _io_mem_access_bits_T_31 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _io_mem_access_bits_T_32 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _io_mem_access_bits_T_33 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _io_mem_access_bits_T_34 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _io_mem_access_bits_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _io_mem_access_bits_T_36 = or(_io_mem_access_bits_T_31, _io_mem_access_bits_T_32)
node _io_mem_access_bits_T_37 = or(_io_mem_access_bits_T_36, _io_mem_access_bits_T_33)
node _io_mem_access_bits_T_38 = or(_io_mem_access_bits_T_37, _io_mem_access_bits_T_34)
node _io_mem_access_bits_T_39 = or(_io_mem_access_bits_T_38, _io_mem_access_bits_T_35)
node _io_mem_access_bits_T_40 = or(_io_mem_access_bits_T_30, _io_mem_access_bits_T_39)
node _io_mem_access_bits_T_41 = or(_io_mem_access_bits_T_23, _io_mem_access_bits_T_40)
node _io_mem_access_bits_T_42 = mux(_io_mem_access_bits_T_41, get, put)
node _io_mem_access_bits_T_43 = mux(_io_mem_access_bits_T_16, atomics, _io_mem_access_bits_T_42)
connect io.mem_access.bits, _io_mem_access_bits_T_43
node _send_resp_T = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _send_resp_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _send_resp_T_2 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _send_resp_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _send_resp_T_4 = or(_send_resp_T, _send_resp_T_1)
node _send_resp_T_5 = or(_send_resp_T_4, _send_resp_T_2)
node _send_resp_T_6 = or(_send_resp_T_5, _send_resp_T_3)
node _send_resp_T_7 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _send_resp_T_8 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _send_resp_T_9 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _send_resp_T_10 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _send_resp_T_11 = or(_send_resp_T_7, _send_resp_T_8)
node _send_resp_T_12 = or(_send_resp_T_11, _send_resp_T_9)
node _send_resp_T_13 = or(_send_resp_T_12, _send_resp_T_10)
node _send_resp_T_14 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _send_resp_T_15 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _send_resp_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _send_resp_T_17 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _send_resp_T_18 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _send_resp_T_19 = or(_send_resp_T_14, _send_resp_T_15)
node _send_resp_T_20 = or(_send_resp_T_19, _send_resp_T_16)
node _send_resp_T_21 = or(_send_resp_T_20, _send_resp_T_17)
node _send_resp_T_22 = or(_send_resp_T_21, _send_resp_T_18)
node _send_resp_T_23 = or(_send_resp_T_13, _send_resp_T_22)
node send_resp = or(_send_resp_T_6, _send_resp_T_23)
node _io_resp_valid_T = eq(state, UInt<2>(0h3))
node _io_resp_valid_T_1 = and(_io_resp_valid_T, send_resp)
connect io.resp.valid, _io_resp_valid_T_1
connect io.resp.bits.uop, req.uop
node _io_resp_bits_data_shifted_T = bits(req.addr, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(grant_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(grant_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(req.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(grant_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(req.addr, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(req.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(req.addr, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(req.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, req.is_hella
node _T_6 = and(io.req.ready, io.req.valid)
when _T_6 :
connect req, io.req.bits
connect state, UInt<2>(0h1)
node _T_7 = and(io.mem_access.ready, io.mem_access.valid)
when _T_7 :
connect state, UInt<2>(0h2)
node _T_8 = eq(state, UInt<2>(0h2))
node _T_9 = and(_T_8, io.mem_ack.valid)
when _T_9 :
connect state, UInt<2>(0h3)
node _T_10 = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _T_11 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _T_12 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _T_13 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _T_14 = or(_T_10, _T_11)
node _T_15 = or(_T_14, _T_12)
node _T_16 = or(_T_15, _T_13)
node _T_17 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _T_18 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _T_19 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _T_20 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _T_21 = or(_T_17, _T_18)
node _T_22 = or(_T_21, _T_19)
node _T_23 = or(_T_22, _T_20)
node _T_24 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _T_25 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _T_26 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _T_27 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _T_28 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _T_29 = or(_T_24, _T_25)
node _T_30 = or(_T_29, _T_26)
node _T_31 = or(_T_30, _T_27)
node _T_32 = or(_T_31, _T_28)
node _T_33 = or(_T_23, _T_32)
node _T_34 = or(_T_16, _T_33)
when _T_34 :
node grant_word_shift = cat(UInt<1>(0h0), UInt<6>(0h0))
node _grant_word_T = dshr(io.mem_ack.bits.data, grant_word_shift)
node _grant_word_T_1 = bits(_grant_word_T, 63, 0)
connect grant_word, _grant_word_T_1
node _T_35 = eq(state, UInt<2>(0h3))
when _T_35 :
node _T_36 = eq(send_resp, UInt<1>(0h0))
node _T_37 = and(io.resp.ready, io.resp.valid)
node _T_38 = or(_T_36, _T_37)
when _T_38 :
connect state, UInt<2>(0h0) | module BoomIOMSHR_1( // @[mshrs.scala:389:7]
input clock, // @[mshrs.scala:389:7]
input reset, // @[mshrs.scala:389:7]
output io_req_ready, // @[mshrs.scala:392:14]
input io_req_valid, // @[mshrs.scala:392:14]
input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:392:14]
input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_rvc, // @[mshrs.scala:392:14]
input [33:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:392:14]
input io_req_bits_uop_iq_type_0, // @[mshrs.scala:392:14]
input io_req_bits_uop_iq_type_1, // @[mshrs.scala:392:14]
input io_req_bits_uop_iq_type_2, // @[mshrs.scala:392:14]
input io_req_bits_uop_iq_type_3, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_0, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_1, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_2, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_3, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_4, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_5, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_6, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_7, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_8, // @[mshrs.scala:392:14]
input io_req_bits_uop_fu_code_9, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_issued, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:392:14]
input io_req_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:392:14]
input io_req_bits_uop_dis_col_sel, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_br_mask, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_br_tag, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_br_type, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_sfb, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_fence, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_fencei, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_sfence, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_amo, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_eret, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_rocc, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_mov, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:392:14]
input io_req_bits_uop_edge_inst, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:392:14]
input io_req_bits_uop_taken, // @[mshrs.scala:392:14]
input io_req_bits_uop_imm_rename, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_imm_sel, // @[mshrs.scala:392:14]
input [4:0] io_req_bits_uop_pimm, // @[mshrs.scala:392:14]
input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_op1_sel, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_op2_sel, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_wen, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_toint, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_fma, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_div, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_ctrl_vec, // @[mshrs.scala:392:14]
input [4:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_pdst, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_prs1, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_prs2, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_prs3, // @[mshrs.scala:392:14]
input [3:0] io_req_bits_uop_ppred, // @[mshrs.scala:392:14]
input io_req_bits_uop_prs1_busy, // @[mshrs.scala:392:14]
input io_req_bits_uop_prs2_busy, // @[mshrs.scala:392:14]
input io_req_bits_uop_prs3_busy, // @[mshrs.scala:392:14]
input io_req_bits_uop_ppred_busy, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:392:14]
input io_req_bits_uop_exception, // @[mshrs.scala:392:14]
input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:392:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:392:14]
input io_req_bits_uop_mem_signed, // @[mshrs.scala:392:14]
input io_req_bits_uop_uses_ldq, // @[mshrs.scala:392:14]
input io_req_bits_uop_uses_stq, // @[mshrs.scala:392:14]
input io_req_bits_uop_is_unique, // @[mshrs.scala:392:14]
input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_csr_cmd, // @[mshrs.scala:392:14]
input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:392:14]
input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:392:14]
input io_req_bits_uop_frs3_en, // @[mshrs.scala:392:14]
input io_req_bits_uop_fcn_dw, // @[mshrs.scala:392:14]
input [4:0] io_req_bits_uop_fcn_op, // @[mshrs.scala:392:14]
input io_req_bits_uop_fp_val, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_fp_rm, // @[mshrs.scala:392:14]
input [1:0] io_req_bits_uop_fp_typ, // @[mshrs.scala:392:14]
input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:392:14]
input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:392:14]
input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:392:14]
input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:392:14]
input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:392:14]
input [2:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:392:14]
input [33:0] io_req_bits_addr, // @[mshrs.scala:392:14]
input [63:0] io_req_bits_data, // @[mshrs.scala:392:14]
input io_req_bits_is_hella, // @[mshrs.scala:392:14]
input io_resp_ready, // @[mshrs.scala:392:14]
output io_resp_valid, // @[mshrs.scala:392:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:392:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:392:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_issued, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:392:14]
output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:392:14]
output io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_sfence, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_eret, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_rocc, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_mov, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:392:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:392:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:392:14]
output io_resp_bits_uop_imm_rename, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:392:14]
output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:392:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:392:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:392:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:392:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:392:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:392:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:392:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:392:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:392:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:392:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:392:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:392:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:392:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:392:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:392:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:392:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:392:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:392:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:392:14]
output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:392:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:392:14]
output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:392:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:392:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:392:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:392:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:392:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:392:14]
output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:392:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:392:14]
output io_resp_bits_is_hella, // @[mshrs.scala:392:14]
input io_mem_access_ready, // @[mshrs.scala:392:14]
output io_mem_access_valid, // @[mshrs.scala:392:14]
output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:392:14]
output [2:0] io_mem_access_bits_param, // @[mshrs.scala:392:14]
output [3:0] io_mem_access_bits_size, // @[mshrs.scala:392:14]
output [3:0] io_mem_access_bits_source, // @[mshrs.scala:392:14]
output [31:0] io_mem_access_bits_address, // @[mshrs.scala:392:14]
output [7:0] io_mem_access_bits_mask, // @[mshrs.scala:392:14]
output [63:0] io_mem_access_bits_data, // @[mshrs.scala:392:14]
input io_mem_ack_valid, // @[mshrs.scala:392:14]
input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:392:14]
input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:392:14]
input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:392:14]
input [3:0] io_mem_ack_bits_source, // @[mshrs.scala:392:14]
input [2:0] io_mem_ack_bits_sink, // @[mshrs.scala:392:14]
input io_mem_ack_bits_denied, // @[mshrs.scala:392:14]
input [63:0] io_mem_ack_bits_data, // @[mshrs.scala:392:14]
input io_mem_ack_bits_corrupt // @[mshrs.scala:392:14]
);
wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:389:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:389:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:389:7]
wire [33:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:389:7]
wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:389:7]
wire io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:389:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:389:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:389:7]
wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[mshrs.scala:389:7]
wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[mshrs.scala:389:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[mshrs.scala:389:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:389:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:389:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:389:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:389:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:389:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:389:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:389:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:389:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:389:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:389:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:389:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:389:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:389:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[mshrs.scala:389:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:389:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:389:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[mshrs.scala:389:7]
wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[mshrs.scala:389:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[mshrs.scala:389:7]
wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[mshrs.scala:389:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:389:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:389:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:389:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:389:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:389:7]
wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:389:7]
wire [33:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:389:7]
wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:389:7]
wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:389:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:389:7]
wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:389:7]
wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:389:7]
wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:389:7]
wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:389:7]
wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:389:7]
wire [3:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:389:7]
wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:389:7]
wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:389:7]
wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:389:7]
wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:389:7]
wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:389:7]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:426:46]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire atomics_corrupt = 1'h0; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:444:66]
wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:444:29]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire [6:0] grant_word_shift = 7'h0; // @[mshrs.scala:404:20]
wire [3:0] get_source = 4'h9; // @[Edges.scala:460:17]
wire [3:0] put_source = 4'h9; // @[Edges.scala:480:17]
wire [3:0] atomics_a_source = 4'h9; // @[Edges.scala:534:17]
wire [3:0] atomics_a_1_source = 4'h9; // @[Edges.scala:534:17]
wire [3:0] atomics_a_2_source = 4'h9; // @[Edges.scala:534:17]
wire [3:0] atomics_a_3_source = 4'h9; // @[Edges.scala:534:17]
wire [3:0] atomics_a_4_source = 4'h9; // @[Edges.scala:517:17]
wire [3:0] atomics_a_5_source = 4'h9; // @[Edges.scala:517:17]
wire [3:0] atomics_a_6_source = 4'h9; // @[Edges.scala:517:17]
wire [3:0] atomics_a_7_source = 4'h9; // @[Edges.scala:517:17]
wire [3:0] atomics_a_8_source = 4'h9; // @[Edges.scala:517:17]
wire [3:0] _io_mem_access_bits_T_42_source = 4'h9; // @[mshrs.scala:444:66]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:426:46]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:426:46]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:444:66]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_8 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_9 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_18 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_19 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_1 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_20 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_21 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_22 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_23 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_28 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_29 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_2 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_30 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_31 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_32 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_33 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_38 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_39 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_3 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_40 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_48 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_49 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_4 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_50 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_51 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_52 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_53 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_58 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_5 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_68 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_69 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_6 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_70 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_71 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_72 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_73 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_78 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_79 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_7 = 1'h1; // @[Parameters.scala:686:26]
wire _atomics_legal_T_80 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_81 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_82 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_83 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_88 = 1'h1; // @[Parameters.scala:137:59]
wire _atomics_legal_T_89 = 1'h1; // @[Parameters.scala:684:54]
wire atomics_legal_8 = 1'h1; // @[Parameters.scala:686:26]
wire [34:0] _atomics_legal_T_6 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_7 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_16 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_17 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_26 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_27 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_36 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_37 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_46 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_47 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_56 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_57 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_66 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_67 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_76 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_77 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_86 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _atomics_legal_T_87 = 35'h0; // @[Parameters.scala:137:46]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[mshrs.scala:426:46]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[mshrs.scala:426:46]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:426:46]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:426:46]
wire [3:0] _atomics_WIRE_source = 4'h0; // @[mshrs.scala:426:46]
wire _io_req_ready_T; // @[mshrs.scala:414:25]
wire _io_resp_valid_T_1; // @[mshrs.scala:448:43]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_mem_access_valid_T; // @[mshrs.scala:443:32]
wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:444:29]
wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:444:29]
wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:444:29]
wire [3:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:444:29]
wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:444:29]
wire [7:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:444:29]
wire [63:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:444:29]
wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[mshrs.scala:389:7, :405:10]
wire io_req_ready_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:389:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:389:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:389:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:389:7]
wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:389:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:389:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:389:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:389:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:389:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:389:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:389:7]
wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:389:7]
wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:389:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:389:7]
wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:389:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:389:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:389:7]
wire io_resp_valid_0; // @[mshrs.scala:389:7]
wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:389:7]
wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:389:7]
wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:389:7]
wire [3:0] io_mem_access_bits_source_0; // @[mshrs.scala:389:7]
wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:389:7]
wire [7:0] io_mem_access_bits_mask_0; // @[mshrs.scala:389:7]
wire [63:0] io_mem_access_bits_data_0; // @[mshrs.scala:389:7]
wire io_mem_access_valid_0; // @[mshrs.scala:389:7]
reg [31:0] req_uop_inst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:389:7, :408:16]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_rvc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:389:7, :408:16]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iq_type_0; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iq_type_0_0 = req_uop_iq_type_0; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iq_type_1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iq_type_1_0 = req_uop_iq_type_1; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iq_type_2; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iq_type_2_0 = req_uop_iq_type_2; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iq_type_3; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iq_type_3_0 = req_uop_iq_type_3; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_0; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_0_0 = req_uop_fu_code_0; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_1_0 = req_uop_fu_code_1; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_2; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_2_0 = req_uop_fu_code_2; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_3; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_3_0 = req_uop_fu_code_3; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_4; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_4_0 = req_uop_fu_code_4; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_5; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_5_0 = req_uop_fu_code_5; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_6; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_6_0 = req_uop_fu_code_6; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_7; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_7_0 = req_uop_fu_code_7; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_8; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_8_0 = req_uop_fu_code_8; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fu_code_9; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fu_code_9_0 = req_uop_fu_code_9; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_issued; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_issued_0 = req_uop_iw_issued; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_issued_partial_agen_0 = req_uop_iw_issued_partial_agen; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_issued_partial_dgen_0 = req_uop_iw_issued_partial_dgen; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_p1_speculative_child; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_p1_speculative_child_0 = req_uop_iw_p1_speculative_child; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_p2_speculative_child; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_p2_speculative_child_0 = req_uop_iw_p2_speculative_child; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_p1_bypass_hint_0 = req_uop_iw_p1_bypass_hint; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_p2_bypass_hint_0 = req_uop_iw_p2_bypass_hint; // @[mshrs.scala:389:7, :408:16]
reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_iw_p3_bypass_hint_0 = req_uop_iw_p3_bypass_hint; // @[mshrs.scala:389:7, :408:16]
reg req_uop_dis_col_sel; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_dis_col_sel_0 = req_uop_dis_col_sel; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_br_type; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_br_type_0 = req_uop_br_type; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_sfb; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_fence; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_fencei; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_sfence; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_sfence_0 = req_uop_is_sfence; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_amo; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_eret; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_eret_0 = req_uop_is_eret; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_rocc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_rocc_0 = req_uop_is_rocc; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_mov; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_mov_0 = req_uop_is_mov; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:389:7, :408:16]
reg req_uop_edge_inst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:389:7, :408:16]
reg req_uop_taken; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:389:7, :408:16]
reg req_uop_imm_rename; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_imm_rename_0 = req_uop_imm_rename; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_imm_sel; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_imm_sel_0 = req_uop_imm_sel; // @[mshrs.scala:389:7, :408:16]
reg [4:0] req_uop_pimm; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_pimm_0 = req_uop_pimm; // @[mshrs.scala:389:7, :408:16]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_op1_sel; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_op1_sel_0 = req_uop_op1_sel; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_op2_sel; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_op2_sel_0 = req_uop_op2_sel; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_ldst_0 = req_uop_fp_ctrl_ldst; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_wen; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_wen_0 = req_uop_fp_ctrl_wen; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_ren1_0 = req_uop_fp_ctrl_ren1; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_ren2_0 = req_uop_fp_ctrl_ren2; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_ren3_0 = req_uop_fp_ctrl_ren3; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_swap12_0 = req_uop_fp_ctrl_swap12; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_swap23_0 = req_uop_fp_ctrl_swap23; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_typeTagIn_0 = req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_typeTagOut_0 = req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_fromint_0 = req_uop_fp_ctrl_fromint; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_toint; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_toint_0 = req_uop_fp_ctrl_toint; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_fastpipe_0 = req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_fma; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_fma_0 = req_uop_fp_ctrl_fma; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_div; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_div_0 = req_uop_fp_ctrl_div; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_sqrt_0 = req_uop_fp_ctrl_sqrt; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_wflags_0 = req_uop_fp_ctrl_wflags; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_ctrl_vec; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_ctrl_vec_0 = req_uop_fp_ctrl_vec; // @[mshrs.scala:389:7, :408:16]
reg [4:0] req_uop_rob_idx; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_pdst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_prs1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_prs2; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_prs3; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:389:7, :408:16]
reg [3:0] req_uop_ppred; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:389:7, :408:16]
reg req_uop_prs1_busy; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:389:7, :408:16]
reg req_uop_prs2_busy; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:389:7, :408:16]
reg req_uop_prs3_busy; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:389:7, :408:16]
reg req_uop_ppred_busy; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:389:7, :408:16]
reg req_uop_exception; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:389:7, :408:16]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:389:7, :408:16]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:389:7, :408:16]
wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18]
reg req_uop_mem_signed; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:389:7, :408:16]
reg req_uop_uses_ldq; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:389:7, :408:16]
reg req_uop_uses_stq; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:389:7, :408:16]
reg req_uop_is_unique; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:389:7, :408:16]
reg req_uop_flush_on_commit; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_csr_cmd_0 = req_uop_csr_cmd; // @[mshrs.scala:389:7, :408:16]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_ldst; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:389:7, :408:16]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:389:7, :408:16]
reg req_uop_frs3_en; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fcn_dw; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fcn_dw_0 = req_uop_fcn_dw; // @[mshrs.scala:389:7, :408:16]
reg [4:0] req_uop_fcn_op; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fcn_op_0 = req_uop_fcn_op; // @[mshrs.scala:389:7, :408:16]
reg req_uop_fp_val; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_fp_rm; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_rm_0 = req_uop_fp_rm; // @[mshrs.scala:389:7, :408:16]
reg [1:0] req_uop_fp_typ; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_fp_typ_0 = req_uop_fp_typ; // @[mshrs.scala:389:7, :408:16]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:389:7, :408:16]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:389:7, :408:16]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:389:7, :408:16]
reg req_uop_bp_debug_if; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:389:7, :408:16]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:389:7, :408:16]
reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:408:16]
assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:389:7, :408:16]
reg [33:0] req_addr; // @[mshrs.scala:408:16]
wire [33:0] _get_legal_T_4 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_4 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_14 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_24 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_34 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_44 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_54 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_64 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_74 = req_addr; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_84 = req_addr; // @[Parameters.scala:137:31]
reg [63:0] req_data; // @[mshrs.scala:408:16]
wire [63:0] put_data = req_data; // @[Edges.scala:480:17]
wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17]
reg req_is_hella; // @[mshrs.scala:408:16]
assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:389:7, :408:16]
reg [63:0] grant_word; // @[mshrs.scala:409:23]
reg [1:0] state; // @[mshrs.scala:413:22]
assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:413:22, :414:25]
assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:389:7, :414:25]
wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_32 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [33:0] _GEN = {req_addr[33:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [33:0] _get_legal_T_14; // @[Parameters.scala:137:31]
assign _get_legal_T_14 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_14; // @[Parameters.scala:137:31]
assign _put_legal_T_14 = _GEN; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_0 = {req_addr[33:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [33:0] _GEN_1 = {req_addr[33:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_29 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_30 = _get_legal_T_29 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_31 = _get_legal_T_30; // @[Parameters.scala:684:54, :685:42]
wire get_legal = _get_legal_T_32 | _get_legal_T_31; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_2 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_2; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_2; // @[Edges.scala:463:15, :480:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_2; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_2; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_2; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_2; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_2; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_2; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_2; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_2; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_2; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_3 = {1'h0, req_uop_mem_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_3; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_3; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_32 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_29 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_30 = _put_legal_T_29 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_31 = _put_legal_T_30; // @[Parameters.scala:684:54, :685:42]
wire put_legal = _put_legal_T_32 | _put_legal_T_31; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_45 = {1'h0, _atomics_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_55 = {1'h0, _atomics_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_85 = {1'h0, _atomics_legal_T_84}; // @[Parameters.scala:137:{31,41}]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T; // @[mshrs.scala:426:75]
assign _atomics_T = _T_17; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T; // @[package.scala:16:47]
assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47]
wire _io_mem_access_bits_T_24; // @[package.scala:16:47]
assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47]
wire _send_resp_T_7; // @[package.scala:16:47]
assign _send_resp_T_7 = _T_17; // @[package.scala:16:47]
wire [2:0] _GEN_4 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:426:75]
assign _atomics_T_1_opcode = _GEN_4; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_1_param; // @[mshrs.scala:426:75]
assign _atomics_T_1_param = _GEN_4; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire [3:0] _atomics_T_1_source = _atomics_T ? 4'h9 : 4'h0; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_2; // @[mshrs.scala:426:75]
assign _atomics_T_2 = _T_18; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_1; // @[package.scala:16:47]
assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47]
wire _io_mem_access_bits_T_25; // @[package.scala:16:47]
assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47]
wire _send_resp_T_8; // @[package.scala:16:47]
assign _send_resp_T_8 = _T_18; // @[package.scala:16:47]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire [3:0] _atomics_T_3_source = _atomics_T_2 ? 4'h9 : _atomics_T_1_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_4; // @[mshrs.scala:426:75]
assign _atomics_T_4 = _T_19; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_2; // @[package.scala:16:47]
assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47]
wire _io_mem_access_bits_T_26; // @[package.scala:16:47]
assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47]
wire _send_resp_T_9; // @[package.scala:16:47]
assign _send_resp_T_9 = _T_19; // @[package.scala:16:47]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire [3:0] _atomics_T_5_source = _atomics_T_4 ? 4'h9 : _atomics_T_3_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_6; // @[mshrs.scala:426:75]
assign _atomics_T_6 = _T_20; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_3; // @[package.scala:16:47]
assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47]
wire _io_mem_access_bits_T_27; // @[package.scala:16:47]
assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47]
wire _send_resp_T_10; // @[package.scala:16:47]
assign _send_resp_T_10 = _T_20; // @[package.scala:16:47]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire [3:0] _atomics_T_7_source = _atomics_T_6 ? 4'h9 : _atomics_T_5_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_8; // @[mshrs.scala:426:75]
assign _atomics_T_8 = _T_24; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_7; // @[package.scala:16:47]
assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47]
wire _io_mem_access_bits_T_31; // @[package.scala:16:47]
assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47]
wire _send_resp_T_14; // @[package.scala:16:47]
assign _send_resp_T_14 = _T_24; // @[package.scala:16:47]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire [3:0] _atomics_T_9_source = _atomics_T_8 ? 4'h9 : _atomics_T_7_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_10; // @[mshrs.scala:426:75]
assign _atomics_T_10 = _T_25; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_8; // @[package.scala:16:47]
assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47]
wire _io_mem_access_bits_T_32; // @[package.scala:16:47]
assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47]
wire _send_resp_T_15; // @[package.scala:16:47]
assign _send_resp_T_15 = _T_25; // @[package.scala:16:47]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire [3:0] _atomics_T_11_source = _atomics_T_10 ? 4'h9 : _atomics_T_9_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_12; // @[mshrs.scala:426:75]
assign _atomics_T_12 = _T_26; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_9; // @[package.scala:16:47]
assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47]
wire _io_mem_access_bits_T_33; // @[package.scala:16:47]
assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47]
wire _send_resp_T_16; // @[package.scala:16:47]
assign _send_resp_T_16 = _T_26; // @[package.scala:16:47]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire [3:0] _atomics_T_13_source = _atomics_T_12 ? 4'h9 : _atomics_T_11_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_14; // @[mshrs.scala:426:75]
assign _atomics_T_14 = _T_27; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_10; // @[package.scala:16:47]
assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47]
wire _io_mem_access_bits_T_34; // @[package.scala:16:47]
assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47]
wire _send_resp_T_17; // @[package.scala:16:47]
assign _send_resp_T_17 = _T_27; // @[package.scala:16:47]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:426:75]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:426:75]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire [3:0] _atomics_T_15_source = _atomics_T_14 ? 4'h9 : _atomics_T_13_source; // @[mshrs.scala:426:75]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:408:16, :426:75]
wire _atomics_T_16; // @[mshrs.scala:426:75]
assign _atomics_T_16 = _T_28; // @[mshrs.scala:426:75]
wire _io_mem_access_bits_T_11; // @[package.scala:16:47]
assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47]
wire _io_mem_access_bits_T_35; // @[package.scala:16:47]
assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47]
wire _send_resp_T_18; // @[package.scala:16:47]
assign _send_resp_T_18 = _T_28; // @[package.scala:16:47]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:426:75]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:426:75]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire [3:0] atomics_source = _atomics_T_16 ? 4'h9 : _atomics_T_15_source; // @[mshrs.scala:426:75]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<8>(0hc0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<10>(0h1c0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_98 = shr(io.in.a.bits.source, 5)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_176 = shr(io.in.a.bits.source, 5)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_229 = shr(io.in.a.bits.source, 5)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_276 = shr(io.in.a.bits.source, 5)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_325 = shr(io.in.a.bits.source, 5)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_369 = shr(io.in.a.bits.source, 5)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_413 = shr(io.in.a.bits.source, 5)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_68
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_69
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_70 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_71 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_21 = and(_T_19, _T_20)
node _T_22 = or(UInt<1>(0h0), _T_21)
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = and(_T_22, _T_27)
node _T_29 = or(UInt<1>(0h0), _T_28)
node _T_30 = and(_T_18, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_30, UInt<1>(0h1), "") : assert_2
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = or(UInt<1>(0h0), _T_36)
node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = and(_T_37, _T_42)
node _T_44 = or(UInt<1>(0h0), _T_43)
node _T_45 = and(UInt<1>(0h0), _T_44)
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_T_45, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_45, UInt<1>(0h1), "") : assert_3
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_52, UInt<1>(0h1), "") : assert_5
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(is_aligned, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_60 = asUInt(reset)
node _T_61 = eq(_T_60, UInt<1>(0h0))
when _T_61 :
node _T_62 = eq(_T_59, UInt<1>(0h0))
when _T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_59, UInt<1>(0h1), "") : assert_7
node _T_63 = not(io.in.a.bits.mask)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_64, UInt<1>(0h1), "") : assert_8
node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_68, UInt<1>(0h1), "") : assert_9
node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_72 :
node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_74 = and(UInt<1>(0h0), _T_73)
node _T_75 = or(UInt<1>(0h0), _T_74)
node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = or(UInt<1>(0h0), _T_78)
node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = and(_T_79, _T_84)
node _T_86 = or(UInt<1>(0h0), _T_85)
node _T_87 = and(_T_75, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_87, UInt<1>(0h1), "") : assert_10
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_102, UInt<1>(0h1), "") : assert_11
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_109, UInt<1>(0h1), "") : assert_13
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_116, UInt<1>(0h1), "") : assert_15
node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_120, UInt<1>(0h1), "") : assert_16
node _T_124 = not(io.in.a.bits.mask)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_125, UInt<1>(0h1), "") : assert_17
node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_129, UInt<1>(0h1), "") : assert_18
node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_133 :
node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = or(UInt<1>(0h0), _T_136)
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_137, UInt<1>(0h1), "") : assert_19
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_143 = and(_T_141, _T_142)
node _T_144 = or(UInt<1>(0h0), _T_143)
node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = and(_T_144, _T_149)
node _T_151 = or(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_151, UInt<1>(0h1), "") : assert_20
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_158 = asUInt(reset)
node _T_159 = eq(_T_158, UInt<1>(0h0))
when _T_159 :
node _T_160 = eq(is_aligned, UInt<1>(0h0))
when _T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(_T_161, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_161, UInt<1>(0h1), "") : assert_23
node _T_165 = eq(io.in.a.bits.mask, mask)
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_165, UInt<1>(0h1), "") : assert_24
node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_169, UInt<1>(0h1), "") : assert_25
node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_180 = and(_T_178, _T_179)
node _T_181 = or(UInt<1>(0h0), _T_180)
node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_177, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_189, UInt<1>(0h1), "") : assert_26
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(is_aligned, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_200 = asUInt(reset)
node _T_201 = eq(_T_200, UInt<1>(0h0))
when _T_201 :
node _T_202 = eq(_T_199, UInt<1>(0h0))
when _T_202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_199, UInt<1>(0h1), "") : assert_29
node _T_203 = eq(io.in.a.bits.mask, mask)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_203, UInt<1>(0h1), "") : assert_30
node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_207 :
node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_209 = and(UInt<1>(0h0), _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_213 = and(_T_211, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = and(_T_214, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_210, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_222, UInt<1>(0h1), "") : assert_31
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(is_aligned, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_232, UInt<1>(0h1), "") : assert_34
node _T_236 = not(mask)
node _T_237 = and(io.in.a.bits.mask, _T_236)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_238, UInt<1>(0h1), "") : assert_35
node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_242 :
node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_244 = and(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), _T_244)
node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_248 = cvt(_T_247)
node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_250 = asSInt(_T_249)
node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0)))
node _T_252 = and(_T_246, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_245, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_254, UInt<1>(0h1), "") : assert_36
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_264, UInt<1>(0h1), "") : assert_39
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_268, UInt<1>(0h1), "") : assert_40
node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_272 :
node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_274 = and(UInt<1>(0h0), _T_273)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = and(_T_276, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = and(_T_275, _T_283)
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_284, UInt<1>(0h1), "") : assert_41
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(is_aligned, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_294, UInt<1>(0h1), "") : assert_44
node _T_298 = eq(io.in.a.bits.mask, mask)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_298, UInt<1>(0h1), "") : assert_45
node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_302 :
node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_304 = and(UInt<1>(0h0), _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_308 = and(_T_306, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = and(_T_309, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = and(_T_305, _T_316)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_317, UInt<1>(0h1), "") : assert_46
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(is_aligned, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_327, UInt<1>(0h1), "") : assert_49
node _T_331 = eq(io.in.a.bits.mask, mask)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_331, UInt<1>(0h1), "") : assert_50
node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_T_335, UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_335, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_339, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1))
node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_343 :
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_347, UInt<1>(0h1), "") : assert_54
node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_351, UInt<1>(0h1), "") : assert_55
node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_355, UInt<1>(0h1), "") : assert_56
node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_359, UInt<1>(0h1), "") : assert_57
node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_363 :
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(sink_ok, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_370, UInt<1>(0h1), "") : assert_60
node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_374, UInt<1>(0h1), "") : assert_61
node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_378, UInt<1>(0h1), "") : assert_62
node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_382, UInt<1>(0h1), "") : assert_63
node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_387 = or(UInt<1>(0h1), _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_387, UInt<1>(0h1), "") : assert_64
node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_391 :
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(sink_ok, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_398, UInt<1>(0h1), "") : assert_67
node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_402, UInt<1>(0h1), "") : assert_68
node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_406, UInt<1>(0h1), "") : assert_69
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = or(_T_410, io.in.d.bits.corrupt)
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_411, UInt<1>(0h1), "") : assert_70
node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_416 = or(UInt<1>(0h1), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_416, UInt<1>(0h1), "") : assert_71
node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_420 :
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_424, UInt<1>(0h1), "") : assert_73
node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_428, UInt<1>(0h1), "") : assert_74
node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_433 = or(UInt<1>(0h1), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_433, UInt<1>(0h1), "") : assert_75
node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_437 :
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_441, UInt<1>(0h1), "") : assert_77
node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_446 = or(_T_445, io.in.d.bits.corrupt)
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_446, UInt<1>(0h1), "") : assert_78
node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_451 = or(UInt<1>(0h1), _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_451, UInt<1>(0h1), "") : assert_79
node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_455 :
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_459, UInt<1>(0h1), "") : assert_81
node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_463, UInt<1>(0h1), "") : assert_82
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h1), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_468, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<128>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_472, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<128>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_476, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_480, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_484 = eq(a_first, UInt<1>(0h0))
node _T_485 = and(io.in.a.valid, _T_484)
when _T_485 :
node _T_486 = eq(io.in.a.bits.opcode, opcode)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_486, UInt<1>(0h1), "") : assert_87
node _T_490 = eq(io.in.a.bits.param, param)
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_490, UInt<1>(0h1), "") : assert_88
node _T_494 = eq(io.in.a.bits.size, size)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_494, UInt<1>(0h1), "") : assert_89
node _T_498 = eq(io.in.a.bits.source, source)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_498, UInt<1>(0h1), "") : assert_90
node _T_502 = eq(io.in.a.bits.address, address)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_502, UInt<1>(0h1), "") : assert_91
node _T_506 = and(io.in.a.ready, io.in.a.valid)
node _T_507 = and(_T_506, a_first)
when _T_507 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_508 = eq(d_first, UInt<1>(0h0))
node _T_509 = and(io.in.d.valid, _T_508)
when _T_509 :
node _T_510 = eq(io.in.d.bits.opcode, opcode_1)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_510, UInt<1>(0h1), "") : assert_92
node _T_514 = eq(io.in.d.bits.param, param_1)
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_514, UInt<1>(0h1), "") : assert_93
node _T_518 = eq(io.in.d.bits.size, size_1)
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_518, UInt<1>(0h1), "") : assert_94
node _T_522 = eq(io.in.d.bits.source, source_1)
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_522, UInt<1>(0h1), "") : assert_95
node _T_526 = eq(io.in.d.bits.sink, sink)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_526, UInt<1>(0h1), "") : assert_96
node _T_530 = eq(io.in.d.bits.denied, denied)
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_530, UInt<1>(0h1), "") : assert_97
node _T_534 = and(io.in.d.ready, io.in.d.valid)
node _T_535 = and(_T_534, d_first)
when _T_535 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_536 = and(io.in.a.valid, a_first_1)
node _T_537 = and(_T_536, UInt<1>(0h1))
when _T_537 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_538 = and(io.in.a.ready, io.in.a.valid)
node _T_539 = and(_T_538, a_first_1)
node _T_540 = and(_T_539, UInt<1>(0h1))
when _T_540 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_541 = dshr(inflight, io.in.a.bits.source)
node _T_542 = bits(_T_541, 0, 0)
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_543, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_551 = and(io.in.d.ready, io.in.d.valid)
node _T_552 = and(_T_551, d_first_1)
node _T_553 = and(_T_552, UInt<1>(0h1))
node _T_554 = eq(d_release_ack, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
when _T_555 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_556 = and(io.in.d.valid, d_first_1)
node _T_557 = and(_T_556, UInt<1>(0h1))
node _T_558 = eq(d_release_ack, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
when _T_559 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_560 = dshr(inflight, io.in.d.bits.source)
node _T_561 = bits(_T_560, 0, 0)
node _T_562 = or(_T_561, same_cycle_resp)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_562, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_568 = or(_T_566, _T_567)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_568, UInt<1>(0h1), "") : assert_100
node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_572, UInt<1>(0h1), "") : assert_101
else :
node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_578 = or(_T_576, _T_577)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_578, UInt<1>(0h1), "") : assert_102
node _T_582 = eq(io.in.d.bits.size, a_size_lookup)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_582, UInt<1>(0h1), "") : assert_103
node _T_586 = and(io.in.d.valid, d_first_1)
node _T_587 = and(_T_586, a_first_1)
node _T_588 = and(_T_587, io.in.a.valid)
node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(d_release_ack, UInt<1>(0h0))
node _T_592 = and(_T_590, _T_591)
when _T_592 :
node _T_593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_594 = or(_T_593, io.in.a.ready)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_594, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_123
node _T_598 = orr(inflight)
node _T_599 = eq(_T_598, UInt<1>(0h0))
node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_601 = or(_T_599, _T_600)
node _T_602 = lt(watchdog, plusarg_reader.out)
node _T_603 = or(_T_601, _T_602)
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_603, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_607 = and(io.in.a.ready, io.in.a.valid)
node _T_608 = and(io.in.d.ready, io.in.d.valid)
node _T_609 = or(_T_607, _T_608)
when _T_609 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<128>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<128>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_610 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<128>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_613 = and(_T_611, _T_612)
node _T_614 = and(_T_610, _T_613)
when _T_614 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<128>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_616 = and(_T_615, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<128>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_619 = and(_T_617, _T_618)
node _T_620 = and(_T_616, _T_619)
when _T_620 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<128>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_621 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_622 = bits(_T_621, 0, 0)
node _T_623 = eq(_T_622, UInt<1>(0h0))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_623, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_627 = and(io.in.d.valid, d_first_2)
node _T_628 = and(_T_627, UInt<1>(0h1))
node _T_629 = and(_T_628, d_release_ack_1)
when _T_629 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_630 = and(io.in.d.ready, io.in.d.valid)
node _T_631 = and(_T_630, d_first_2)
node _T_632 = and(_T_631, UInt<1>(0h1))
node _T_633 = and(_T_632, d_release_ack_1)
when _T_633 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_634 = and(io.in.d.valid, d_first_2)
node _T_635 = and(_T_634, UInt<1>(0h1))
node _T_636 = and(_T_635, d_release_ack_1)
when _T_636 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_637 = dshr(inflight_1, io.in.d.bits.source)
node _T_638 = bits(_T_637, 0, 0)
node _T_639 = or(_T_638, same_cycle_resp_1)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_639, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<128>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_643, UInt<1>(0h1), "") : assert_108
else :
node _T_647 = eq(io.in.d.bits.size, c_size_lookup)
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_647, UInt<1>(0h1), "") : assert_109
node _T_651 = and(io.in.d.valid, d_first_2)
node _T_652 = and(_T_651, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<128>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_653 = and(_T_652, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<128>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_655 = and(_T_653, _T_654)
node _T_656 = and(_T_655, d_release_ack_1)
node _T_657 = eq(c_probe_ack, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
when _T_658 :
node _T_659 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<128>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_660 = or(_T_659, _WIRE_23.ready)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_660, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_124
node _T_664 = orr(inflight_1)
node _T_665 = eq(_T_664, UInt<1>(0h0))
node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_667 = or(_T_665, _T_666)
node _T_668 = lt(watchdog_1, plusarg_reader_1.out)
node _T_669 = or(_T_667, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_669, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_674 = and(io.in.d.ready, io.in.d.valid)
node _T_675 = or(_T_673, _T_674)
when _T_675 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_61( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_607; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_238 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_238( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = and(_T_11, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_24 :
node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_35 = cvt(_T_34)
node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000)))
node _T_37 = asSInt(_T_36)
node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0)))
node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_40 = cvt(_T_39)
node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000)))
node _T_42 = asSInt(_T_41)
node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0)))
node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_45 = cvt(_T_44)
node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000)))
node _T_47 = asSInt(_T_46)
node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0)))
node _T_49 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_50 = cvt(_T_49)
node _T_51 = and(_T_50, asSInt(UInt<15>(0h4000)))
node _T_52 = asSInt(_T_51)
node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0)))
node _T_54 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<13>(0h1000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_38, _T_43)
node _T_85 = or(_T_84, _T_48)
node _T_86 = or(_T_85, _T_53)
node _T_87 = or(_T_86, _T_58)
node _T_88 = or(_T_87, _T_63)
node _T_89 = or(_T_88, _T_68)
node _T_90 = or(_T_89, _T_73)
node _T_91 = or(_T_90, _T_78)
node _T_92 = or(_T_91, _T_83)
node _T_93 = and(_T_33, _T_92)
node _T_94 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<29>(0h10000000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = or(_T_100, _T_105)
node _T_107 = and(_T_95, _T_106)
node _T_108 = or(UInt<1>(0h0), _T_93)
node _T_109 = or(_T_108, _T_107)
node _T_110 = and(_T_32, _T_109)
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_110, UInt<1>(0h1), "") : assert_2
node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_115 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE : UInt<1>[2]
connect _WIRE[0], _T_114
connect _WIRE[1], _T_115
node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0))
node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_119 = or(_T_117, _T_118)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_119
node _T_120 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_121 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_122 = and(_T_120, _T_121)
node _T_123 = or(UInt<1>(0h0), _T_122)
node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_125 = cvt(_T_124)
node _T_126 = and(_T_125, asSInt(UInt<14>(0h2000)))
node _T_127 = asSInt(_T_126)
node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0)))
node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<17>(0h10000)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<15>(0h4000)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<18>(0h2f000)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<17>(0h10000)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<17>(0h10000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_170 = cvt(_T_169)
node _T_171 = and(_T_170, asSInt(UInt<27>(0h4000000)))
node _T_172 = asSInt(_T_171)
node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0)))
node _T_174 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_175 = cvt(_T_174)
node _T_176 = and(_T_175, asSInt(UInt<13>(0h1000)))
node _T_177 = asSInt(_T_176)
node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0)))
node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = or(_T_128, _T_133)
node _T_185 = or(_T_184, _T_138)
node _T_186 = or(_T_185, _T_143)
node _T_187 = or(_T_186, _T_148)
node _T_188 = or(_T_187, _T_153)
node _T_189 = or(_T_188, _T_158)
node _T_190 = or(_T_189, _T_163)
node _T_191 = or(_T_190, _T_168)
node _T_192 = or(_T_191, _T_173)
node _T_193 = or(_T_192, _T_178)
node _T_194 = or(_T_193, _T_183)
node _T_195 = and(_T_123, _T_194)
node _T_196 = or(UInt<1>(0h0), _T_195)
node _T_197 = and(_WIRE_1, _T_196)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_197, UInt<1>(0h1), "") : assert_3
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(source_ok, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_204 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_204, UInt<1>(0h1), "") : assert_5
node _T_208 = asUInt(reset)
node _T_209 = eq(_T_208, UInt<1>(0h0))
when _T_209 :
node _T_210 = eq(is_aligned, UInt<1>(0h0))
when _T_210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_211 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_211, UInt<1>(0h1), "") : assert_7
node _T_215 = not(io.in.a.bits.mask)
node _T_216 = eq(_T_215, UInt<1>(0h0))
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_216, UInt<1>(0h1), "") : assert_8
node _T_220 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_220, UInt<1>(0h1), "") : assert_9
node _T_224 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_224 :
node _T_225 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_226 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_227 = and(_T_225, _T_226)
node _T_228 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_229 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_230 = or(_T_228, _T_229)
node _T_231 = and(_T_227, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<15>(0h4000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<13>(0h1000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<18>(0h2f000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<17>(0h10000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<27>(0h4000000)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<13>(0h1000)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = or(_T_238, _T_243)
node _T_285 = or(_T_284, _T_248)
node _T_286 = or(_T_285, _T_253)
node _T_287 = or(_T_286, _T_258)
node _T_288 = or(_T_287, _T_263)
node _T_289 = or(_T_288, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = and(_T_233, _T_292)
node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_293)
node _T_309 = or(_T_308, _T_307)
node _T_310 = and(_T_232, _T_309)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_310, UInt<1>(0h1), "") : assert_10
node _T_314 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE_2 : UInt<1>[2]
connect _WIRE_2[0], _T_314
connect _WIRE_2[1], _T_315
node _T_316 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_317 = mux(_WIRE_2[0], _T_316, UInt<1>(0h0))
node _T_318 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = or(_T_317, _T_318)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_319
node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_322 = and(_T_320, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<14>(0h2000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<13>(0h1000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<15>(0h4000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<18>(0h2f000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_365 = cvt(_T_364)
node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000)))
node _T_367 = asSInt(_T_366)
node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0)))
node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = or(_T_328, _T_333)
node _T_385 = or(_T_384, _T_338)
node _T_386 = or(_T_385, _T_343)
node _T_387 = or(_T_386, _T_348)
node _T_388 = or(_T_387, _T_353)
node _T_389 = or(_T_388, _T_358)
node _T_390 = or(_T_389, _T_363)
node _T_391 = or(_T_390, _T_368)
node _T_392 = or(_T_391, _T_373)
node _T_393 = or(_T_392, _T_378)
node _T_394 = or(_T_393, _T_383)
node _T_395 = and(_T_323, _T_394)
node _T_396 = or(UInt<1>(0h0), _T_395)
node _T_397 = and(_WIRE_3, _T_396)
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_397, UInt<1>(0h1), "") : assert_11
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(source_ok, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_404 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_404, UInt<1>(0h1), "") : assert_13
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(is_aligned, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_411 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_411, UInt<1>(0h1), "") : assert_15
node _T_415 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_415, UInt<1>(0h1), "") : assert_16
node _T_419 = not(io.in.a.bits.mask)
node _T_420 = eq(_T_419, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_420, UInt<1>(0h1), "") : assert_17
node _T_424 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_424, UInt<1>(0h1), "") : assert_18
node _T_428 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_428 :
node _T_429 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_430 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_433 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_434 = or(_T_432, _T_433)
node _T_435 = and(_T_431, _T_434)
node _T_436 = or(UInt<1>(0h0), _T_435)
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_436, UInt<1>(0h1), "") : assert_19
node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_442 = and(_T_440, _T_441)
node _T_443 = or(UInt<1>(0h0), _T_442)
node _T_444 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<13>(0h1000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = and(_T_443, _T_448)
node _T_450 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_451 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_452 = and(_T_450, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_452)
node _T_454 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_455 = cvt(_T_454)
node _T_456 = and(_T_455, asSInt(UInt<14>(0h2000)))
node _T_457 = asSInt(_T_456)
node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0)))
node _T_459 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<18>(0h2f000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_470 = cvt(_T_469)
node _T_471 = and(_T_470, asSInt(UInt<17>(0h10000)))
node _T_472 = asSInt(_T_471)
node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0)))
node _T_474 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_475 = cvt(_T_474)
node _T_476 = and(_T_475, asSInt(UInt<13>(0h1000)))
node _T_477 = asSInt(_T_476)
node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0)))
node _T_479 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_480 = cvt(_T_479)
node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000)))
node _T_482 = asSInt(_T_481)
node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0)))
node _T_484 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_485 = cvt(_T_484)
node _T_486 = and(_T_485, asSInt(UInt<27>(0h4000000)))
node _T_487 = asSInt(_T_486)
node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0)))
node _T_489 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_490 = cvt(_T_489)
node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000)))
node _T_492 = asSInt(_T_491)
node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0)))
node _T_494 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<29>(0h10000000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = or(_T_458, _T_463)
node _T_500 = or(_T_499, _T_468)
node _T_501 = or(_T_500, _T_473)
node _T_502 = or(_T_501, _T_478)
node _T_503 = or(_T_502, _T_483)
node _T_504 = or(_T_503, _T_488)
node _T_505 = or(_T_504, _T_493)
node _T_506 = or(_T_505, _T_498)
node _T_507 = and(_T_453, _T_506)
node _T_508 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_509 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_510 = and(_T_508, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<15>(0h4000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = or(_T_516, _T_521)
node _T_523 = and(_T_511, _T_522)
node _T_524 = or(UInt<1>(0h0), _T_449)
node _T_525 = or(_T_524, _T_507)
node _T_526 = or(_T_525, _T_523)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_526, UInt<1>(0h1), "") : assert_20
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(source_ok, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(is_aligned, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_536 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(_T_536, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_536, UInt<1>(0h1), "") : assert_23
node _T_540 = eq(io.in.a.bits.mask, mask)
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_540, UInt<1>(0h1), "") : assert_24
node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_544, UInt<1>(0h1), "") : assert_25
node _T_548 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_548 :
node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_553 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_554 = or(_T_552, _T_553)
node _T_555 = and(_T_551, _T_554)
node _T_556 = or(UInt<1>(0h0), _T_555)
node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_558 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_559 = and(_T_557, _T_558)
node _T_560 = or(UInt<1>(0h0), _T_559)
node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_562 = cvt(_T_561)
node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000)))
node _T_564 = asSInt(_T_563)
node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0)))
node _T_566 = and(_T_560, _T_565)
node _T_567 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_568 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_569 = and(_T_567, _T_568)
node _T_570 = or(UInt<1>(0h0), _T_569)
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<14>(0h2000)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<18>(0h2f000)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<17>(0h10000)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<17>(0h10000)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<27>(0h4000000)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_602 = cvt(_T_601)
node _T_603 = and(_T_602, asSInt(UInt<13>(0h1000)))
node _T_604 = asSInt(_T_603)
node _T_605 = eq(_T_604, asSInt(UInt<1>(0h0)))
node _T_606 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_607 = cvt(_T_606)
node _T_608 = and(_T_607, asSInt(UInt<29>(0h10000000)))
node _T_609 = asSInt(_T_608)
node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0)))
node _T_611 = or(_T_575, _T_580)
node _T_612 = or(_T_611, _T_585)
node _T_613 = or(_T_612, _T_590)
node _T_614 = or(_T_613, _T_595)
node _T_615 = or(_T_614, _T_600)
node _T_616 = or(_T_615, _T_605)
node _T_617 = or(_T_616, _T_610)
node _T_618 = and(_T_570, _T_617)
node _T_619 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_620 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = and(_T_619, _T_624)
node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_627 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_628)
node _T_630 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<15>(0h4000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = or(_T_634, _T_639)
node _T_641 = and(_T_629, _T_640)
node _T_642 = or(UInt<1>(0h0), _T_566)
node _T_643 = or(_T_642, _T_618)
node _T_644 = or(_T_643, _T_625)
node _T_645 = or(_T_644, _T_641)
node _T_646 = and(_T_556, _T_645)
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_646, UInt<1>(0h1), "") : assert_26
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(source_ok, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(is_aligned, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_656 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_657 = asUInt(reset)
node _T_658 = eq(_T_657, UInt<1>(0h0))
when _T_658 :
node _T_659 = eq(_T_656, UInt<1>(0h0))
when _T_659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_656, UInt<1>(0h1), "") : assert_29
node _T_660 = eq(io.in.a.bits.mask, mask)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_660, UInt<1>(0h1), "") : assert_30
node _T_664 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_664 :
node _T_665 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_666 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_669 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_670 = or(_T_668, _T_669)
node _T_671 = and(_T_667, _T_670)
node _T_672 = or(UInt<1>(0h0), _T_671)
node _T_673 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_674 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_675 = and(_T_673, _T_674)
node _T_676 = or(UInt<1>(0h0), _T_675)
node _T_677 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_678 = cvt(_T_677)
node _T_679 = and(_T_678, asSInt(UInt<13>(0h1000)))
node _T_680 = asSInt(_T_679)
node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0)))
node _T_682 = and(_T_676, _T_681)
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_685 = and(_T_683, _T_684)
node _T_686 = or(UInt<1>(0h0), _T_685)
node _T_687 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_688 = cvt(_T_687)
node _T_689 = and(_T_688, asSInt(UInt<14>(0h2000)))
node _T_690 = asSInt(_T_689)
node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0)))
node _T_692 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_693 = cvt(_T_692)
node _T_694 = and(_T_693, asSInt(UInt<18>(0h2f000)))
node _T_695 = asSInt(_T_694)
node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0)))
node _T_697 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_698 = cvt(_T_697)
node _T_699 = and(_T_698, asSInt(UInt<17>(0h10000)))
node _T_700 = asSInt(_T_699)
node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0)))
node _T_702 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<13>(0h1000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_708 = cvt(_T_707)
node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000)))
node _T_710 = asSInt(_T_709)
node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0)))
node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_713 = cvt(_T_712)
node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000)))
node _T_715 = asSInt(_T_714)
node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0)))
node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_718 = cvt(_T_717)
node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000)))
node _T_720 = asSInt(_T_719)
node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0)))
node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_723 = cvt(_T_722)
node _T_724 = and(_T_723, asSInt(UInt<29>(0h10000000)))
node _T_725 = asSInt(_T_724)
node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0)))
node _T_727 = or(_T_691, _T_696)
node _T_728 = or(_T_727, _T_701)
node _T_729 = or(_T_728, _T_706)
node _T_730 = or(_T_729, _T_711)
node _T_731 = or(_T_730, _T_716)
node _T_732 = or(_T_731, _T_721)
node _T_733 = or(_T_732, _T_726)
node _T_734 = and(_T_686, _T_733)
node _T_735 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_736 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = and(_T_735, _T_740)
node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_743 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_744 = and(_T_742, _T_743)
node _T_745 = or(UInt<1>(0h0), _T_744)
node _T_746 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_750, _T_755)
node _T_757 = and(_T_745, _T_756)
node _T_758 = or(UInt<1>(0h0), _T_682)
node _T_759 = or(_T_758, _T_734)
node _T_760 = or(_T_759, _T_741)
node _T_761 = or(_T_760, _T_757)
node _T_762 = and(_T_672, _T_761)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_762, UInt<1>(0h1), "") : assert_31
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(source_ok, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(is_aligned, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_772 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_772, UInt<1>(0h1), "") : assert_34
node _T_776 = not(mask)
node _T_777 = and(io.in.a.bits.mask, _T_776)
node _T_778 = eq(_T_777, UInt<1>(0h0))
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_778, UInt<1>(0h1), "") : assert_35
node _T_782 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_782 :
node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_787 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_788 = or(_T_786, _T_787)
node _T_789 = and(_T_785, _T_788)
node _T_790 = or(UInt<1>(0h0), _T_789)
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<15>(0h4000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<18>(0h2f000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<27>(0h4000000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_841 = cvt(_T_840)
node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000)))
node _T_843 = asSInt(_T_842)
node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0)))
node _T_845 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_846 = cvt(_T_845)
node _T_847 = and(_T_846, asSInt(UInt<29>(0h10000000)))
node _T_848 = asSInt(_T_847)
node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0)))
node _T_850 = or(_T_799, _T_804)
node _T_851 = or(_T_850, _T_809)
node _T_852 = or(_T_851, _T_814)
node _T_853 = or(_T_852, _T_819)
node _T_854 = or(_T_853, _T_824)
node _T_855 = or(_T_854, _T_829)
node _T_856 = or(_T_855, _T_834)
node _T_857 = or(_T_856, _T_839)
node _T_858 = or(_T_857, _T_844)
node _T_859 = or(_T_858, _T_849)
node _T_860 = and(_T_794, _T_859)
node _T_861 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_862 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<17>(0h10000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = and(_T_861, _T_866)
node _T_868 = or(UInt<1>(0h0), _T_860)
node _T_869 = or(_T_868, _T_867)
node _T_870 = and(_T_790, _T_869)
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_870, UInt<1>(0h1), "") : assert_36
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(source_ok, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_877 = asUInt(reset)
node _T_878 = eq(_T_877, UInt<1>(0h0))
when _T_878 :
node _T_879 = eq(is_aligned, UInt<1>(0h0))
when _T_879 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_880 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_881 = asUInt(reset)
node _T_882 = eq(_T_881, UInt<1>(0h0))
when _T_882 :
node _T_883 = eq(_T_880, UInt<1>(0h0))
when _T_883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_880, UInt<1>(0h1), "") : assert_39
node _T_884 = eq(io.in.a.bits.mask, mask)
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(_T_884, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_884, UInt<1>(0h1), "") : assert_40
node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_888 :
node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_893 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_894 = or(_T_892, _T_893)
node _T_895 = and(_T_891, _T_894)
node _T_896 = or(UInt<1>(0h0), _T_895)
node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_898 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_899 = and(_T_897, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_899)
node _T_901 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<14>(0h2000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_912 = cvt(_T_911)
node _T_913 = and(_T_912, asSInt(UInt<15>(0h4000)))
node _T_914 = asSInt(_T_913)
node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<13>(0h1000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<18>(0h2f000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_927 = cvt(_T_926)
node _T_928 = and(_T_927, asSInt(UInt<17>(0h10000)))
node _T_929 = asSInt(_T_928)
node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0)))
node _T_931 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_932 = cvt(_T_931)
node _T_933 = and(_T_932, asSInt(UInt<13>(0h1000)))
node _T_934 = asSInt(_T_933)
node _T_935 = eq(_T_934, asSInt(UInt<1>(0h0)))
node _T_936 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_937 = cvt(_T_936)
node _T_938 = and(_T_937, asSInt(UInt<17>(0h10000)))
node _T_939 = asSInt(_T_938)
node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0)))
node _T_941 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_942 = cvt(_T_941)
node _T_943 = and(_T_942, asSInt(UInt<27>(0h4000000)))
node _T_944 = asSInt(_T_943)
node _T_945 = eq(_T_944, asSInt(UInt<1>(0h0)))
node _T_946 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_947 = cvt(_T_946)
node _T_948 = and(_T_947, asSInt(UInt<13>(0h1000)))
node _T_949 = asSInt(_T_948)
node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0)))
node _T_951 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<29>(0h10000000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = or(_T_905, _T_910)
node _T_957 = or(_T_956, _T_915)
node _T_958 = or(_T_957, _T_920)
node _T_959 = or(_T_958, _T_925)
node _T_960 = or(_T_959, _T_930)
node _T_961 = or(_T_960, _T_935)
node _T_962 = or(_T_961, _T_940)
node _T_963 = or(_T_962, _T_945)
node _T_964 = or(_T_963, _T_950)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_900, _T_965)
node _T_967 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_968 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_969 = cvt(_T_968)
node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000)))
node _T_971 = asSInt(_T_970)
node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0)))
node _T_973 = and(_T_967, _T_972)
node _T_974 = or(UInt<1>(0h0), _T_966)
node _T_975 = or(_T_974, _T_973)
node _T_976 = and(_T_896, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_976, UInt<1>(0h1), "") : assert_41
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_986 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_986, UInt<1>(0h1), "") : assert_44
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_990, UInt<1>(0h1), "") : assert_45
node _T_994 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_994 :
node _T_995 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_996 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_997 = and(_T_995, _T_996)
node _T_998 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_999 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_1000 = or(_T_998, _T_999)
node _T_1001 = and(_T_997, _T_1000)
node _T_1002 = or(UInt<1>(0h0), _T_1001)
node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = or(UInt<1>(0h0), _T_1005)
node _T_1007 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = and(_T_1006, _T_1011)
node _T_1013 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1014 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<14>(0h2000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1025 = cvt(_T_1024)
node _T_1026 = and(_T_1025, asSInt(UInt<15>(0h4000)))
node _T_1027 = asSInt(_T_1026)
node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0)))
node _T_1029 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<13>(0h1000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1035 = cvt(_T_1034)
node _T_1036 = and(_T_1035, asSInt(UInt<18>(0h2f000)))
node _T_1037 = asSInt(_T_1036)
node _T_1038 = eq(_T_1037, asSInt(UInt<1>(0h0)))
node _T_1039 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1040 = cvt(_T_1039)
node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000)))
node _T_1042 = asSInt(_T_1041)
node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0)))
node _T_1044 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1045 = cvt(_T_1044)
node _T_1046 = and(_T_1045, asSInt(UInt<13>(0h1000)))
node _T_1047 = asSInt(_T_1046)
node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0)))
node _T_1049 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1050 = cvt(_T_1049)
node _T_1051 = and(_T_1050, asSInt(UInt<27>(0h4000000)))
node _T_1052 = asSInt(_T_1051)
node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0)))
node _T_1054 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1055 = cvt(_T_1054)
node _T_1056 = and(_T_1055, asSInt(UInt<13>(0h1000)))
node _T_1057 = asSInt(_T_1056)
node _T_1058 = eq(_T_1057, asSInt(UInt<1>(0h0)))
node _T_1059 = or(_T_1018, _T_1023)
node _T_1060 = or(_T_1059, _T_1028)
node _T_1061 = or(_T_1060, _T_1033)
node _T_1062 = or(_T_1061, _T_1038)
node _T_1063 = or(_T_1062, _T_1043)
node _T_1064 = or(_T_1063, _T_1048)
node _T_1065 = or(_T_1064, _T_1053)
node _T_1066 = or(_T_1065, _T_1058)
node _T_1067 = and(_T_1013, _T_1066)
node _T_1068 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1069 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1070 = and(_T_1068, _T_1069)
node _T_1071 = or(UInt<1>(0h0), _T_1070)
node _T_1072 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1073 = cvt(_T_1072)
node _T_1074 = and(_T_1073, asSInt(UInt<17>(0h10000)))
node _T_1075 = asSInt(_T_1074)
node _T_1076 = eq(_T_1075, asSInt(UInt<1>(0h0)))
node _T_1077 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1078 = cvt(_T_1077)
node _T_1079 = and(_T_1078, asSInt(UInt<29>(0h10000000)))
node _T_1080 = asSInt(_T_1079)
node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0)))
node _T_1082 = or(_T_1076, _T_1081)
node _T_1083 = and(_T_1071, _T_1082)
node _T_1084 = or(UInt<1>(0h0), _T_1012)
node _T_1085 = or(_T_1084, _T_1067)
node _T_1086 = or(_T_1085, _T_1083)
node _T_1087 = and(_T_1002, _T_1086)
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_46
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(source_ok, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(is_aligned, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1097 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_49
node _T_1101 = eq(io.in.a.bits.mask, mask)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_50
node _T_1105 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1109 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_52
node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_2
connect _source_ok_WIRE_1[1], _source_ok_T_3
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1113 :
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(source_ok_1, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_54
node _T_1121 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_55
node _T_1125 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_56
node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_57
node _T_1133 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1133 :
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(source_ok_1, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(sink_ok, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1140 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_60
node _T_1144 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_61
node _T_1148 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_62
node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_63
node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1157 = or(UInt<1>(0h1), _T_1156)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_64
node _T_1161 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1161 :
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(source_ok_1, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(sink_ok, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1168 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_67
node _T_1172 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_68
node _T_1176 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_69
node _T_1180 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1181 = or(_T_1180, io.in.d.bits.corrupt)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_70
node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1186 = or(UInt<1>(0h1), _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_71
node _T_1190 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(source_ok_1, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1194 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_73
node _T_1198 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_74
node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1203 = or(UInt<1>(0h1), _T_1202)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_75
node _T_1207 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1207 :
node _T_1208 = asUInt(reset)
node _T_1209 = eq(_T_1208, UInt<1>(0h0))
when _T_1209 :
node _T_1210 = eq(source_ok_1, UInt<1>(0h0))
when _T_1210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1211 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_77
node _T_1215 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1216 = or(_T_1215, io.in.d.bits.corrupt)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_78
node _T_1220 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1221 = or(UInt<1>(0h1), _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_79
node _T_1225 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1225 :
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(source_ok_1, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_81
node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_82
node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1238 = or(UInt<1>(0h1), _T_1237)
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1242 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1243 = asUInt(reset)
node _T_1244 = eq(_T_1243, UInt<1>(0h0))
when _T_1244 :
node _T_1245 = eq(_T_1242, UInt<1>(0h0))
when _T_1245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1242, UInt<1>(0h1), "") : assert_84
node _T_1246 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
node _T_1248 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<1>(0h0)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = or(_T_1247, _T_1252)
node _T_1254 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
node _T_1256 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1257 = cvt(_T_1256)
node _T_1258 = and(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = asSInt(_T_1258)
node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0)))
node _T_1261 = or(_T_1255, _T_1260)
node _T_1262 = and(_T_1253, _T_1261)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<18>(0h21000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<18>(0h22000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<13>(0h1000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<18>(0h23000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<13>(0h1000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_61 = cvt(_address_ok_T_60)
node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000)))
node _address_ok_T_63 = asSInt(_address_ok_T_62)
node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0)))
node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_66 = cvt(_address_ok_T_65)
node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000)))
node _address_ok_T_68 = asSInt(_address_ok_T_67)
node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0)))
node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[17]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
connect _address_ok_WIRE[12], _address_ok_T_64
connect _address_ok_WIRE[13], _address_ok_T_69
connect _address_ok_WIRE[14], _address_ok_T_74
connect _address_ok_WIRE[15], _address_ok_T_79
connect _address_ok_WIRE[16], _address_ok_T_84
node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2])
node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3])
node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4])
node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5])
node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6])
node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7])
node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8])
node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9])
node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10])
node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11])
node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12])
node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13])
node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14])
node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15])
node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _legal_source_WIRE : UInt<1>[2]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3)
wire _legal_source_WIRE_1 : UInt<1>
connect _legal_source_WIRE_1, _legal_source_T_4
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1266 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1266 :
node _T_1267 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1268 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _WIRE_4 : UInt<1>[2]
connect _WIRE_4[0], _T_1267
connect _WIRE_4[1], _T_1268
node _T_1269 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1270 = mux(_WIRE_4[0], _T_1269, UInt<1>(0h0))
node _T_1271 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1272 = or(_T_1270, _T_1271)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1272
node _T_1273 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1274 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1275 = and(_T_1273, _T_1274)
node _T_1276 = or(UInt<1>(0h0), _T_1275)
node _T_1277 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1278 = cvt(_T_1277)
node _T_1279 = and(_T_1278, asSInt(UInt<14>(0h2000)))
node _T_1280 = asSInt(_T_1279)
node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0)))
node _T_1282 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1283 = cvt(_T_1282)
node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000)))
node _T_1285 = asSInt(_T_1284)
node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0)))
node _T_1287 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1288 = cvt(_T_1287)
node _T_1289 = and(_T_1288, asSInt(UInt<17>(0h10000)))
node _T_1290 = asSInt(_T_1289)
node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0)))
node _T_1292 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1293 = cvt(_T_1292)
node _T_1294 = and(_T_1293, asSInt(UInt<15>(0h4000)))
node _T_1295 = asSInt(_T_1294)
node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0)))
node _T_1297 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1298 = cvt(_T_1297)
node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000)))
node _T_1300 = asSInt(_T_1299)
node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0)))
node _T_1302 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1303 = cvt(_T_1302)
node _T_1304 = and(_T_1303, asSInt(UInt<18>(0h2f000)))
node _T_1305 = asSInt(_T_1304)
node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0)))
node _T_1307 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1308 = cvt(_T_1307)
node _T_1309 = and(_T_1308, asSInt(UInt<17>(0h10000)))
node _T_1310 = asSInt(_T_1309)
node _T_1311 = eq(_T_1310, asSInt(UInt<1>(0h0)))
node _T_1312 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1313 = cvt(_T_1312)
node _T_1314 = and(_T_1313, asSInt(UInt<13>(0h1000)))
node _T_1315 = asSInt(_T_1314)
node _T_1316 = eq(_T_1315, asSInt(UInt<1>(0h0)))
node _T_1317 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1318 = cvt(_T_1317)
node _T_1319 = and(_T_1318, asSInt(UInt<17>(0h10000)))
node _T_1320 = asSInt(_T_1319)
node _T_1321 = eq(_T_1320, asSInt(UInt<1>(0h0)))
node _T_1322 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1323 = cvt(_T_1322)
node _T_1324 = and(_T_1323, asSInt(UInt<27>(0h4000000)))
node _T_1325 = asSInt(_T_1324)
node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0)))
node _T_1327 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1328 = cvt(_T_1327)
node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000)))
node _T_1330 = asSInt(_T_1329)
node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0)))
node _T_1332 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1333 = cvt(_T_1332)
node _T_1334 = and(_T_1333, asSInt(UInt<29>(0h10000000)))
node _T_1335 = asSInt(_T_1334)
node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0)))
node _T_1337 = or(_T_1281, _T_1286)
node _T_1338 = or(_T_1337, _T_1291)
node _T_1339 = or(_T_1338, _T_1296)
node _T_1340 = or(_T_1339, _T_1301)
node _T_1341 = or(_T_1340, _T_1306)
node _T_1342 = or(_T_1341, _T_1311)
node _T_1343 = or(_T_1342, _T_1316)
node _T_1344 = or(_T_1343, _T_1321)
node _T_1345 = or(_T_1344, _T_1326)
node _T_1346 = or(_T_1345, _T_1331)
node _T_1347 = or(_T_1346, _T_1336)
node _T_1348 = and(_T_1276, _T_1347)
node _T_1349 = or(UInt<1>(0h0), _T_1348)
node _T_1350 = and(_WIRE_5, _T_1349)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_86
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(address_ok, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1357 = asUInt(reset)
node _T_1358 = eq(_T_1357, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = eq(legal_source, UInt<1>(0h0))
when _T_1359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1363 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1364 = asUInt(reset)
node _T_1365 = eq(_T_1364, UInt<1>(0h0))
when _T_1365 :
node _T_1366 = eq(_T_1363, UInt<1>(0h0))
when _T_1366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1363, UInt<1>(0h1), "") : assert_90
node _T_1367 = eq(io.in.b.bits.mask, mask_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_91
node _T_1371 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_92
node _T_1375 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1375 :
node _T_1376 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1377 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1378 = and(_T_1376, _T_1377)
node _T_1379 = or(UInt<1>(0h0), _T_1378)
node _T_1380 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1381 = cvt(_T_1380)
node _T_1382 = and(_T_1381, asSInt(UInt<14>(0h2000)))
node _T_1383 = asSInt(_T_1382)
node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0)))
node _T_1385 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1386 = cvt(_T_1385)
node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000)))
node _T_1388 = asSInt(_T_1387)
node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0)))
node _T_1390 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1391 = cvt(_T_1390)
node _T_1392 = and(_T_1391, asSInt(UInt<17>(0h10000)))
node _T_1393 = asSInt(_T_1392)
node _T_1394 = eq(_T_1393, asSInt(UInt<1>(0h0)))
node _T_1395 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1396 = cvt(_T_1395)
node _T_1397 = and(_T_1396, asSInt(UInt<15>(0h4000)))
node _T_1398 = asSInt(_T_1397)
node _T_1399 = eq(_T_1398, asSInt(UInt<1>(0h0)))
node _T_1400 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1401 = cvt(_T_1400)
node _T_1402 = and(_T_1401, asSInt(UInt<13>(0h1000)))
node _T_1403 = asSInt(_T_1402)
node _T_1404 = eq(_T_1403, asSInt(UInt<1>(0h0)))
node _T_1405 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1406 = cvt(_T_1405)
node _T_1407 = and(_T_1406, asSInt(UInt<18>(0h2f000)))
node _T_1408 = asSInt(_T_1407)
node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0)))
node _T_1410 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1411 = cvt(_T_1410)
node _T_1412 = and(_T_1411, asSInt(UInt<17>(0h10000)))
node _T_1413 = asSInt(_T_1412)
node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0)))
node _T_1415 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1416 = cvt(_T_1415)
node _T_1417 = and(_T_1416, asSInt(UInt<13>(0h1000)))
node _T_1418 = asSInt(_T_1417)
node _T_1419 = eq(_T_1418, asSInt(UInt<1>(0h0)))
node _T_1420 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1421 = cvt(_T_1420)
node _T_1422 = and(_T_1421, asSInt(UInt<17>(0h10000)))
node _T_1423 = asSInt(_T_1422)
node _T_1424 = eq(_T_1423, asSInt(UInt<1>(0h0)))
node _T_1425 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1426 = cvt(_T_1425)
node _T_1427 = and(_T_1426, asSInt(UInt<27>(0h4000000)))
node _T_1428 = asSInt(_T_1427)
node _T_1429 = eq(_T_1428, asSInt(UInt<1>(0h0)))
node _T_1430 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1431 = cvt(_T_1430)
node _T_1432 = and(_T_1431, asSInt(UInt<13>(0h1000)))
node _T_1433 = asSInt(_T_1432)
node _T_1434 = eq(_T_1433, asSInt(UInt<1>(0h0)))
node _T_1435 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1436 = cvt(_T_1435)
node _T_1437 = and(_T_1436, asSInt(UInt<29>(0h10000000)))
node _T_1438 = asSInt(_T_1437)
node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0)))
node _T_1440 = or(_T_1384, _T_1389)
node _T_1441 = or(_T_1440, _T_1394)
node _T_1442 = or(_T_1441, _T_1399)
node _T_1443 = or(_T_1442, _T_1404)
node _T_1444 = or(_T_1443, _T_1409)
node _T_1445 = or(_T_1444, _T_1414)
node _T_1446 = or(_T_1445, _T_1419)
node _T_1447 = or(_T_1446, _T_1424)
node _T_1448 = or(_T_1447, _T_1429)
node _T_1449 = or(_T_1448, _T_1434)
node _T_1450 = or(_T_1449, _T_1439)
node _T_1451 = and(_T_1379, _T_1450)
node _T_1452 = or(UInt<1>(0h0), _T_1451)
node _T_1453 = and(UInt<1>(0h0), _T_1452)
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(_T_1453, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1453, UInt<1>(0h1), "") : assert_93
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(address_ok, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(legal_source, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1463 = asUInt(reset)
node _T_1464 = eq(_T_1463, UInt<1>(0h0))
when _T_1464 :
node _T_1465 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1466 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1467 = asUInt(reset)
node _T_1468 = eq(_T_1467, UInt<1>(0h0))
when _T_1468 :
node _T_1469 = eq(_T_1466, UInt<1>(0h0))
when _T_1469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1466, UInt<1>(0h1), "") : assert_97
node _T_1470 = eq(io.in.b.bits.mask, mask_1)
node _T_1471 = asUInt(reset)
node _T_1472 = eq(_T_1471, UInt<1>(0h0))
when _T_1472 :
node _T_1473 = eq(_T_1470, UInt<1>(0h0))
when _T_1473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1470, UInt<1>(0h1), "") : assert_98
node _T_1474 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1475 = asUInt(reset)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
when _T_1476 :
node _T_1477 = eq(_T_1474, UInt<1>(0h0))
when _T_1477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1474, UInt<1>(0h1), "") : assert_99
node _T_1478 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1480 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1481 = and(_T_1479, _T_1480)
node _T_1482 = or(UInt<1>(0h0), _T_1481)
node _T_1483 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1484 = cvt(_T_1483)
node _T_1485 = and(_T_1484, asSInt(UInt<14>(0h2000)))
node _T_1486 = asSInt(_T_1485)
node _T_1487 = eq(_T_1486, asSInt(UInt<1>(0h0)))
node _T_1488 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1489 = cvt(_T_1488)
node _T_1490 = and(_T_1489, asSInt(UInt<13>(0h1000)))
node _T_1491 = asSInt(_T_1490)
node _T_1492 = eq(_T_1491, asSInt(UInt<1>(0h0)))
node _T_1493 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1494 = cvt(_T_1493)
node _T_1495 = and(_T_1494, asSInt(UInt<17>(0h10000)))
node _T_1496 = asSInt(_T_1495)
node _T_1497 = eq(_T_1496, asSInt(UInt<1>(0h0)))
node _T_1498 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1499 = cvt(_T_1498)
node _T_1500 = and(_T_1499, asSInt(UInt<15>(0h4000)))
node _T_1501 = asSInt(_T_1500)
node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0)))
node _T_1503 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1504 = cvt(_T_1503)
node _T_1505 = and(_T_1504, asSInt(UInt<13>(0h1000)))
node _T_1506 = asSInt(_T_1505)
node _T_1507 = eq(_T_1506, asSInt(UInt<1>(0h0)))
node _T_1508 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1509 = cvt(_T_1508)
node _T_1510 = and(_T_1509, asSInt(UInt<18>(0h2f000)))
node _T_1511 = asSInt(_T_1510)
node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0)))
node _T_1513 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1514 = cvt(_T_1513)
node _T_1515 = and(_T_1514, asSInt(UInt<17>(0h10000)))
node _T_1516 = asSInt(_T_1515)
node _T_1517 = eq(_T_1516, asSInt(UInt<1>(0h0)))
node _T_1518 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1519 = cvt(_T_1518)
node _T_1520 = and(_T_1519, asSInt(UInt<13>(0h1000)))
node _T_1521 = asSInt(_T_1520)
node _T_1522 = eq(_T_1521, asSInt(UInt<1>(0h0)))
node _T_1523 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1524 = cvt(_T_1523)
node _T_1525 = and(_T_1524, asSInt(UInt<17>(0h10000)))
node _T_1526 = asSInt(_T_1525)
node _T_1527 = eq(_T_1526, asSInt(UInt<1>(0h0)))
node _T_1528 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1529 = cvt(_T_1528)
node _T_1530 = and(_T_1529, asSInt(UInt<27>(0h4000000)))
node _T_1531 = asSInt(_T_1530)
node _T_1532 = eq(_T_1531, asSInt(UInt<1>(0h0)))
node _T_1533 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1534 = cvt(_T_1533)
node _T_1535 = and(_T_1534, asSInt(UInt<13>(0h1000)))
node _T_1536 = asSInt(_T_1535)
node _T_1537 = eq(_T_1536, asSInt(UInt<1>(0h0)))
node _T_1538 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1539 = cvt(_T_1538)
node _T_1540 = and(_T_1539, asSInt(UInt<29>(0h10000000)))
node _T_1541 = asSInt(_T_1540)
node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0)))
node _T_1543 = or(_T_1487, _T_1492)
node _T_1544 = or(_T_1543, _T_1497)
node _T_1545 = or(_T_1544, _T_1502)
node _T_1546 = or(_T_1545, _T_1507)
node _T_1547 = or(_T_1546, _T_1512)
node _T_1548 = or(_T_1547, _T_1517)
node _T_1549 = or(_T_1548, _T_1522)
node _T_1550 = or(_T_1549, _T_1527)
node _T_1551 = or(_T_1550, _T_1532)
node _T_1552 = or(_T_1551, _T_1537)
node _T_1553 = or(_T_1552, _T_1542)
node _T_1554 = and(_T_1482, _T_1553)
node _T_1555 = or(UInt<1>(0h0), _T_1554)
node _T_1556 = and(UInt<1>(0h0), _T_1555)
node _T_1557 = asUInt(reset)
node _T_1558 = eq(_T_1557, UInt<1>(0h0))
when _T_1558 :
node _T_1559 = eq(_T_1556, UInt<1>(0h0))
when _T_1559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1556, UInt<1>(0h1), "") : assert_100
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(address_ok, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1563 = asUInt(reset)
node _T_1564 = eq(_T_1563, UInt<1>(0h0))
when _T_1564 :
node _T_1565 = eq(legal_source, UInt<1>(0h0))
when _T_1565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1566 = asUInt(reset)
node _T_1567 = eq(_T_1566, UInt<1>(0h0))
when _T_1567 :
node _T_1568 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1569 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1570 = asUInt(reset)
node _T_1571 = eq(_T_1570, UInt<1>(0h0))
when _T_1571 :
node _T_1572 = eq(_T_1569, UInt<1>(0h0))
when _T_1572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1569, UInt<1>(0h1), "") : assert_104
node _T_1573 = eq(io.in.b.bits.mask, mask_1)
node _T_1574 = asUInt(reset)
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
when _T_1575 :
node _T_1576 = eq(_T_1573, UInt<1>(0h0))
when _T_1576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1573, UInt<1>(0h1), "") : assert_105
node _T_1577 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1577 :
node _T_1578 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1579 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1580 = and(_T_1578, _T_1579)
node _T_1581 = or(UInt<1>(0h0), _T_1580)
node _T_1582 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1583 = cvt(_T_1582)
node _T_1584 = and(_T_1583, asSInt(UInt<14>(0h2000)))
node _T_1585 = asSInt(_T_1584)
node _T_1586 = eq(_T_1585, asSInt(UInt<1>(0h0)))
node _T_1587 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1588 = cvt(_T_1587)
node _T_1589 = and(_T_1588, asSInt(UInt<13>(0h1000)))
node _T_1590 = asSInt(_T_1589)
node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0)))
node _T_1592 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1593 = cvt(_T_1592)
node _T_1594 = and(_T_1593, asSInt(UInt<17>(0h10000)))
node _T_1595 = asSInt(_T_1594)
node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0)))
node _T_1597 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1598 = cvt(_T_1597)
node _T_1599 = and(_T_1598, asSInt(UInt<15>(0h4000)))
node _T_1600 = asSInt(_T_1599)
node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0)))
node _T_1602 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<13>(0h1000)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1608 = cvt(_T_1607)
node _T_1609 = and(_T_1608, asSInt(UInt<18>(0h2f000)))
node _T_1610 = asSInt(_T_1609)
node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0)))
node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1613 = cvt(_T_1612)
node _T_1614 = and(_T_1613, asSInt(UInt<17>(0h10000)))
node _T_1615 = asSInt(_T_1614)
node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0)))
node _T_1617 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1618 = cvt(_T_1617)
node _T_1619 = and(_T_1618, asSInt(UInt<13>(0h1000)))
node _T_1620 = asSInt(_T_1619)
node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0)))
node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1623 = cvt(_T_1622)
node _T_1624 = and(_T_1623, asSInt(UInt<17>(0h10000)))
node _T_1625 = asSInt(_T_1624)
node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0)))
node _T_1627 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1628 = cvt(_T_1627)
node _T_1629 = and(_T_1628, asSInt(UInt<27>(0h4000000)))
node _T_1630 = asSInt(_T_1629)
node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1633 = cvt(_T_1632)
node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000)))
node _T_1635 = asSInt(_T_1634)
node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0)))
node _T_1637 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1638 = cvt(_T_1637)
node _T_1639 = and(_T_1638, asSInt(UInt<29>(0h10000000)))
node _T_1640 = asSInt(_T_1639)
node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0)))
node _T_1642 = or(_T_1586, _T_1591)
node _T_1643 = or(_T_1642, _T_1596)
node _T_1644 = or(_T_1643, _T_1601)
node _T_1645 = or(_T_1644, _T_1606)
node _T_1646 = or(_T_1645, _T_1611)
node _T_1647 = or(_T_1646, _T_1616)
node _T_1648 = or(_T_1647, _T_1621)
node _T_1649 = or(_T_1648, _T_1626)
node _T_1650 = or(_T_1649, _T_1631)
node _T_1651 = or(_T_1650, _T_1636)
node _T_1652 = or(_T_1651, _T_1641)
node _T_1653 = and(_T_1581, _T_1652)
node _T_1654 = or(UInt<1>(0h0), _T_1653)
node _T_1655 = and(UInt<1>(0h0), _T_1654)
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(_T_1655, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1655, UInt<1>(0h1), "") : assert_106
node _T_1659 = asUInt(reset)
node _T_1660 = eq(_T_1659, UInt<1>(0h0))
when _T_1660 :
node _T_1661 = eq(address_ok, UInt<1>(0h0))
when _T_1661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1662 = asUInt(reset)
node _T_1663 = eq(_T_1662, UInt<1>(0h0))
when _T_1663 :
node _T_1664 = eq(legal_source, UInt<1>(0h0))
when _T_1664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1665 = asUInt(reset)
node _T_1666 = eq(_T_1665, UInt<1>(0h0))
when _T_1666 :
node _T_1667 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1668 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1669 = asUInt(reset)
node _T_1670 = eq(_T_1669, UInt<1>(0h0))
when _T_1670 :
node _T_1671 = eq(_T_1668, UInt<1>(0h0))
when _T_1671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1668, UInt<1>(0h1), "") : assert_110
node _T_1672 = not(mask_1)
node _T_1673 = and(io.in.b.bits.mask, _T_1672)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(_T_1674, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1674, UInt<1>(0h1), "") : assert_111
node _T_1678 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1678 :
node _T_1679 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1680 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1681 = and(_T_1679, _T_1680)
node _T_1682 = or(UInt<1>(0h0), _T_1681)
node _T_1683 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1684 = cvt(_T_1683)
node _T_1685 = and(_T_1684, asSInt(UInt<14>(0h2000)))
node _T_1686 = asSInt(_T_1685)
node _T_1687 = eq(_T_1686, asSInt(UInt<1>(0h0)))
node _T_1688 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1689 = cvt(_T_1688)
node _T_1690 = and(_T_1689, asSInt(UInt<13>(0h1000)))
node _T_1691 = asSInt(_T_1690)
node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0)))
node _T_1693 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1694 = cvt(_T_1693)
node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000)))
node _T_1696 = asSInt(_T_1695)
node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0)))
node _T_1698 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1699 = cvt(_T_1698)
node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000)))
node _T_1701 = asSInt(_T_1700)
node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0)))
node _T_1703 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1704 = cvt(_T_1703)
node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000)))
node _T_1706 = asSInt(_T_1705)
node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0)))
node _T_1708 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1709 = cvt(_T_1708)
node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000)))
node _T_1711 = asSInt(_T_1710)
node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0)))
node _T_1713 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1714 = cvt(_T_1713)
node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000)))
node _T_1716 = asSInt(_T_1715)
node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0)))
node _T_1718 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1719 = cvt(_T_1718)
node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000)))
node _T_1721 = asSInt(_T_1720)
node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0)))
node _T_1723 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1724 = cvt(_T_1723)
node _T_1725 = and(_T_1724, asSInt(UInt<17>(0h10000)))
node _T_1726 = asSInt(_T_1725)
node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0)))
node _T_1728 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1729 = cvt(_T_1728)
node _T_1730 = and(_T_1729, asSInt(UInt<27>(0h4000000)))
node _T_1731 = asSInt(_T_1730)
node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0)))
node _T_1733 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1734 = cvt(_T_1733)
node _T_1735 = and(_T_1734, asSInt(UInt<13>(0h1000)))
node _T_1736 = asSInt(_T_1735)
node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0)))
node _T_1738 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1739 = cvt(_T_1738)
node _T_1740 = and(_T_1739, asSInt(UInt<29>(0h10000000)))
node _T_1741 = asSInt(_T_1740)
node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0)))
node _T_1743 = or(_T_1687, _T_1692)
node _T_1744 = or(_T_1743, _T_1697)
node _T_1745 = or(_T_1744, _T_1702)
node _T_1746 = or(_T_1745, _T_1707)
node _T_1747 = or(_T_1746, _T_1712)
node _T_1748 = or(_T_1747, _T_1717)
node _T_1749 = or(_T_1748, _T_1722)
node _T_1750 = or(_T_1749, _T_1727)
node _T_1751 = or(_T_1750, _T_1732)
node _T_1752 = or(_T_1751, _T_1737)
node _T_1753 = or(_T_1752, _T_1742)
node _T_1754 = and(_T_1682, _T_1753)
node _T_1755 = or(UInt<1>(0h0), _T_1754)
node _T_1756 = and(UInt<1>(0h0), _T_1755)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_112
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(address_ok, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(legal_source, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_116
node _T_1773 = eq(io.in.b.bits.mask, mask_1)
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_117
node _T_1777 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1777 :
node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = or(UInt<1>(0h0), _T_1780)
node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1783 = cvt(_T_1782)
node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000)))
node _T_1785 = asSInt(_T_1784)
node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0)))
node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1788 = cvt(_T_1787)
node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000)))
node _T_1790 = asSInt(_T_1789)
node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0)))
node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1793 = cvt(_T_1792)
node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000)))
node _T_1795 = asSInt(_T_1794)
node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0)))
node _T_1797 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1798 = cvt(_T_1797)
node _T_1799 = and(_T_1798, asSInt(UInt<15>(0h4000)))
node _T_1800 = asSInt(_T_1799)
node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0)))
node _T_1802 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1803 = cvt(_T_1802)
node _T_1804 = and(_T_1803, asSInt(UInt<13>(0h1000)))
node _T_1805 = asSInt(_T_1804)
node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0)))
node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1808 = cvt(_T_1807)
node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000)))
node _T_1810 = asSInt(_T_1809)
node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0)))
node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1813 = cvt(_T_1812)
node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000)))
node _T_1815 = asSInt(_T_1814)
node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0)))
node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1818 = cvt(_T_1817)
node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000)))
node _T_1820 = asSInt(_T_1819)
node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0)))
node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1823 = cvt(_T_1822)
node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000)))
node _T_1825 = asSInt(_T_1824)
node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0)))
node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1828 = cvt(_T_1827)
node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000)))
node _T_1830 = asSInt(_T_1829)
node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0)))
node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1833 = cvt(_T_1832)
node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000)))
node _T_1835 = asSInt(_T_1834)
node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0)))
node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1838 = cvt(_T_1837)
node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000)))
node _T_1840 = asSInt(_T_1839)
node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0)))
node _T_1842 = or(_T_1786, _T_1791)
node _T_1843 = or(_T_1842, _T_1796)
node _T_1844 = or(_T_1843, _T_1801)
node _T_1845 = or(_T_1844, _T_1806)
node _T_1846 = or(_T_1845, _T_1811)
node _T_1847 = or(_T_1846, _T_1816)
node _T_1848 = or(_T_1847, _T_1821)
node _T_1849 = or(_T_1848, _T_1826)
node _T_1850 = or(_T_1849, _T_1831)
node _T_1851 = or(_T_1850, _T_1836)
node _T_1852 = or(_T_1851, _T_1841)
node _T_1853 = and(_T_1781, _T_1852)
node _T_1854 = or(UInt<1>(0h0), _T_1853)
node _T_1855 = and(UInt<1>(0h0), _T_1854)
node _T_1856 = asUInt(reset)
node _T_1857 = eq(_T_1856, UInt<1>(0h0))
when _T_1857 :
node _T_1858 = eq(_T_1855, UInt<1>(0h0))
when _T_1858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1855, UInt<1>(0h1), "") : assert_118
node _T_1859 = asUInt(reset)
node _T_1860 = eq(_T_1859, UInt<1>(0h0))
when _T_1860 :
node _T_1861 = eq(address_ok, UInt<1>(0h0))
when _T_1861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1862 = asUInt(reset)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
when _T_1863 :
node _T_1864 = eq(legal_source, UInt<1>(0h0))
when _T_1864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1868 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1869 = asUInt(reset)
node _T_1870 = eq(_T_1869, UInt<1>(0h0))
when _T_1870 :
node _T_1871 = eq(_T_1868, UInt<1>(0h0))
when _T_1871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1868, UInt<1>(0h1), "") : assert_122
node _T_1872 = eq(io.in.b.bits.mask, mask_1)
node _T_1873 = asUInt(reset)
node _T_1874 = eq(_T_1873, UInt<1>(0h0))
when _T_1874 :
node _T_1875 = eq(_T_1872, UInt<1>(0h0))
when _T_1875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1872, UInt<1>(0h1), "") : assert_123
node _T_1876 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1876 :
node _T_1877 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1878 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1879 = and(_T_1877, _T_1878)
node _T_1880 = or(UInt<1>(0h0), _T_1879)
node _T_1881 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1882 = cvt(_T_1881)
node _T_1883 = and(_T_1882, asSInt(UInt<14>(0h2000)))
node _T_1884 = asSInt(_T_1883)
node _T_1885 = eq(_T_1884, asSInt(UInt<1>(0h0)))
node _T_1886 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1887 = cvt(_T_1886)
node _T_1888 = and(_T_1887, asSInt(UInt<13>(0h1000)))
node _T_1889 = asSInt(_T_1888)
node _T_1890 = eq(_T_1889, asSInt(UInt<1>(0h0)))
node _T_1891 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1892 = cvt(_T_1891)
node _T_1893 = and(_T_1892, asSInt(UInt<17>(0h10000)))
node _T_1894 = asSInt(_T_1893)
node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0)))
node _T_1896 = xor(io.in.b.bits.address, UInt<18>(0h20000))
node _T_1897 = cvt(_T_1896)
node _T_1898 = and(_T_1897, asSInt(UInt<15>(0h4000)))
node _T_1899 = asSInt(_T_1898)
node _T_1900 = eq(_T_1899, asSInt(UInt<1>(0h0)))
node _T_1901 = xor(io.in.b.bits.address, UInt<18>(0h24000))
node _T_1902 = cvt(_T_1901)
node _T_1903 = and(_T_1902, asSInt(UInt<13>(0h1000)))
node _T_1904 = asSInt(_T_1903)
node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0)))
node _T_1906 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1907 = cvt(_T_1906)
node _T_1908 = and(_T_1907, asSInt(UInt<18>(0h2f000)))
node _T_1909 = asSInt(_T_1908)
node _T_1910 = eq(_T_1909, asSInt(UInt<1>(0h0)))
node _T_1911 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1912 = cvt(_T_1911)
node _T_1913 = and(_T_1912, asSInt(UInt<17>(0h10000)))
node _T_1914 = asSInt(_T_1913)
node _T_1915 = eq(_T_1914, asSInt(UInt<1>(0h0)))
node _T_1916 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1917 = cvt(_T_1916)
node _T_1918 = and(_T_1917, asSInt(UInt<13>(0h1000)))
node _T_1919 = asSInt(_T_1918)
node _T_1920 = eq(_T_1919, asSInt(UInt<1>(0h0)))
node _T_1921 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1922 = cvt(_T_1921)
node _T_1923 = and(_T_1922, asSInt(UInt<17>(0h10000)))
node _T_1924 = asSInt(_T_1923)
node _T_1925 = eq(_T_1924, asSInt(UInt<1>(0h0)))
node _T_1926 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1927 = cvt(_T_1926)
node _T_1928 = and(_T_1927, asSInt(UInt<27>(0h4000000)))
node _T_1929 = asSInt(_T_1928)
node _T_1930 = eq(_T_1929, asSInt(UInt<1>(0h0)))
node _T_1931 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1932 = cvt(_T_1931)
node _T_1933 = and(_T_1932, asSInt(UInt<13>(0h1000)))
node _T_1934 = asSInt(_T_1933)
node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0)))
node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1937 = cvt(_T_1936)
node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h10000000)))
node _T_1939 = asSInt(_T_1938)
node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0)))
node _T_1941 = or(_T_1885, _T_1890)
node _T_1942 = or(_T_1941, _T_1895)
node _T_1943 = or(_T_1942, _T_1900)
node _T_1944 = or(_T_1943, _T_1905)
node _T_1945 = or(_T_1944, _T_1910)
node _T_1946 = or(_T_1945, _T_1915)
node _T_1947 = or(_T_1946, _T_1920)
node _T_1948 = or(_T_1947, _T_1925)
node _T_1949 = or(_T_1948, _T_1930)
node _T_1950 = or(_T_1949, _T_1935)
node _T_1951 = or(_T_1950, _T_1940)
node _T_1952 = and(_T_1880, _T_1951)
node _T_1953 = or(UInt<1>(0h0), _T_1952)
node _T_1954 = and(UInt<1>(0h0), _T_1953)
node _T_1955 = asUInt(reset)
node _T_1956 = eq(_T_1955, UInt<1>(0h0))
when _T_1956 :
node _T_1957 = eq(_T_1954, UInt<1>(0h0))
when _T_1957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1954, UInt<1>(0h1), "") : assert_124
node _T_1958 = asUInt(reset)
node _T_1959 = eq(_T_1958, UInt<1>(0h0))
when _T_1959 :
node _T_1960 = eq(address_ok, UInt<1>(0h0))
when _T_1960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1961 = asUInt(reset)
node _T_1962 = eq(_T_1961, UInt<1>(0h0))
when _T_1962 :
node _T_1963 = eq(legal_source, UInt<1>(0h0))
when _T_1963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1964 = asUInt(reset)
node _T_1965 = eq(_T_1964, UInt<1>(0h0))
when _T_1965 :
node _T_1966 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1967 = eq(io.in.b.bits.mask, mask_1)
node _T_1968 = asUInt(reset)
node _T_1969 = eq(_T_1968, UInt<1>(0h0))
when _T_1969 :
node _T_1970 = eq(_T_1967, UInt<1>(0h0))
when _T_1970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1967, UInt<1>(0h1), "") : assert_128
node _T_1971 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1972 = asUInt(reset)
node _T_1973 = eq(_T_1972, UInt<1>(0h0))
when _T_1973 :
node _T_1974 = eq(_T_1971, UInt<1>(0h0))
when _T_1974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1971, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1975 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1976 = asUInt(reset)
node _T_1977 = eq(_T_1976, UInt<1>(0h0))
when _T_1977 :
node _T_1978 = eq(_T_1975, UInt<1>(0h0))
when _T_1978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1975, UInt<1>(0h1), "") : assert_130
node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_2 : UInt<1>[2]
connect _source_ok_WIRE_2[0], _source_ok_T_4
connect _source_ok_WIRE_2[1], _source_ok_T_5
node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<13>(0h1000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<17>(0h10000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<18>(0h20000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<18>(0h21000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<13>(0h1000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<18>(0h22000))
node _address_ok_T_131 = cvt(_address_ok_T_130)
node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<13>(0h1000)))
node _address_ok_T_133 = asSInt(_address_ok_T_132)
node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0)))
node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<18>(0h23000))
node _address_ok_T_136 = cvt(_address_ok_T_135)
node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000)))
node _address_ok_T_138 = asSInt(_address_ok_T_137)
node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0)))
node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<18>(0h24000))
node _address_ok_T_141 = cvt(_address_ok_T_140)
node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<13>(0h1000)))
node _address_ok_T_143 = asSInt(_address_ok_T_142)
node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0)))
node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_146 = cvt(_address_ok_T_145)
node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000)))
node _address_ok_T_148 = asSInt(_address_ok_T_147)
node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0)))
node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_151 = cvt(_address_ok_T_150)
node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000)))
node _address_ok_T_153 = asSInt(_address_ok_T_152)
node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0)))
node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_156 = cvt(_address_ok_T_155)
node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000)))
node _address_ok_T_158 = asSInt(_address_ok_T_157)
node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0)))
node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_161 = cvt(_address_ok_T_160)
node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000)))
node _address_ok_T_163 = asSInt(_address_ok_T_162)
node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0)))
node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_166 = cvt(_address_ok_T_165)
node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000)))
node _address_ok_T_168 = asSInt(_address_ok_T_167)
node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0)))
node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_171 = cvt(_address_ok_T_170)
node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_173 = asSInt(_address_ok_T_172)
node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0)))
node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_176 = cvt(_address_ok_T_175)
node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000)))
node _address_ok_T_178 = asSInt(_address_ok_T_177)
node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0)))
node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_181 = cvt(_address_ok_T_180)
node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_183 = asSInt(_address_ok_T_182)
node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[17]
connect _address_ok_WIRE_1[0], _address_ok_T_104
connect _address_ok_WIRE_1[1], _address_ok_T_109
connect _address_ok_WIRE_1[2], _address_ok_T_114
connect _address_ok_WIRE_1[3], _address_ok_T_119
connect _address_ok_WIRE_1[4], _address_ok_T_124
connect _address_ok_WIRE_1[5], _address_ok_T_129
connect _address_ok_WIRE_1[6], _address_ok_T_134
connect _address_ok_WIRE_1[7], _address_ok_T_139
connect _address_ok_WIRE_1[8], _address_ok_T_144
connect _address_ok_WIRE_1[9], _address_ok_T_149
connect _address_ok_WIRE_1[10], _address_ok_T_154
connect _address_ok_WIRE_1[11], _address_ok_T_159
connect _address_ok_WIRE_1[12], _address_ok_T_164
connect _address_ok_WIRE_1[13], _address_ok_T_169
connect _address_ok_WIRE_1[14], _address_ok_T_174
connect _address_ok_WIRE_1[15], _address_ok_T_179
connect _address_ok_WIRE_1[16], _address_ok_T_184
node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2])
node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3])
node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4])
node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5])
node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6])
node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7])
node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8])
node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9])
node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10])
node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11])
node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12])
node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13])
node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14])
node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15])
node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16])
node _T_1979 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1980 = eq(_T_1979, UInt<1>(0h0))
node _T_1981 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1982 = cvt(_T_1981)
node _T_1983 = and(_T_1982, asSInt(UInt<1>(0h0)))
node _T_1984 = asSInt(_T_1983)
node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0)))
node _T_1986 = or(_T_1980, _T_1985)
node _T_1987 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1988 = eq(_T_1987, UInt<1>(0h0))
node _T_1989 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1990 = cvt(_T_1989)
node _T_1991 = and(_T_1990, asSInt(UInt<1>(0h0)))
node _T_1992 = asSInt(_T_1991)
node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0)))
node _T_1994 = or(_T_1988, _T_1993)
node _T_1995 = and(_T_1986, _T_1994)
node _T_1996 = asUInt(reset)
node _T_1997 = eq(_T_1996, UInt<1>(0h0))
when _T_1997 :
node _T_1998 = eq(_T_1995, UInt<1>(0h0))
when _T_1998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1995, UInt<1>(0h1), "") : assert_131
node _T_1999 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1999 :
node _T_2000 = asUInt(reset)
node _T_2001 = eq(_T_2000, UInt<1>(0h0))
when _T_2001 :
node _T_2002 = eq(address_ok_1, UInt<1>(0h0))
when _T_2002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_2003 = asUInt(reset)
node _T_2004 = eq(_T_2003, UInt<1>(0h0))
when _T_2004 :
node _T_2005 = eq(source_ok_2, UInt<1>(0h0))
when _T_2005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_2006 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2007 = asUInt(reset)
node _T_2008 = eq(_T_2007, UInt<1>(0h0))
when _T_2008 :
node _T_2009 = eq(_T_2006, UInt<1>(0h0))
when _T_2009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_2006, UInt<1>(0h1), "") : assert_134
node _T_2010 = asUInt(reset)
node _T_2011 = eq(_T_2010, UInt<1>(0h0))
when _T_2011 :
node _T_2012 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_2013 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2014 = asUInt(reset)
node _T_2015 = eq(_T_2014, UInt<1>(0h0))
when _T_2015 :
node _T_2016 = eq(_T_2013, UInt<1>(0h0))
when _T_2016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_2013, UInt<1>(0h1), "") : assert_136
node _T_2017 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2018 = asUInt(reset)
node _T_2019 = eq(_T_2018, UInt<1>(0h0))
when _T_2019 :
node _T_2020 = eq(_T_2017, UInt<1>(0h0))
when _T_2020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_2017, UInt<1>(0h1), "") : assert_137
node _T_2021 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_2021 :
node _T_2022 = asUInt(reset)
node _T_2023 = eq(_T_2022, UInt<1>(0h0))
when _T_2023 :
node _T_2024 = eq(address_ok_1, UInt<1>(0h0))
when _T_2024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_2025 = asUInt(reset)
node _T_2026 = eq(_T_2025, UInt<1>(0h0))
when _T_2026 :
node _T_2027 = eq(source_ok_2, UInt<1>(0h0))
when _T_2027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_2028 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2029 = asUInt(reset)
node _T_2030 = eq(_T_2029, UInt<1>(0h0))
when _T_2030 :
node _T_2031 = eq(_T_2028, UInt<1>(0h0))
when _T_2031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_2028, UInt<1>(0h1), "") : assert_140
node _T_2032 = asUInt(reset)
node _T_2033 = eq(_T_2032, UInt<1>(0h0))
when _T_2033 :
node _T_2034 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_2035 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2036 = asUInt(reset)
node _T_2037 = eq(_T_2036, UInt<1>(0h0))
when _T_2037 :
node _T_2038 = eq(_T_2035, UInt<1>(0h0))
when _T_2038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_2035, UInt<1>(0h1), "") : assert_142
node _T_2039 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_2039 :
node _T_2040 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2041 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2042 = and(_T_2040, _T_2041)
node _T_2043 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2044 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2045 = or(_T_2043, _T_2044)
node _T_2046 = and(_T_2042, _T_2045)
node _T_2047 = or(UInt<1>(0h0), _T_2046)
node _T_2048 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2050 = cvt(_T_2049)
node _T_2051 = and(_T_2050, asSInt(UInt<14>(0h2000)))
node _T_2052 = asSInt(_T_2051)
node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0)))
node _T_2054 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2055 = cvt(_T_2054)
node _T_2056 = and(_T_2055, asSInt(UInt<13>(0h1000)))
node _T_2057 = asSInt(_T_2056)
node _T_2058 = eq(_T_2057, asSInt(UInt<1>(0h0)))
node _T_2059 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2060 = cvt(_T_2059)
node _T_2061 = and(_T_2060, asSInt(UInt<17>(0h10000)))
node _T_2062 = asSInt(_T_2061)
node _T_2063 = eq(_T_2062, asSInt(UInt<1>(0h0)))
node _T_2064 = xor(io.in.c.bits.address, UInt<18>(0h20000))
node _T_2065 = cvt(_T_2064)
node _T_2066 = and(_T_2065, asSInt(UInt<15>(0h4000)))
node _T_2067 = asSInt(_T_2066)
node _T_2068 = eq(_T_2067, asSInt(UInt<1>(0h0)))
node _T_2069 = xor(io.in.c.bits.address, UInt<18>(0h24000))
node _T_2070 = cvt(_T_2069)
node _T_2071 = and(_T_2070, asSInt(UInt<13>(0h1000)))
node _T_2072 = asSInt(_T_2071)
node _T_2073 = eq(_T_2072, asSInt(UInt<1>(0h0)))
node _T_2074 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2075 = cvt(_T_2074)
node _T_2076 = and(_T_2075, asSInt(UInt<18>(0h2f000)))
node _T_2077 = asSInt(_T_2076)
node _T_2078 = eq(_T_2077, asSInt(UInt<1>(0h0)))
node _T_2079 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2080 = cvt(_T_2079)
node _T_2081 = and(_T_2080, asSInt(UInt<17>(0h10000)))
node _T_2082 = asSInt(_T_2081)
node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0)))
node _T_2084 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2085 = cvt(_T_2084)
node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000)))
node _T_2087 = asSInt(_T_2086)
node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0)))
node _T_2089 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2090 = cvt(_T_2089)
node _T_2091 = and(_T_2090, asSInt(UInt<27>(0h4000000)))
node _T_2092 = asSInt(_T_2091)
node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0)))
node _T_2094 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2095 = cvt(_T_2094)
node _T_2096 = and(_T_2095, asSInt(UInt<13>(0h1000)))
node _T_2097 = asSInt(_T_2096)
node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0)))
node _T_2099 = or(_T_2053, _T_2058)
node _T_2100 = or(_T_2099, _T_2063)
node _T_2101 = or(_T_2100, _T_2068)
node _T_2102 = or(_T_2101, _T_2073)
node _T_2103 = or(_T_2102, _T_2078)
node _T_2104 = or(_T_2103, _T_2083)
node _T_2105 = or(_T_2104, _T_2088)
node _T_2106 = or(_T_2105, _T_2093)
node _T_2107 = or(_T_2106, _T_2098)
node _T_2108 = and(_T_2048, _T_2107)
node _T_2109 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2110 = or(UInt<1>(0h0), _T_2109)
node _T_2111 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2112 = cvt(_T_2111)
node _T_2113 = and(_T_2112, asSInt(UInt<17>(0h10000)))
node _T_2114 = asSInt(_T_2113)
node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0)))
node _T_2116 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2117 = cvt(_T_2116)
node _T_2118 = and(_T_2117, asSInt(UInt<29>(0h10000000)))
node _T_2119 = asSInt(_T_2118)
node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0)))
node _T_2121 = or(_T_2115, _T_2120)
node _T_2122 = and(_T_2110, _T_2121)
node _T_2123 = or(UInt<1>(0h0), _T_2108)
node _T_2124 = or(_T_2123, _T_2122)
node _T_2125 = and(_T_2047, _T_2124)
node _T_2126 = asUInt(reset)
node _T_2127 = eq(_T_2126, UInt<1>(0h0))
when _T_2127 :
node _T_2128 = eq(_T_2125, UInt<1>(0h0))
when _T_2128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2125, UInt<1>(0h1), "") : assert_143
node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2130 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_6 : UInt<1>[2]
connect _WIRE_6[0], _T_2129
connect _WIRE_6[1], _T_2130
node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2132 = mux(_WIRE_6[0], _T_2131, UInt<1>(0h0))
node _T_2133 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2134 = or(_T_2132, _T_2133)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2134
node _T_2135 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2136 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2137 = and(_T_2135, _T_2136)
node _T_2138 = or(UInt<1>(0h0), _T_2137)
node _T_2139 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2140 = cvt(_T_2139)
node _T_2141 = and(_T_2140, asSInt(UInt<14>(0h2000)))
node _T_2142 = asSInt(_T_2141)
node _T_2143 = eq(_T_2142, asSInt(UInt<1>(0h0)))
node _T_2144 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2145 = cvt(_T_2144)
node _T_2146 = and(_T_2145, asSInt(UInt<13>(0h1000)))
node _T_2147 = asSInt(_T_2146)
node _T_2148 = eq(_T_2147, asSInt(UInt<1>(0h0)))
node _T_2149 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2150 = cvt(_T_2149)
node _T_2151 = and(_T_2150, asSInt(UInt<17>(0h10000)))
node _T_2152 = asSInt(_T_2151)
node _T_2153 = eq(_T_2152, asSInt(UInt<1>(0h0)))
node _T_2154 = xor(io.in.c.bits.address, UInt<18>(0h20000))
node _T_2155 = cvt(_T_2154)
node _T_2156 = and(_T_2155, asSInt(UInt<15>(0h4000)))
node _T_2157 = asSInt(_T_2156)
node _T_2158 = eq(_T_2157, asSInt(UInt<1>(0h0)))
node _T_2159 = xor(io.in.c.bits.address, UInt<18>(0h24000))
node _T_2160 = cvt(_T_2159)
node _T_2161 = and(_T_2160, asSInt(UInt<13>(0h1000)))
node _T_2162 = asSInt(_T_2161)
node _T_2163 = eq(_T_2162, asSInt(UInt<1>(0h0)))
node _T_2164 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2165 = cvt(_T_2164)
node _T_2166 = and(_T_2165, asSInt(UInt<18>(0h2f000)))
node _T_2167 = asSInt(_T_2166)
node _T_2168 = eq(_T_2167, asSInt(UInt<1>(0h0)))
node _T_2169 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2170 = cvt(_T_2169)
node _T_2171 = and(_T_2170, asSInt(UInt<17>(0h10000)))
node _T_2172 = asSInt(_T_2171)
node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0)))
node _T_2174 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2175 = cvt(_T_2174)
node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000)))
node _T_2177 = asSInt(_T_2176)
node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0)))
node _T_2179 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2180 = cvt(_T_2179)
node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000)))
node _T_2182 = asSInt(_T_2181)
node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0)))
node _T_2184 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2185 = cvt(_T_2184)
node _T_2186 = and(_T_2185, asSInt(UInt<27>(0h4000000)))
node _T_2187 = asSInt(_T_2186)
node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0)))
node _T_2189 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2190 = cvt(_T_2189)
node _T_2191 = and(_T_2190, asSInt(UInt<13>(0h1000)))
node _T_2192 = asSInt(_T_2191)
node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0)))
node _T_2194 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2195 = cvt(_T_2194)
node _T_2196 = and(_T_2195, asSInt(UInt<29>(0h10000000)))
node _T_2197 = asSInt(_T_2196)
node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0)))
node _T_2199 = or(_T_2143, _T_2148)
node _T_2200 = or(_T_2199, _T_2153)
node _T_2201 = or(_T_2200, _T_2158)
node _T_2202 = or(_T_2201, _T_2163)
node _T_2203 = or(_T_2202, _T_2168)
node _T_2204 = or(_T_2203, _T_2173)
node _T_2205 = or(_T_2204, _T_2178)
node _T_2206 = or(_T_2205, _T_2183)
node _T_2207 = or(_T_2206, _T_2188)
node _T_2208 = or(_T_2207, _T_2193)
node _T_2209 = or(_T_2208, _T_2198)
node _T_2210 = and(_T_2138, _T_2209)
node _T_2211 = or(UInt<1>(0h0), _T_2210)
node _T_2212 = and(_WIRE_7, _T_2211)
node _T_2213 = asUInt(reset)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
when _T_2214 :
node _T_2215 = eq(_T_2212, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2212, UInt<1>(0h1), "") : assert_144
node _T_2216 = asUInt(reset)
node _T_2217 = eq(_T_2216, UInt<1>(0h0))
when _T_2217 :
node _T_2218 = eq(source_ok_2, UInt<1>(0h0))
when _T_2218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2219 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2220 = asUInt(reset)
node _T_2221 = eq(_T_2220, UInt<1>(0h0))
when _T_2221 :
node _T_2222 = eq(_T_2219, UInt<1>(0h0))
when _T_2222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2219, UInt<1>(0h1), "") : assert_146
node _T_2223 = asUInt(reset)
node _T_2224 = eq(_T_2223, UInt<1>(0h0))
when _T_2224 :
node _T_2225 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2226 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(_T_2226, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2226, UInt<1>(0h1), "") : assert_148
node _T_2230 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2231 = asUInt(reset)
node _T_2232 = eq(_T_2231, UInt<1>(0h0))
when _T_2232 :
node _T_2233 = eq(_T_2230, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2230, UInt<1>(0h1), "") : assert_149
node _T_2234 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2234 :
node _T_2235 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2236 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2237 = and(_T_2235, _T_2236)
node _T_2238 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2239 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2240 = or(_T_2238, _T_2239)
node _T_2241 = and(_T_2237, _T_2240)
node _T_2242 = or(UInt<1>(0h0), _T_2241)
node _T_2243 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2244 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2245 = cvt(_T_2244)
node _T_2246 = and(_T_2245, asSInt(UInt<14>(0h2000)))
node _T_2247 = asSInt(_T_2246)
node _T_2248 = eq(_T_2247, asSInt(UInt<1>(0h0)))
node _T_2249 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2250 = cvt(_T_2249)
node _T_2251 = and(_T_2250, asSInt(UInt<13>(0h1000)))
node _T_2252 = asSInt(_T_2251)
node _T_2253 = eq(_T_2252, asSInt(UInt<1>(0h0)))
node _T_2254 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2255 = cvt(_T_2254)
node _T_2256 = and(_T_2255, asSInt(UInt<17>(0h10000)))
node _T_2257 = asSInt(_T_2256)
node _T_2258 = eq(_T_2257, asSInt(UInt<1>(0h0)))
node _T_2259 = xor(io.in.c.bits.address, UInt<18>(0h20000))
node _T_2260 = cvt(_T_2259)
node _T_2261 = and(_T_2260, asSInt(UInt<15>(0h4000)))
node _T_2262 = asSInt(_T_2261)
node _T_2263 = eq(_T_2262, asSInt(UInt<1>(0h0)))
node _T_2264 = xor(io.in.c.bits.address, UInt<18>(0h24000))
node _T_2265 = cvt(_T_2264)
node _T_2266 = and(_T_2265, asSInt(UInt<13>(0h1000)))
node _T_2267 = asSInt(_T_2266)
node _T_2268 = eq(_T_2267, asSInt(UInt<1>(0h0)))
node _T_2269 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2270 = cvt(_T_2269)
node _T_2271 = and(_T_2270, asSInt(UInt<18>(0h2f000)))
node _T_2272 = asSInt(_T_2271)
node _T_2273 = eq(_T_2272, asSInt(UInt<1>(0h0)))
node _T_2274 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2275 = cvt(_T_2274)
node _T_2276 = and(_T_2275, asSInt(UInt<17>(0h10000)))
node _T_2277 = asSInt(_T_2276)
node _T_2278 = eq(_T_2277, asSInt(UInt<1>(0h0)))
node _T_2279 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2280 = cvt(_T_2279)
node _T_2281 = and(_T_2280, asSInt(UInt<13>(0h1000)))
node _T_2282 = asSInt(_T_2281)
node _T_2283 = eq(_T_2282, asSInt(UInt<1>(0h0)))
node _T_2284 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2285 = cvt(_T_2284)
node _T_2286 = and(_T_2285, asSInt(UInt<27>(0h4000000)))
node _T_2287 = asSInt(_T_2286)
node _T_2288 = eq(_T_2287, asSInt(UInt<1>(0h0)))
node _T_2289 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2290 = cvt(_T_2289)
node _T_2291 = and(_T_2290, asSInt(UInt<13>(0h1000)))
node _T_2292 = asSInt(_T_2291)
node _T_2293 = eq(_T_2292, asSInt(UInt<1>(0h0)))
node _T_2294 = or(_T_2248, _T_2253)
node _T_2295 = or(_T_2294, _T_2258)
node _T_2296 = or(_T_2295, _T_2263)
node _T_2297 = or(_T_2296, _T_2268)
node _T_2298 = or(_T_2297, _T_2273)
node _T_2299 = or(_T_2298, _T_2278)
node _T_2300 = or(_T_2299, _T_2283)
node _T_2301 = or(_T_2300, _T_2288)
node _T_2302 = or(_T_2301, _T_2293)
node _T_2303 = and(_T_2243, _T_2302)
node _T_2304 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2305 = or(UInt<1>(0h0), _T_2304)
node _T_2306 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2307 = cvt(_T_2306)
node _T_2308 = and(_T_2307, asSInt(UInt<17>(0h10000)))
node _T_2309 = asSInt(_T_2308)
node _T_2310 = eq(_T_2309, asSInt(UInt<1>(0h0)))
node _T_2311 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2312 = cvt(_T_2311)
node _T_2313 = and(_T_2312, asSInt(UInt<29>(0h10000000)))
node _T_2314 = asSInt(_T_2313)
node _T_2315 = eq(_T_2314, asSInt(UInt<1>(0h0)))
node _T_2316 = or(_T_2310, _T_2315)
node _T_2317 = and(_T_2305, _T_2316)
node _T_2318 = or(UInt<1>(0h0), _T_2303)
node _T_2319 = or(_T_2318, _T_2317)
node _T_2320 = and(_T_2242, _T_2319)
node _T_2321 = asUInt(reset)
node _T_2322 = eq(_T_2321, UInt<1>(0h0))
when _T_2322 :
node _T_2323 = eq(_T_2320, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2320, UInt<1>(0h1), "") : assert_150
node _T_2324 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2325 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_8 : UInt<1>[2]
connect _WIRE_8[0], _T_2324
connect _WIRE_8[1], _T_2325
node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2327 = mux(_WIRE_8[0], _T_2326, UInt<1>(0h0))
node _T_2328 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2329 = or(_T_2327, _T_2328)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2329
node _T_2330 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2331 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2332 = and(_T_2330, _T_2331)
node _T_2333 = or(UInt<1>(0h0), _T_2332)
node _T_2334 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2335 = cvt(_T_2334)
node _T_2336 = and(_T_2335, asSInt(UInt<14>(0h2000)))
node _T_2337 = asSInt(_T_2336)
node _T_2338 = eq(_T_2337, asSInt(UInt<1>(0h0)))
node _T_2339 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2340 = cvt(_T_2339)
node _T_2341 = and(_T_2340, asSInt(UInt<13>(0h1000)))
node _T_2342 = asSInt(_T_2341)
node _T_2343 = eq(_T_2342, asSInt(UInt<1>(0h0)))
node _T_2344 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2345 = cvt(_T_2344)
node _T_2346 = and(_T_2345, asSInt(UInt<17>(0h10000)))
node _T_2347 = asSInt(_T_2346)
node _T_2348 = eq(_T_2347, asSInt(UInt<1>(0h0)))
node _T_2349 = xor(io.in.c.bits.address, UInt<18>(0h20000))
node _T_2350 = cvt(_T_2349)
node _T_2351 = and(_T_2350, asSInt(UInt<15>(0h4000)))
node _T_2352 = asSInt(_T_2351)
node _T_2353 = eq(_T_2352, asSInt(UInt<1>(0h0)))
node _T_2354 = xor(io.in.c.bits.address, UInt<18>(0h24000))
node _T_2355 = cvt(_T_2354)
node _T_2356 = and(_T_2355, asSInt(UInt<13>(0h1000)))
node _T_2357 = asSInt(_T_2356)
node _T_2358 = eq(_T_2357, asSInt(UInt<1>(0h0)))
node _T_2359 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2360 = cvt(_T_2359)
node _T_2361 = and(_T_2360, asSInt(UInt<18>(0h2f000)))
node _T_2362 = asSInt(_T_2361)
node _T_2363 = eq(_T_2362, asSInt(UInt<1>(0h0)))
node _T_2364 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2365 = cvt(_T_2364)
node _T_2366 = and(_T_2365, asSInt(UInt<17>(0h10000)))
node _T_2367 = asSInt(_T_2366)
node _T_2368 = eq(_T_2367, asSInt(UInt<1>(0h0)))
node _T_2369 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2370 = cvt(_T_2369)
node _T_2371 = and(_T_2370, asSInt(UInt<13>(0h1000)))
node _T_2372 = asSInt(_T_2371)
node _T_2373 = eq(_T_2372, asSInt(UInt<1>(0h0)))
node _T_2374 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2375 = cvt(_T_2374)
node _T_2376 = and(_T_2375, asSInt(UInt<17>(0h10000)))
node _T_2377 = asSInt(_T_2376)
node _T_2378 = eq(_T_2377, asSInt(UInt<1>(0h0)))
node _T_2379 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2380 = cvt(_T_2379)
node _T_2381 = and(_T_2380, asSInt(UInt<27>(0h4000000)))
node _T_2382 = asSInt(_T_2381)
node _T_2383 = eq(_T_2382, asSInt(UInt<1>(0h0)))
node _T_2384 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2385 = cvt(_T_2384)
node _T_2386 = and(_T_2385, asSInt(UInt<13>(0h1000)))
node _T_2387 = asSInt(_T_2386)
node _T_2388 = eq(_T_2387, asSInt(UInt<1>(0h0)))
node _T_2389 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2390 = cvt(_T_2389)
node _T_2391 = and(_T_2390, asSInt(UInt<29>(0h10000000)))
node _T_2392 = asSInt(_T_2391)
node _T_2393 = eq(_T_2392, asSInt(UInt<1>(0h0)))
node _T_2394 = or(_T_2338, _T_2343)
node _T_2395 = or(_T_2394, _T_2348)
node _T_2396 = or(_T_2395, _T_2353)
node _T_2397 = or(_T_2396, _T_2358)
node _T_2398 = or(_T_2397, _T_2363)
node _T_2399 = or(_T_2398, _T_2368)
node _T_2400 = or(_T_2399, _T_2373)
node _T_2401 = or(_T_2400, _T_2378)
node _T_2402 = or(_T_2401, _T_2383)
node _T_2403 = or(_T_2402, _T_2388)
node _T_2404 = or(_T_2403, _T_2393)
node _T_2405 = and(_T_2333, _T_2404)
node _T_2406 = or(UInt<1>(0h0), _T_2405)
node _T_2407 = and(_WIRE_9, _T_2406)
node _T_2408 = asUInt(reset)
node _T_2409 = eq(_T_2408, UInt<1>(0h0))
when _T_2409 :
node _T_2410 = eq(_T_2407, UInt<1>(0h0))
when _T_2410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2407, UInt<1>(0h1), "") : assert_151
node _T_2411 = asUInt(reset)
node _T_2412 = eq(_T_2411, UInt<1>(0h0))
when _T_2412 :
node _T_2413 = eq(source_ok_2, UInt<1>(0h0))
when _T_2413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2414 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2415 = asUInt(reset)
node _T_2416 = eq(_T_2415, UInt<1>(0h0))
when _T_2416 :
node _T_2417 = eq(_T_2414, UInt<1>(0h0))
when _T_2417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2414, UInt<1>(0h1), "") : assert_153
node _T_2418 = asUInt(reset)
node _T_2419 = eq(_T_2418, UInt<1>(0h0))
when _T_2419 :
node _T_2420 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2421 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_155
node _T_2425 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2425 :
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(address_ok_1, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2429 = asUInt(reset)
node _T_2430 = eq(_T_2429, UInt<1>(0h0))
when _T_2430 :
node _T_2431 = eq(source_ok_2, UInt<1>(0h0))
when _T_2431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2432 = asUInt(reset)
node _T_2433 = eq(_T_2432, UInt<1>(0h0))
when _T_2433 :
node _T_2434 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2435 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2436 = asUInt(reset)
node _T_2437 = eq(_T_2436, UInt<1>(0h0))
when _T_2437 :
node _T_2438 = eq(_T_2435, UInt<1>(0h0))
when _T_2438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2435, UInt<1>(0h1), "") : assert_159
node _T_2439 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2440 = asUInt(reset)
node _T_2441 = eq(_T_2440, UInt<1>(0h0))
when _T_2441 :
node _T_2442 = eq(_T_2439, UInt<1>(0h0))
when _T_2442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2439, UInt<1>(0h1), "") : assert_160
node _T_2443 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2443 :
node _T_2444 = asUInt(reset)
node _T_2445 = eq(_T_2444, UInt<1>(0h0))
when _T_2445 :
node _T_2446 = eq(address_ok_1, UInt<1>(0h0))
when _T_2446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2447 = asUInt(reset)
node _T_2448 = eq(_T_2447, UInt<1>(0h0))
when _T_2448 :
node _T_2449 = eq(source_ok_2, UInt<1>(0h0))
when _T_2449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2450 = asUInt(reset)
node _T_2451 = eq(_T_2450, UInt<1>(0h0))
when _T_2451 :
node _T_2452 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2453 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2454 = asUInt(reset)
node _T_2455 = eq(_T_2454, UInt<1>(0h0))
when _T_2455 :
node _T_2456 = eq(_T_2453, UInt<1>(0h0))
when _T_2456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2453, UInt<1>(0h1), "") : assert_164
node _T_2457 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2457 :
node _T_2458 = asUInt(reset)
node _T_2459 = eq(_T_2458, UInt<1>(0h0))
when _T_2459 :
node _T_2460 = eq(address_ok_1, UInt<1>(0h0))
when _T_2460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2461 = asUInt(reset)
node _T_2462 = eq(_T_2461, UInt<1>(0h0))
when _T_2462 :
node _T_2463 = eq(source_ok_2, UInt<1>(0h0))
when _T_2463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2464 = asUInt(reset)
node _T_2465 = eq(_T_2464, UInt<1>(0h0))
when _T_2465 :
node _T_2466 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2467 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2468 = asUInt(reset)
node _T_2469 = eq(_T_2468, UInt<1>(0h0))
when _T_2469 :
node _T_2470 = eq(_T_2467, UInt<1>(0h0))
when _T_2470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2467, UInt<1>(0h1), "") : assert_168
node _T_2471 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2472 = asUInt(reset)
node _T_2473 = eq(_T_2472, UInt<1>(0h0))
when _T_2473 :
node _T_2474 = eq(_T_2471, UInt<1>(0h0))
when _T_2474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2471, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2475 = asUInt(reset)
node _T_2476 = eq(_T_2475, UInt<1>(0h0))
when _T_2476 :
node _T_2477 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2478 = eq(a_first, UInt<1>(0h0))
node _T_2479 = and(io.in.a.valid, _T_2478)
when _T_2479 :
node _T_2480 = eq(io.in.a.bits.opcode, opcode)
node _T_2481 = asUInt(reset)
node _T_2482 = eq(_T_2481, UInt<1>(0h0))
when _T_2482 :
node _T_2483 = eq(_T_2480, UInt<1>(0h0))
when _T_2483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2480, UInt<1>(0h1), "") : assert_171
node _T_2484 = eq(io.in.a.bits.param, param)
node _T_2485 = asUInt(reset)
node _T_2486 = eq(_T_2485, UInt<1>(0h0))
when _T_2486 :
node _T_2487 = eq(_T_2484, UInt<1>(0h0))
when _T_2487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2484, UInt<1>(0h1), "") : assert_172
node _T_2488 = eq(io.in.a.bits.size, size)
node _T_2489 = asUInt(reset)
node _T_2490 = eq(_T_2489, UInt<1>(0h0))
when _T_2490 :
node _T_2491 = eq(_T_2488, UInt<1>(0h0))
when _T_2491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2488, UInt<1>(0h1), "") : assert_173
node _T_2492 = eq(io.in.a.bits.source, source)
node _T_2493 = asUInt(reset)
node _T_2494 = eq(_T_2493, UInt<1>(0h0))
when _T_2494 :
node _T_2495 = eq(_T_2492, UInt<1>(0h0))
when _T_2495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2492, UInt<1>(0h1), "") : assert_174
node _T_2496 = eq(io.in.a.bits.address, address)
node _T_2497 = asUInt(reset)
node _T_2498 = eq(_T_2497, UInt<1>(0h0))
when _T_2498 :
node _T_2499 = eq(_T_2496, UInt<1>(0h0))
when _T_2499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2496, UInt<1>(0h1), "") : assert_175
node _T_2500 = and(io.in.a.ready, io.in.a.valid)
node _T_2501 = and(_T_2500, a_first)
when _T_2501 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2502 = eq(d_first, UInt<1>(0h0))
node _T_2503 = and(io.in.d.valid, _T_2502)
when _T_2503 :
node _T_2504 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(_T_2504, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2504, UInt<1>(0h1), "") : assert_176
node _T_2508 = eq(io.in.d.bits.param, param_1)
node _T_2509 = asUInt(reset)
node _T_2510 = eq(_T_2509, UInt<1>(0h0))
when _T_2510 :
node _T_2511 = eq(_T_2508, UInt<1>(0h0))
when _T_2511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2508, UInt<1>(0h1), "") : assert_177
node _T_2512 = eq(io.in.d.bits.size, size_1)
node _T_2513 = asUInt(reset)
node _T_2514 = eq(_T_2513, UInt<1>(0h0))
when _T_2514 :
node _T_2515 = eq(_T_2512, UInt<1>(0h0))
when _T_2515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2512, UInt<1>(0h1), "") : assert_178
node _T_2516 = eq(io.in.d.bits.source, source_1)
node _T_2517 = asUInt(reset)
node _T_2518 = eq(_T_2517, UInt<1>(0h0))
when _T_2518 :
node _T_2519 = eq(_T_2516, UInt<1>(0h0))
when _T_2519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2516, UInt<1>(0h1), "") : assert_179
node _T_2520 = eq(io.in.d.bits.sink, sink)
node _T_2521 = asUInt(reset)
node _T_2522 = eq(_T_2521, UInt<1>(0h0))
when _T_2522 :
node _T_2523 = eq(_T_2520, UInt<1>(0h0))
when _T_2523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2520, UInt<1>(0h1), "") : assert_180
node _T_2524 = eq(io.in.d.bits.denied, denied)
node _T_2525 = asUInt(reset)
node _T_2526 = eq(_T_2525, UInt<1>(0h0))
when _T_2526 :
node _T_2527 = eq(_T_2524, UInt<1>(0h0))
when _T_2527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2524, UInt<1>(0h1), "") : assert_181
node _T_2528 = and(io.in.d.ready, io.in.d.valid)
node _T_2529 = and(_T_2528, d_first)
when _T_2529 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2530 = eq(b_first, UInt<1>(0h0))
node _T_2531 = and(io.in.b.valid, _T_2530)
when _T_2531 :
node _T_2532 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2533 = asUInt(reset)
node _T_2534 = eq(_T_2533, UInt<1>(0h0))
when _T_2534 :
node _T_2535 = eq(_T_2532, UInt<1>(0h0))
when _T_2535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2532, UInt<1>(0h1), "") : assert_182
node _T_2536 = eq(io.in.b.bits.param, param_2)
node _T_2537 = asUInt(reset)
node _T_2538 = eq(_T_2537, UInt<1>(0h0))
when _T_2538 :
node _T_2539 = eq(_T_2536, UInt<1>(0h0))
when _T_2539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2536, UInt<1>(0h1), "") : assert_183
node _T_2540 = eq(io.in.b.bits.size, size_2)
node _T_2541 = asUInt(reset)
node _T_2542 = eq(_T_2541, UInt<1>(0h0))
when _T_2542 :
node _T_2543 = eq(_T_2540, UInt<1>(0h0))
when _T_2543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2540, UInt<1>(0h1), "") : assert_184
node _T_2544 = eq(io.in.b.bits.source, source_2)
node _T_2545 = asUInt(reset)
node _T_2546 = eq(_T_2545, UInt<1>(0h0))
when _T_2546 :
node _T_2547 = eq(_T_2544, UInt<1>(0h0))
when _T_2547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2544, UInt<1>(0h1), "") : assert_185
node _T_2548 = eq(io.in.b.bits.address, address_1)
node _T_2549 = asUInt(reset)
node _T_2550 = eq(_T_2549, UInt<1>(0h0))
when _T_2550 :
node _T_2551 = eq(_T_2548, UInt<1>(0h0))
when _T_2551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2548, UInt<1>(0h1), "") : assert_186
node _T_2552 = and(io.in.b.ready, io.in.b.valid)
node _T_2553 = and(_T_2552, b_first)
when _T_2553 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2554 = eq(c_first, UInt<1>(0h0))
node _T_2555 = and(io.in.c.valid, _T_2554)
when _T_2555 :
node _T_2556 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2557 = asUInt(reset)
node _T_2558 = eq(_T_2557, UInt<1>(0h0))
when _T_2558 :
node _T_2559 = eq(_T_2556, UInt<1>(0h0))
when _T_2559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2556, UInt<1>(0h1), "") : assert_187
node _T_2560 = eq(io.in.c.bits.param, param_3)
node _T_2561 = asUInt(reset)
node _T_2562 = eq(_T_2561, UInt<1>(0h0))
when _T_2562 :
node _T_2563 = eq(_T_2560, UInt<1>(0h0))
when _T_2563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2560, UInt<1>(0h1), "") : assert_188
node _T_2564 = eq(io.in.c.bits.size, size_3)
node _T_2565 = asUInt(reset)
node _T_2566 = eq(_T_2565, UInt<1>(0h0))
when _T_2566 :
node _T_2567 = eq(_T_2564, UInt<1>(0h0))
when _T_2567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2564, UInt<1>(0h1), "") : assert_189
node _T_2568 = eq(io.in.c.bits.source, source_3)
node _T_2569 = asUInt(reset)
node _T_2570 = eq(_T_2569, UInt<1>(0h0))
when _T_2570 :
node _T_2571 = eq(_T_2568, UInt<1>(0h0))
when _T_2571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2568, UInt<1>(0h1), "") : assert_190
node _T_2572 = eq(io.in.c.bits.address, address_2)
node _T_2573 = asUInt(reset)
node _T_2574 = eq(_T_2573, UInt<1>(0h0))
when _T_2574 :
node _T_2575 = eq(_T_2572, UInt<1>(0h0))
when _T_2575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2572, UInt<1>(0h1), "") : assert_191
node _T_2576 = and(io.in.c.ready, io.in.c.valid)
node _T_2577 = and(_T_2576, c_first)
when _T_2577 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2>
connect a_set, UInt<2>(0h0)
wire a_set_wo_ready : UInt<2>
connect a_set_wo_ready, UInt<2>(0h0)
wire a_opcodes_set : UInt<8>
connect a_opcodes_set, UInt<8>(0h0)
wire a_sizes_set : UInt<16>
connect a_sizes_set, UInt<16>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2578 = and(io.in.a.valid, a_first_1)
node _T_2579 = and(_T_2578, UInt<1>(0h1))
when _T_2579 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2580 = and(io.in.a.ready, io.in.a.valid)
node _T_2581 = and(_T_2580, a_first_1)
node _T_2582 = and(_T_2581, UInt<1>(0h1))
when _T_2582 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2583 = dshr(inflight, io.in.a.bits.source)
node _T_2584 = bits(_T_2583, 0, 0)
node _T_2585 = eq(_T_2584, UInt<1>(0h0))
node _T_2586 = asUInt(reset)
node _T_2587 = eq(_T_2586, UInt<1>(0h0))
when _T_2587 :
node _T_2588 = eq(_T_2585, UInt<1>(0h0))
when _T_2588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2585, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<2>
connect d_clr, UInt<2>(0h0)
wire d_clr_wo_ready : UInt<2>
connect d_clr_wo_ready, UInt<2>(0h0)
wire d_opcodes_clr : UInt<8>
connect d_opcodes_clr, UInt<8>(0h0)
wire d_sizes_clr : UInt<16>
connect d_sizes_clr, UInt<16>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2589 = and(io.in.d.valid, d_first_1)
node _T_2590 = and(_T_2589, UInt<1>(0h1))
node _T_2591 = eq(d_release_ack, UInt<1>(0h0))
node _T_2592 = and(_T_2590, _T_2591)
when _T_2592 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2593 = and(io.in.d.ready, io.in.d.valid)
node _T_2594 = and(_T_2593, d_first_1)
node _T_2595 = and(_T_2594, UInt<1>(0h1))
node _T_2596 = eq(d_release_ack, UInt<1>(0h0))
node _T_2597 = and(_T_2595, _T_2596)
when _T_2597 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2598 = and(io.in.d.valid, d_first_1)
node _T_2599 = and(_T_2598, UInt<1>(0h1))
node _T_2600 = eq(d_release_ack, UInt<1>(0h0))
node _T_2601 = and(_T_2599, _T_2600)
when _T_2601 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2602 = dshr(inflight, io.in.d.bits.source)
node _T_2603 = bits(_T_2602, 0, 0)
node _T_2604 = or(_T_2603, same_cycle_resp)
node _T_2605 = asUInt(reset)
node _T_2606 = eq(_T_2605, UInt<1>(0h0))
when _T_2606 :
node _T_2607 = eq(_T_2604, UInt<1>(0h0))
when _T_2607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2604, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2608 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2609 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2610 = or(_T_2608, _T_2609)
node _T_2611 = asUInt(reset)
node _T_2612 = eq(_T_2611, UInt<1>(0h0))
when _T_2612 :
node _T_2613 = eq(_T_2610, UInt<1>(0h0))
when _T_2613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2610, UInt<1>(0h1), "") : assert_194
node _T_2614 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2615 = asUInt(reset)
node _T_2616 = eq(_T_2615, UInt<1>(0h0))
when _T_2616 :
node _T_2617 = eq(_T_2614, UInt<1>(0h0))
when _T_2617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2614, UInt<1>(0h1), "") : assert_195
else :
node _T_2618 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2619 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2620 = or(_T_2618, _T_2619)
node _T_2621 = asUInt(reset)
node _T_2622 = eq(_T_2621, UInt<1>(0h0))
when _T_2622 :
node _T_2623 = eq(_T_2620, UInt<1>(0h0))
when _T_2623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2620, UInt<1>(0h1), "") : assert_196
node _T_2624 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2625 = asUInt(reset)
node _T_2626 = eq(_T_2625, UInt<1>(0h0))
when _T_2626 :
node _T_2627 = eq(_T_2624, UInt<1>(0h0))
when _T_2627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2624, UInt<1>(0h1), "") : assert_197
node _T_2628 = and(io.in.d.valid, d_first_1)
node _T_2629 = and(_T_2628, a_first_1)
node _T_2630 = and(_T_2629, io.in.a.valid)
node _T_2631 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2632 = and(_T_2630, _T_2631)
node _T_2633 = eq(d_release_ack, UInt<1>(0h0))
node _T_2634 = and(_T_2632, _T_2633)
when _T_2634 :
node _T_2635 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2636 = or(_T_2635, io.in.a.ready)
node _T_2637 = asUInt(reset)
node _T_2638 = eq(_T_2637, UInt<1>(0h0))
when _T_2638 :
node _T_2639 = eq(_T_2636, UInt<1>(0h0))
when _T_2639 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2636, UInt<1>(0h1), "") : assert_198
node _T_2640 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2641 = orr(a_set_wo_ready)
node _T_2642 = eq(_T_2641, UInt<1>(0h0))
node _T_2643 = or(_T_2640, _T_2642)
node _T_2644 = asUInt(reset)
node _T_2645 = eq(_T_2644, UInt<1>(0h0))
when _T_2645 :
node _T_2646 = eq(_T_2643, UInt<1>(0h0))
when _T_2646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2643, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_4
node _T_2647 = orr(inflight)
node _T_2648 = eq(_T_2647, UInt<1>(0h0))
node _T_2649 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2650 = or(_T_2648, _T_2649)
node _T_2651 = lt(watchdog, plusarg_reader.out)
node _T_2652 = or(_T_2650, _T_2651)
node _T_2653 = asUInt(reset)
node _T_2654 = eq(_T_2653, UInt<1>(0h0))
when _T_2654 :
node _T_2655 = eq(_T_2652, UInt<1>(0h0))
when _T_2655 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2652, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2656 = and(io.in.a.ready, io.in.a.valid)
node _T_2657 = and(io.in.d.ready, io.in.d.valid)
node _T_2658 = or(_T_2656, _T_2657)
when _T_2658 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2>
connect c_set, UInt<2>(0h0)
wire c_set_wo_ready : UInt<2>
connect c_set_wo_ready, UInt<2>(0h0)
wire c_opcodes_set : UInt<8>
connect c_opcodes_set, UInt<8>(0h0)
wire c_sizes_set : UInt<16>
connect c_sizes_set, UInt<16>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2659 = and(io.in.c.valid, c_first_1)
node _T_2660 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2661 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2662 = and(_T_2660, _T_2661)
node _T_2663 = and(_T_2659, _T_2662)
when _T_2663 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2664 = and(io.in.c.ready, io.in.c.valid)
node _T_2665 = and(_T_2664, c_first_1)
node _T_2666 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2667 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2668 = and(_T_2666, _T_2667)
node _T_2669 = and(_T_2665, _T_2668)
when _T_2669 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2670 = dshr(inflight_1, io.in.c.bits.source)
node _T_2671 = bits(_T_2670, 0, 0)
node _T_2672 = eq(_T_2671, UInt<1>(0h0))
node _T_2673 = asUInt(reset)
node _T_2674 = eq(_T_2673, UInt<1>(0h0))
when _T_2674 :
node _T_2675 = eq(_T_2672, UInt<1>(0h0))
when _T_2675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2672, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2>
connect d_clr_1, UInt<2>(0h0)
wire d_clr_wo_ready_1 : UInt<2>
connect d_clr_wo_ready_1, UInt<2>(0h0)
wire d_opcodes_clr_1 : UInt<8>
connect d_opcodes_clr_1, UInt<8>(0h0)
wire d_sizes_clr_1 : UInt<16>
connect d_sizes_clr_1, UInt<16>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2676 = and(io.in.d.valid, d_first_2)
node _T_2677 = and(_T_2676, UInt<1>(0h1))
node _T_2678 = and(_T_2677, d_release_ack_1)
when _T_2678 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2679 = and(io.in.d.ready, io.in.d.valid)
node _T_2680 = and(_T_2679, d_first_2)
node _T_2681 = and(_T_2680, UInt<1>(0h1))
node _T_2682 = and(_T_2681, d_release_ack_1)
when _T_2682 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2683 = and(io.in.d.valid, d_first_2)
node _T_2684 = and(_T_2683, UInt<1>(0h1))
node _T_2685 = and(_T_2684, d_release_ack_1)
when _T_2685 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2686 = dshr(inflight_1, io.in.d.bits.source)
node _T_2687 = bits(_T_2686, 0, 0)
node _T_2688 = or(_T_2687, same_cycle_resp_1)
node _T_2689 = asUInt(reset)
node _T_2690 = eq(_T_2689, UInt<1>(0h0))
when _T_2690 :
node _T_2691 = eq(_T_2688, UInt<1>(0h0))
when _T_2691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2688, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2692 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2693 = asUInt(reset)
node _T_2694 = eq(_T_2693, UInt<1>(0h0))
when _T_2694 :
node _T_2695 = eq(_T_2692, UInt<1>(0h0))
when _T_2695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2692, UInt<1>(0h1), "") : assert_203
else :
node _T_2696 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2697 = asUInt(reset)
node _T_2698 = eq(_T_2697, UInt<1>(0h0))
when _T_2698 :
node _T_2699 = eq(_T_2696, UInt<1>(0h0))
when _T_2699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2696, UInt<1>(0h1), "") : assert_204
node _T_2700 = and(io.in.d.valid, d_first_2)
node _T_2701 = and(_T_2700, c_first_1)
node _T_2702 = and(_T_2701, io.in.c.valid)
node _T_2703 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2704 = and(_T_2702, _T_2703)
node _T_2705 = and(_T_2704, d_release_ack_1)
node _T_2706 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2707 = and(_T_2705, _T_2706)
when _T_2707 :
node _T_2708 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2709 = or(_T_2708, io.in.c.ready)
node _T_2710 = asUInt(reset)
node _T_2711 = eq(_T_2710, UInt<1>(0h0))
when _T_2711 :
node _T_2712 = eq(_T_2709, UInt<1>(0h0))
when _T_2712 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2709, UInt<1>(0h1), "") : assert_205
node _T_2713 = orr(c_set_wo_ready)
when _T_2713 :
node _T_2714 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2715 = asUInt(reset)
node _T_2716 = eq(_T_2715, UInt<1>(0h0))
when _T_2716 :
node _T_2717 = eq(_T_2714, UInt<1>(0h0))
when _T_2717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2714, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_5
node _T_2718 = orr(inflight_1)
node _T_2719 = eq(_T_2718, UInt<1>(0h0))
node _T_2720 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2721 = or(_T_2719, _T_2720)
node _T_2722 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2723 = or(_T_2721, _T_2722)
node _T_2724 = asUInt(reset)
node _T_2725 = eq(_T_2724, UInt<1>(0h0))
when _T_2725 :
node _T_2726 = eq(_T_2723, UInt<1>(0h0))
when _T_2726 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2723, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2727 = and(io.in.c.ready, io.in.c.valid)
node _T_2728 = and(io.in.d.ready, io.in.d.valid)
node _T_2729 = or(_T_2727, _T_2728)
when _T_2729 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2730 = and(io.in.d.ready, io.in.d.valid)
node _T_2731 = and(_T_2730, d_first_3)
node _T_2732 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2733 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2734 = eq(_T_2733, UInt<1>(0h0))
node _T_2735 = and(_T_2732, _T_2734)
node _T_2736 = and(_T_2731, _T_2735)
when _T_2736 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2737 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2738 = bits(_T_2737, 0, 0)
node _T_2739 = eq(_T_2738, UInt<1>(0h0))
node _T_2740 = asUInt(reset)
node _T_2741 = eq(_T_2740, UInt<1>(0h0))
when _T_2741 :
node _T_2742 = eq(_T_2739, UInt<1>(0h0))
when _T_2742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2739, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2743 = and(io.in.e.ready, io.in.e.valid)
node _T_2744 = and(_T_2743, UInt<1>(0h1))
node _T_2745 = and(_T_2744, UInt<1>(0h1))
when _T_2745 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2746 = or(d_set, inflight_2)
node _T_2747 = dshr(_T_2746, io.in.e.bits.sink)
node _T_2748 = bits(_T_2747, 0, 0)
node _T_2749 = asUInt(reset)
node _T_2750 = eq(_T_2749, UInt<1>(0h0))
when _T_2750 :
node _T_2751 = eq(_T_2748, UInt<1>(0h0))
when _T_2751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2748, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_6 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_7 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46]
wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40]
wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46]
wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40]
wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73]
wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_10 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_10; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_10; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [13:0] _GEN_11 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [16:0] _GEN_12 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [17:0] _GEN_13 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46]
wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46]
wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40]
wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46]
wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40]
wire [20:0] _GEN_15 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46]
wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46]
wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40]
wire [25:0] _GEN_16 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46]
wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40]
wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46]
wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40]
wire [27:0] _GEN_18 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_18}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46]
wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40]
wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46]
wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40]
wire [28:0] _GEN_20 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_20}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46]
wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46]
wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40]
wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64]
wire _T_2656 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2656; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2656; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2730 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2730; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2730; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2730; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2730; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_21 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_21; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_21; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_21; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_21; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2727 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2727; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2727; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [15:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] a_set; // @[Monitor.scala:626:34]
wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [15:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_22 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_22; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_22; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_23 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_23; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_23; // @[Monitor.scala:641:65, :791:99]
wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_24 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_25; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2582 = _T_2656 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2582 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2582 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2582 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2582 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_2582 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1:0] d_clr; // @[Monitor.scala:664:34]
wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_26 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_26; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_26; // @[Monitor.scala:673:46, :783:46]
wire _T_2628 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_27 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_28 = 2'h1 << _GEN_27; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_28; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_28; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_28; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_28; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2628 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2597 = _T_2730 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2597 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2597 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2597 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] c_set; // @[Monitor.scala:738:34]
wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [15:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [1:0] _GEN_29 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_30 = 2'h1 << _GEN_29; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_30; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_30; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2669 = _T_2727 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2669 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2669 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2669 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}]
assign c_opcodes_set = _T_2669 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}]
assign c_sizes_set = _T_2669 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [1:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2700 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2700 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire _T_2682 = _T_2730 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2682 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2682 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2682 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2736 = _T_2730 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_31 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_31; // @[OneHot.scala:58:35]
assign d_set = _T_2736 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2745 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_32 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_32; // @[OneHot.scala:58:35]
assign e_clr = _T_2745 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_17 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
when _T_6 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_9 = neq(_T_8, UInt<1>(0h0))
node _T_10 = or(_T_7, _T_9)
node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1)
when _T_13 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_16 = neq(_T_15, UInt<1>(0h0))
node _T_17 = or(_T_14, _T_16)
node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_19 = and(_T_17, _T_18)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1)
when _T_20 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_22 = and(io.pred_wakeup_port.valid, _T_21)
when _T_22 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_23 = eq(io.squash_grant, UInt<1>(0h0))
node _T_24 = and(io.grant, _T_23)
when _T_24 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_25 = and(slot_valid, slot_uop.iw_issued)
when _T_25 :
connect next_valid, rebusied | module IssueSlot_17( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31]
wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31]
wire rebusied = 1'h0; // @[issue-slot.scala:94:32]
wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28]
wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_59 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_513
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_514
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_515
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_516
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_59( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_513 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_514 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_515 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_516 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_37 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_37
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_37( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_37 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_44 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_valid, slot_uop.iw_issued)
when _T_35 :
connect next_valid, rebusied | module IssueSlot_44( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_15 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_15( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25]
wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30]
wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68]
wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9]
wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23]
wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30]
wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_493 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_237
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_493( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_237 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_157 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_157( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AccPipe :
input clock : Clock
input reset : Reset
output io : { flip op1 : { bits : UInt<32>}, flip op2 : { bits : UInt<32>}, sum : { bits : UInt<32>}}
node io_sum_t_rec_rawIn_sign = bits(io.op2.bits, 31, 31)
node io_sum_t_rec_rawIn_expIn = bits(io.op2.bits, 30, 23)
node io_sum_t_rec_rawIn_fractIn = bits(io.op2.bits, 22, 0)
node io_sum_t_rec_rawIn_isZeroExpIn = eq(io_sum_t_rec_rawIn_expIn, UInt<1>(0h0))
node io_sum_t_rec_rawIn_isZeroFractIn = eq(io_sum_t_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_sum_t_rec_rawIn_normDist_T = bits(io_sum_t_rec_rawIn_fractIn, 0, 0)
node _io_sum_t_rec_rawIn_normDist_T_1 = bits(io_sum_t_rec_rawIn_fractIn, 1, 1)
node _io_sum_t_rec_rawIn_normDist_T_2 = bits(io_sum_t_rec_rawIn_fractIn, 2, 2)
node _io_sum_t_rec_rawIn_normDist_T_3 = bits(io_sum_t_rec_rawIn_fractIn, 3, 3)
node _io_sum_t_rec_rawIn_normDist_T_4 = bits(io_sum_t_rec_rawIn_fractIn, 4, 4)
node _io_sum_t_rec_rawIn_normDist_T_5 = bits(io_sum_t_rec_rawIn_fractIn, 5, 5)
node _io_sum_t_rec_rawIn_normDist_T_6 = bits(io_sum_t_rec_rawIn_fractIn, 6, 6)
node _io_sum_t_rec_rawIn_normDist_T_7 = bits(io_sum_t_rec_rawIn_fractIn, 7, 7)
node _io_sum_t_rec_rawIn_normDist_T_8 = bits(io_sum_t_rec_rawIn_fractIn, 8, 8)
node _io_sum_t_rec_rawIn_normDist_T_9 = bits(io_sum_t_rec_rawIn_fractIn, 9, 9)
node _io_sum_t_rec_rawIn_normDist_T_10 = bits(io_sum_t_rec_rawIn_fractIn, 10, 10)
node _io_sum_t_rec_rawIn_normDist_T_11 = bits(io_sum_t_rec_rawIn_fractIn, 11, 11)
node _io_sum_t_rec_rawIn_normDist_T_12 = bits(io_sum_t_rec_rawIn_fractIn, 12, 12)
node _io_sum_t_rec_rawIn_normDist_T_13 = bits(io_sum_t_rec_rawIn_fractIn, 13, 13)
node _io_sum_t_rec_rawIn_normDist_T_14 = bits(io_sum_t_rec_rawIn_fractIn, 14, 14)
node _io_sum_t_rec_rawIn_normDist_T_15 = bits(io_sum_t_rec_rawIn_fractIn, 15, 15)
node _io_sum_t_rec_rawIn_normDist_T_16 = bits(io_sum_t_rec_rawIn_fractIn, 16, 16)
node _io_sum_t_rec_rawIn_normDist_T_17 = bits(io_sum_t_rec_rawIn_fractIn, 17, 17)
node _io_sum_t_rec_rawIn_normDist_T_18 = bits(io_sum_t_rec_rawIn_fractIn, 18, 18)
node _io_sum_t_rec_rawIn_normDist_T_19 = bits(io_sum_t_rec_rawIn_fractIn, 19, 19)
node _io_sum_t_rec_rawIn_normDist_T_20 = bits(io_sum_t_rec_rawIn_fractIn, 20, 20)
node _io_sum_t_rec_rawIn_normDist_T_21 = bits(io_sum_t_rec_rawIn_fractIn, 21, 21)
node _io_sum_t_rec_rawIn_normDist_T_22 = bits(io_sum_t_rec_rawIn_fractIn, 22, 22)
node _io_sum_t_rec_rawIn_normDist_T_23 = mux(_io_sum_t_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_sum_t_rec_rawIn_normDist_T_24 = mux(_io_sum_t_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_sum_t_rec_rawIn_normDist_T_23)
node _io_sum_t_rec_rawIn_normDist_T_25 = mux(_io_sum_t_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_sum_t_rec_rawIn_normDist_T_24)
node _io_sum_t_rec_rawIn_normDist_T_26 = mux(_io_sum_t_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_sum_t_rec_rawIn_normDist_T_25)
node _io_sum_t_rec_rawIn_normDist_T_27 = mux(_io_sum_t_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_sum_t_rec_rawIn_normDist_T_26)
node _io_sum_t_rec_rawIn_normDist_T_28 = mux(_io_sum_t_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_sum_t_rec_rawIn_normDist_T_27)
node _io_sum_t_rec_rawIn_normDist_T_29 = mux(_io_sum_t_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_sum_t_rec_rawIn_normDist_T_28)
node _io_sum_t_rec_rawIn_normDist_T_30 = mux(_io_sum_t_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_sum_t_rec_rawIn_normDist_T_29)
node _io_sum_t_rec_rawIn_normDist_T_31 = mux(_io_sum_t_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_sum_t_rec_rawIn_normDist_T_30)
node _io_sum_t_rec_rawIn_normDist_T_32 = mux(_io_sum_t_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_sum_t_rec_rawIn_normDist_T_31)
node _io_sum_t_rec_rawIn_normDist_T_33 = mux(_io_sum_t_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_sum_t_rec_rawIn_normDist_T_32)
node _io_sum_t_rec_rawIn_normDist_T_34 = mux(_io_sum_t_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_sum_t_rec_rawIn_normDist_T_33)
node _io_sum_t_rec_rawIn_normDist_T_35 = mux(_io_sum_t_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_sum_t_rec_rawIn_normDist_T_34)
node _io_sum_t_rec_rawIn_normDist_T_36 = mux(_io_sum_t_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_sum_t_rec_rawIn_normDist_T_35)
node _io_sum_t_rec_rawIn_normDist_T_37 = mux(_io_sum_t_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_sum_t_rec_rawIn_normDist_T_36)
node _io_sum_t_rec_rawIn_normDist_T_38 = mux(_io_sum_t_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_sum_t_rec_rawIn_normDist_T_37)
node _io_sum_t_rec_rawIn_normDist_T_39 = mux(_io_sum_t_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_sum_t_rec_rawIn_normDist_T_38)
node _io_sum_t_rec_rawIn_normDist_T_40 = mux(_io_sum_t_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_sum_t_rec_rawIn_normDist_T_39)
node _io_sum_t_rec_rawIn_normDist_T_41 = mux(_io_sum_t_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_sum_t_rec_rawIn_normDist_T_40)
node _io_sum_t_rec_rawIn_normDist_T_42 = mux(_io_sum_t_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_sum_t_rec_rawIn_normDist_T_41)
node _io_sum_t_rec_rawIn_normDist_T_43 = mux(_io_sum_t_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_sum_t_rec_rawIn_normDist_T_42)
node io_sum_t_rec_rawIn_normDist = mux(_io_sum_t_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_sum_t_rec_rawIn_normDist_T_43)
node _io_sum_t_rec_rawIn_subnormFract_T = dshl(io_sum_t_rec_rawIn_fractIn, io_sum_t_rec_rawIn_normDist)
node _io_sum_t_rec_rawIn_subnormFract_T_1 = bits(_io_sum_t_rec_rawIn_subnormFract_T, 21, 0)
node io_sum_t_rec_rawIn_subnormFract = shl(_io_sum_t_rec_rawIn_subnormFract_T_1, 1)
node _io_sum_t_rec_rawIn_adjustedExp_T = xor(io_sum_t_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_sum_t_rec_rawIn_adjustedExp_T_1 = mux(io_sum_t_rec_rawIn_isZeroExpIn, _io_sum_t_rec_rawIn_adjustedExp_T, io_sum_t_rec_rawIn_expIn)
node _io_sum_t_rec_rawIn_adjustedExp_T_2 = mux(io_sum_t_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_sum_t_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_sum_t_rec_rawIn_adjustedExp_T_2)
node _io_sum_t_rec_rawIn_adjustedExp_T_4 = add(_io_sum_t_rec_rawIn_adjustedExp_T_1, _io_sum_t_rec_rawIn_adjustedExp_T_3)
node io_sum_t_rec_rawIn_adjustedExp = tail(_io_sum_t_rec_rawIn_adjustedExp_T_4, 1)
node io_sum_t_rec_rawIn_isZero = and(io_sum_t_rec_rawIn_isZeroExpIn, io_sum_t_rec_rawIn_isZeroFractIn)
node _io_sum_t_rec_rawIn_isSpecial_T = bits(io_sum_t_rec_rawIn_adjustedExp, 8, 7)
node io_sum_t_rec_rawIn_isSpecial = eq(_io_sum_t_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_sum_t_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_sum_t_rec_rawIn_out_isNaN_T = eq(io_sum_t_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_sum_t_rec_rawIn_out_isNaN_T_1 = and(io_sum_t_rec_rawIn_isSpecial, _io_sum_t_rec_rawIn_out_isNaN_T)
connect io_sum_t_rec_rawIn.isNaN, _io_sum_t_rec_rawIn_out_isNaN_T_1
node _io_sum_t_rec_rawIn_out_isInf_T = and(io_sum_t_rec_rawIn_isSpecial, io_sum_t_rec_rawIn_isZeroFractIn)
connect io_sum_t_rec_rawIn.isInf, _io_sum_t_rec_rawIn_out_isInf_T
connect io_sum_t_rec_rawIn.isZero, io_sum_t_rec_rawIn_isZero
connect io_sum_t_rec_rawIn.sign, io_sum_t_rec_rawIn_sign
node _io_sum_t_rec_rawIn_out_sExp_T = bits(io_sum_t_rec_rawIn_adjustedExp, 8, 0)
node _io_sum_t_rec_rawIn_out_sExp_T_1 = cvt(_io_sum_t_rec_rawIn_out_sExp_T)
connect io_sum_t_rec_rawIn.sExp, _io_sum_t_rec_rawIn_out_sExp_T_1
node _io_sum_t_rec_rawIn_out_sig_T = eq(io_sum_t_rec_rawIn_isZero, UInt<1>(0h0))
node _io_sum_t_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_sum_t_rec_rawIn_out_sig_T)
node _io_sum_t_rec_rawIn_out_sig_T_2 = mux(io_sum_t_rec_rawIn_isZeroExpIn, io_sum_t_rec_rawIn_subnormFract, io_sum_t_rec_rawIn_fractIn)
node _io_sum_t_rec_rawIn_out_sig_T_3 = cat(_io_sum_t_rec_rawIn_out_sig_T_1, _io_sum_t_rec_rawIn_out_sig_T_2)
connect io_sum_t_rec_rawIn.sig, _io_sum_t_rec_rawIn_out_sig_T_3
node _io_sum_t_rec_T = bits(io_sum_t_rec_rawIn.sExp, 8, 6)
node _io_sum_t_rec_T_1 = mux(io_sum_t_rec_rawIn.isZero, UInt<3>(0h0), _io_sum_t_rec_T)
node _io_sum_t_rec_T_2 = mux(io_sum_t_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_sum_t_rec_T_3 = or(_io_sum_t_rec_T_1, _io_sum_t_rec_T_2)
node _io_sum_t_rec_T_4 = cat(io_sum_t_rec_rawIn.sign, _io_sum_t_rec_T_3)
node _io_sum_t_rec_T_5 = bits(io_sum_t_rec_rawIn.sExp, 5, 0)
node _io_sum_t_rec_T_6 = cat(_io_sum_t_rec_T_4, _io_sum_t_rec_T_5)
node _io_sum_t_rec_T_7 = bits(io_sum_t_rec_rawIn.sig, 22, 0)
node io_sum_t_rec = cat(_io_sum_t_rec_T_6, _io_sum_t_rec_T_7)
node io_sum_self_rec_rawIn_sign = bits(io.op1.bits, 31, 31)
node io_sum_self_rec_rawIn_expIn = bits(io.op1.bits, 30, 23)
node io_sum_self_rec_rawIn_fractIn = bits(io.op1.bits, 22, 0)
node io_sum_self_rec_rawIn_isZeroExpIn = eq(io_sum_self_rec_rawIn_expIn, UInt<1>(0h0))
node io_sum_self_rec_rawIn_isZeroFractIn = eq(io_sum_self_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_sum_self_rec_rawIn_normDist_T = bits(io_sum_self_rec_rawIn_fractIn, 0, 0)
node _io_sum_self_rec_rawIn_normDist_T_1 = bits(io_sum_self_rec_rawIn_fractIn, 1, 1)
node _io_sum_self_rec_rawIn_normDist_T_2 = bits(io_sum_self_rec_rawIn_fractIn, 2, 2)
node _io_sum_self_rec_rawIn_normDist_T_3 = bits(io_sum_self_rec_rawIn_fractIn, 3, 3)
node _io_sum_self_rec_rawIn_normDist_T_4 = bits(io_sum_self_rec_rawIn_fractIn, 4, 4)
node _io_sum_self_rec_rawIn_normDist_T_5 = bits(io_sum_self_rec_rawIn_fractIn, 5, 5)
node _io_sum_self_rec_rawIn_normDist_T_6 = bits(io_sum_self_rec_rawIn_fractIn, 6, 6)
node _io_sum_self_rec_rawIn_normDist_T_7 = bits(io_sum_self_rec_rawIn_fractIn, 7, 7)
node _io_sum_self_rec_rawIn_normDist_T_8 = bits(io_sum_self_rec_rawIn_fractIn, 8, 8)
node _io_sum_self_rec_rawIn_normDist_T_9 = bits(io_sum_self_rec_rawIn_fractIn, 9, 9)
node _io_sum_self_rec_rawIn_normDist_T_10 = bits(io_sum_self_rec_rawIn_fractIn, 10, 10)
node _io_sum_self_rec_rawIn_normDist_T_11 = bits(io_sum_self_rec_rawIn_fractIn, 11, 11)
node _io_sum_self_rec_rawIn_normDist_T_12 = bits(io_sum_self_rec_rawIn_fractIn, 12, 12)
node _io_sum_self_rec_rawIn_normDist_T_13 = bits(io_sum_self_rec_rawIn_fractIn, 13, 13)
node _io_sum_self_rec_rawIn_normDist_T_14 = bits(io_sum_self_rec_rawIn_fractIn, 14, 14)
node _io_sum_self_rec_rawIn_normDist_T_15 = bits(io_sum_self_rec_rawIn_fractIn, 15, 15)
node _io_sum_self_rec_rawIn_normDist_T_16 = bits(io_sum_self_rec_rawIn_fractIn, 16, 16)
node _io_sum_self_rec_rawIn_normDist_T_17 = bits(io_sum_self_rec_rawIn_fractIn, 17, 17)
node _io_sum_self_rec_rawIn_normDist_T_18 = bits(io_sum_self_rec_rawIn_fractIn, 18, 18)
node _io_sum_self_rec_rawIn_normDist_T_19 = bits(io_sum_self_rec_rawIn_fractIn, 19, 19)
node _io_sum_self_rec_rawIn_normDist_T_20 = bits(io_sum_self_rec_rawIn_fractIn, 20, 20)
node _io_sum_self_rec_rawIn_normDist_T_21 = bits(io_sum_self_rec_rawIn_fractIn, 21, 21)
node _io_sum_self_rec_rawIn_normDist_T_22 = bits(io_sum_self_rec_rawIn_fractIn, 22, 22)
node _io_sum_self_rec_rawIn_normDist_T_23 = mux(_io_sum_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_sum_self_rec_rawIn_normDist_T_24 = mux(_io_sum_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_sum_self_rec_rawIn_normDist_T_23)
node _io_sum_self_rec_rawIn_normDist_T_25 = mux(_io_sum_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_sum_self_rec_rawIn_normDist_T_24)
node _io_sum_self_rec_rawIn_normDist_T_26 = mux(_io_sum_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_sum_self_rec_rawIn_normDist_T_25)
node _io_sum_self_rec_rawIn_normDist_T_27 = mux(_io_sum_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_sum_self_rec_rawIn_normDist_T_26)
node _io_sum_self_rec_rawIn_normDist_T_28 = mux(_io_sum_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_sum_self_rec_rawIn_normDist_T_27)
node _io_sum_self_rec_rawIn_normDist_T_29 = mux(_io_sum_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_sum_self_rec_rawIn_normDist_T_28)
node _io_sum_self_rec_rawIn_normDist_T_30 = mux(_io_sum_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_sum_self_rec_rawIn_normDist_T_29)
node _io_sum_self_rec_rawIn_normDist_T_31 = mux(_io_sum_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_sum_self_rec_rawIn_normDist_T_30)
node _io_sum_self_rec_rawIn_normDist_T_32 = mux(_io_sum_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_sum_self_rec_rawIn_normDist_T_31)
node _io_sum_self_rec_rawIn_normDist_T_33 = mux(_io_sum_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_sum_self_rec_rawIn_normDist_T_32)
node _io_sum_self_rec_rawIn_normDist_T_34 = mux(_io_sum_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_sum_self_rec_rawIn_normDist_T_33)
node _io_sum_self_rec_rawIn_normDist_T_35 = mux(_io_sum_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_sum_self_rec_rawIn_normDist_T_34)
node _io_sum_self_rec_rawIn_normDist_T_36 = mux(_io_sum_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_sum_self_rec_rawIn_normDist_T_35)
node _io_sum_self_rec_rawIn_normDist_T_37 = mux(_io_sum_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_sum_self_rec_rawIn_normDist_T_36)
node _io_sum_self_rec_rawIn_normDist_T_38 = mux(_io_sum_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_sum_self_rec_rawIn_normDist_T_37)
node _io_sum_self_rec_rawIn_normDist_T_39 = mux(_io_sum_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_sum_self_rec_rawIn_normDist_T_38)
node _io_sum_self_rec_rawIn_normDist_T_40 = mux(_io_sum_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_sum_self_rec_rawIn_normDist_T_39)
node _io_sum_self_rec_rawIn_normDist_T_41 = mux(_io_sum_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_sum_self_rec_rawIn_normDist_T_40)
node _io_sum_self_rec_rawIn_normDist_T_42 = mux(_io_sum_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_sum_self_rec_rawIn_normDist_T_41)
node _io_sum_self_rec_rawIn_normDist_T_43 = mux(_io_sum_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_sum_self_rec_rawIn_normDist_T_42)
node io_sum_self_rec_rawIn_normDist = mux(_io_sum_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_sum_self_rec_rawIn_normDist_T_43)
node _io_sum_self_rec_rawIn_subnormFract_T = dshl(io_sum_self_rec_rawIn_fractIn, io_sum_self_rec_rawIn_normDist)
node _io_sum_self_rec_rawIn_subnormFract_T_1 = bits(_io_sum_self_rec_rawIn_subnormFract_T, 21, 0)
node io_sum_self_rec_rawIn_subnormFract = shl(_io_sum_self_rec_rawIn_subnormFract_T_1, 1)
node _io_sum_self_rec_rawIn_adjustedExp_T = xor(io_sum_self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_sum_self_rec_rawIn_adjustedExp_T_1 = mux(io_sum_self_rec_rawIn_isZeroExpIn, _io_sum_self_rec_rawIn_adjustedExp_T, io_sum_self_rec_rawIn_expIn)
node _io_sum_self_rec_rawIn_adjustedExp_T_2 = mux(io_sum_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_sum_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_sum_self_rec_rawIn_adjustedExp_T_2)
node _io_sum_self_rec_rawIn_adjustedExp_T_4 = add(_io_sum_self_rec_rawIn_adjustedExp_T_1, _io_sum_self_rec_rawIn_adjustedExp_T_3)
node io_sum_self_rec_rawIn_adjustedExp = tail(_io_sum_self_rec_rawIn_adjustedExp_T_4, 1)
node io_sum_self_rec_rawIn_isZero = and(io_sum_self_rec_rawIn_isZeroExpIn, io_sum_self_rec_rawIn_isZeroFractIn)
node _io_sum_self_rec_rawIn_isSpecial_T = bits(io_sum_self_rec_rawIn_adjustedExp, 8, 7)
node io_sum_self_rec_rawIn_isSpecial = eq(_io_sum_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_sum_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_sum_self_rec_rawIn_out_isNaN_T = eq(io_sum_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_sum_self_rec_rawIn_out_isNaN_T_1 = and(io_sum_self_rec_rawIn_isSpecial, _io_sum_self_rec_rawIn_out_isNaN_T)
connect io_sum_self_rec_rawIn.isNaN, _io_sum_self_rec_rawIn_out_isNaN_T_1
node _io_sum_self_rec_rawIn_out_isInf_T = and(io_sum_self_rec_rawIn_isSpecial, io_sum_self_rec_rawIn_isZeroFractIn)
connect io_sum_self_rec_rawIn.isInf, _io_sum_self_rec_rawIn_out_isInf_T
connect io_sum_self_rec_rawIn.isZero, io_sum_self_rec_rawIn_isZero
connect io_sum_self_rec_rawIn.sign, io_sum_self_rec_rawIn_sign
node _io_sum_self_rec_rawIn_out_sExp_T = bits(io_sum_self_rec_rawIn_adjustedExp, 8, 0)
node _io_sum_self_rec_rawIn_out_sExp_T_1 = cvt(_io_sum_self_rec_rawIn_out_sExp_T)
connect io_sum_self_rec_rawIn.sExp, _io_sum_self_rec_rawIn_out_sExp_T_1
node _io_sum_self_rec_rawIn_out_sig_T = eq(io_sum_self_rec_rawIn_isZero, UInt<1>(0h0))
node _io_sum_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_sum_self_rec_rawIn_out_sig_T)
node _io_sum_self_rec_rawIn_out_sig_T_2 = mux(io_sum_self_rec_rawIn_isZeroExpIn, io_sum_self_rec_rawIn_subnormFract, io_sum_self_rec_rawIn_fractIn)
node _io_sum_self_rec_rawIn_out_sig_T_3 = cat(_io_sum_self_rec_rawIn_out_sig_T_1, _io_sum_self_rec_rawIn_out_sig_T_2)
connect io_sum_self_rec_rawIn.sig, _io_sum_self_rec_rawIn_out_sig_T_3
node _io_sum_self_rec_T = bits(io_sum_self_rec_rawIn.sExp, 8, 6)
node _io_sum_self_rec_T_1 = mux(io_sum_self_rec_rawIn.isZero, UInt<3>(0h0), _io_sum_self_rec_T)
node _io_sum_self_rec_T_2 = mux(io_sum_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_sum_self_rec_T_3 = or(_io_sum_self_rec_T_1, _io_sum_self_rec_T_2)
node _io_sum_self_rec_T_4 = cat(io_sum_self_rec_rawIn.sign, _io_sum_self_rec_T_3)
node _io_sum_self_rec_T_5 = bits(io_sum_self_rec_rawIn.sExp, 5, 0)
node _io_sum_self_rec_T_6 = cat(_io_sum_self_rec_T_4, _io_sum_self_rec_T_5)
node _io_sum_self_rec_T_7 = bits(io_sum_self_rec_rawIn.sig, 22, 0)
node io_sum_self_rec = cat(_io_sum_self_rec_T_6, _io_sum_self_rec_T_7)
inst io_sum_in_to_rec_fn of INToRecFN_i1_e8_s24_48
connect io_sum_in_to_rec_fn.io.signedIn, UInt<1>(0h0)
connect io_sum_in_to_rec_fn.io.in, UInt<1>(0h1)
connect io_sum_in_to_rec_fn.io.roundingMode, UInt<3>(0h0)
connect io_sum_in_to_rec_fn.io.detectTininess, UInt<1>(0h1)
inst io_sum_t_resizer of RecFNToRecFN_136
connect io_sum_t_resizer.io.in, io_sum_t_rec
connect io_sum_t_resizer.io.roundingMode, UInt<3>(0h0)
connect io_sum_t_resizer.io.detectTininess, UInt<1>(0h1)
inst io_sum_muladder of MulAddRecFN_e8_s24_60
connect io_sum_muladder.io.op, UInt<1>(0h0)
connect io_sum_muladder.io.roundingMode, UInt<3>(0h0)
connect io_sum_muladder.io.detectTininess, UInt<1>(0h1)
connect io_sum_muladder.io.a, io_sum_t_resizer.io.out
connect io_sum_muladder.io.b, io_sum_in_to_rec_fn.io.out
connect io_sum_muladder.io.c, io_sum_self_rec
wire io_sum_result : { bits : UInt<32>}
node io_sum_result_bits_rawIn_exp = bits(io_sum_muladder.io.out, 31, 23)
node _io_sum_result_bits_rawIn_isZero_T = bits(io_sum_result_bits_rawIn_exp, 8, 6)
node io_sum_result_bits_rawIn_isZero = eq(_io_sum_result_bits_rawIn_isZero_T, UInt<1>(0h0))
node _io_sum_result_bits_rawIn_isSpecial_T = bits(io_sum_result_bits_rawIn_exp, 8, 7)
node io_sum_result_bits_rawIn_isSpecial = eq(_io_sum_result_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_sum_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_sum_result_bits_rawIn_out_isNaN_T = bits(io_sum_result_bits_rawIn_exp, 6, 6)
node _io_sum_result_bits_rawIn_out_isNaN_T_1 = and(io_sum_result_bits_rawIn_isSpecial, _io_sum_result_bits_rawIn_out_isNaN_T)
connect io_sum_result_bits_rawIn.isNaN, _io_sum_result_bits_rawIn_out_isNaN_T_1
node _io_sum_result_bits_rawIn_out_isInf_T = bits(io_sum_result_bits_rawIn_exp, 6, 6)
node _io_sum_result_bits_rawIn_out_isInf_T_1 = eq(_io_sum_result_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_sum_result_bits_rawIn_out_isInf_T_2 = and(io_sum_result_bits_rawIn_isSpecial, _io_sum_result_bits_rawIn_out_isInf_T_1)
connect io_sum_result_bits_rawIn.isInf, _io_sum_result_bits_rawIn_out_isInf_T_2
connect io_sum_result_bits_rawIn.isZero, io_sum_result_bits_rawIn_isZero
node _io_sum_result_bits_rawIn_out_sign_T = bits(io_sum_muladder.io.out, 32, 32)
connect io_sum_result_bits_rawIn.sign, _io_sum_result_bits_rawIn_out_sign_T
node _io_sum_result_bits_rawIn_out_sExp_T = cvt(io_sum_result_bits_rawIn_exp)
connect io_sum_result_bits_rawIn.sExp, _io_sum_result_bits_rawIn_out_sExp_T
node _io_sum_result_bits_rawIn_out_sig_T = eq(io_sum_result_bits_rawIn_isZero, UInt<1>(0h0))
node _io_sum_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_sum_result_bits_rawIn_out_sig_T)
node _io_sum_result_bits_rawIn_out_sig_T_2 = bits(io_sum_muladder.io.out, 22, 0)
node _io_sum_result_bits_rawIn_out_sig_T_3 = cat(_io_sum_result_bits_rawIn_out_sig_T_1, _io_sum_result_bits_rawIn_out_sig_T_2)
connect io_sum_result_bits_rawIn.sig, _io_sum_result_bits_rawIn_out_sig_T_3
node io_sum_result_bits_isSubnormal = lt(io_sum_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _io_sum_result_bits_denormShiftDist_T = bits(io_sum_result_bits_rawIn.sExp, 4, 0)
node _io_sum_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_sum_result_bits_denormShiftDist_T)
node io_sum_result_bits_denormShiftDist = tail(_io_sum_result_bits_denormShiftDist_T_1, 1)
node _io_sum_result_bits_denormFract_T = shr(io_sum_result_bits_rawIn.sig, 1)
node _io_sum_result_bits_denormFract_T_1 = dshr(_io_sum_result_bits_denormFract_T, io_sum_result_bits_denormShiftDist)
node io_sum_result_bits_denormFract = bits(_io_sum_result_bits_denormFract_T_1, 22, 0)
node _io_sum_result_bits_expOut_T = bits(io_sum_result_bits_rawIn.sExp, 7, 0)
node _io_sum_result_bits_expOut_T_1 = sub(_io_sum_result_bits_expOut_T, UInt<8>(0h81))
node _io_sum_result_bits_expOut_T_2 = tail(_io_sum_result_bits_expOut_T_1, 1)
node _io_sum_result_bits_expOut_T_3 = mux(io_sum_result_bits_isSubnormal, UInt<1>(0h0), _io_sum_result_bits_expOut_T_2)
node _io_sum_result_bits_expOut_T_4 = or(io_sum_result_bits_rawIn.isNaN, io_sum_result_bits_rawIn.isInf)
node _io_sum_result_bits_expOut_T_5 = mux(_io_sum_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node io_sum_result_bits_expOut = or(_io_sum_result_bits_expOut_T_3, _io_sum_result_bits_expOut_T_5)
node _io_sum_result_bits_fractOut_T = bits(io_sum_result_bits_rawIn.sig, 22, 0)
node _io_sum_result_bits_fractOut_T_1 = mux(io_sum_result_bits_rawIn.isInf, UInt<1>(0h0), _io_sum_result_bits_fractOut_T)
node io_sum_result_bits_fractOut = mux(io_sum_result_bits_isSubnormal, io_sum_result_bits_denormFract, _io_sum_result_bits_fractOut_T_1)
node io_sum_result_bits_hi = cat(io_sum_result_bits_rawIn.sign, io_sum_result_bits_expOut)
node _io_sum_result_bits_T = cat(io_sum_result_bits_hi, io_sum_result_bits_fractOut)
connect io_sum_result.bits, _io_sum_result_bits_T
reg io_sum_r : { bits : UInt<32>}, clock
when UInt<1>(0h1) :
connect io_sum_r, io_sum_result
connect io.sum, io_sum_r | module AccPipe( // @[AccumulatorMem.scala:63:7]
input clock, // @[AccumulatorMem.scala:63:7]
input reset, // @[AccumulatorMem.scala:63:7]
input [31:0] io_op1_bits, // @[AccumulatorMem.scala:64:14]
input [31:0] io_op2_bits, // @[AccumulatorMem.scala:64:14]
output [31:0] io_sum_bits // @[AccumulatorMem.scala:64:14]
);
wire io_sum_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_sum_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _io_sum_muladder_io_out; // @[Arithmetic.scala:416:30]
wire [32:0] _io_sum_t_resizer_io_out; // @[Arithmetic.scala:409:31]
wire [31:0] io_op1_bits_0 = io_op1_bits; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_op2_bits_0 = io_op2_bits; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_sum_bits_0; // @[AccumulatorMem.scala:63:7]
wire io_sum_t_rec_rawIn_sign = io_op2_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_sum_t_rec_rawIn_sign_0 = io_sum_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_sum_t_rec_rawIn_expIn = io_op2_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_sum_t_rec_rawIn_fractIn = io_op2_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_sum_t_rec_rawIn_isZeroExpIn = io_sum_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_sum_t_rec_rawIn_isZeroFractIn = io_sum_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_sum_t_rec_rawIn_normDist_T = io_sum_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_1 = io_sum_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_2 = io_sum_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_3 = io_sum_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_4 = io_sum_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_5 = io_sum_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_6 = io_sum_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_7 = io_sum_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_8 = io_sum_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_9 = io_sum_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_10 = io_sum_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_11 = io_sum_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_12 = io_sum_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_13 = io_sum_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_14 = io_sum_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_15 = io_sum_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_16 = io_sum_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_17 = io_sum_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_18 = io_sum_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_19 = io_sum_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_20 = io_sum_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_21 = io_sum_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_t_rec_rawIn_normDist_T_22 = io_sum_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_23 = _io_sum_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_24 = _io_sum_t_rec_rawIn_normDist_T_2 ? 5'h14 : _io_sum_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_25 = _io_sum_t_rec_rawIn_normDist_T_3 ? 5'h13 : _io_sum_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_26 = _io_sum_t_rec_rawIn_normDist_T_4 ? 5'h12 : _io_sum_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_27 = _io_sum_t_rec_rawIn_normDist_T_5 ? 5'h11 : _io_sum_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_28 = _io_sum_t_rec_rawIn_normDist_T_6 ? 5'h10 : _io_sum_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_29 = _io_sum_t_rec_rawIn_normDist_T_7 ? 5'hF : _io_sum_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_30 = _io_sum_t_rec_rawIn_normDist_T_8 ? 5'hE : _io_sum_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_31 = _io_sum_t_rec_rawIn_normDist_T_9 ? 5'hD : _io_sum_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_32 = _io_sum_t_rec_rawIn_normDist_T_10 ? 5'hC : _io_sum_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_33 = _io_sum_t_rec_rawIn_normDist_T_11 ? 5'hB : _io_sum_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_34 = _io_sum_t_rec_rawIn_normDist_T_12 ? 5'hA : _io_sum_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_35 = _io_sum_t_rec_rawIn_normDist_T_13 ? 5'h9 : _io_sum_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_36 = _io_sum_t_rec_rawIn_normDist_T_14 ? 5'h8 : _io_sum_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_37 = _io_sum_t_rec_rawIn_normDist_T_15 ? 5'h7 : _io_sum_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_38 = _io_sum_t_rec_rawIn_normDist_T_16 ? 5'h6 : _io_sum_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_39 = _io_sum_t_rec_rawIn_normDist_T_17 ? 5'h5 : _io_sum_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_40 = _io_sum_t_rec_rawIn_normDist_T_18 ? 5'h4 : _io_sum_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_41 = _io_sum_t_rec_rawIn_normDist_T_19 ? 5'h3 : _io_sum_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_42 = _io_sum_t_rec_rawIn_normDist_T_20 ? 5'h2 : _io_sum_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_sum_t_rec_rawIn_normDist_T_43 = _io_sum_t_rec_rawIn_normDist_T_21 ? 5'h1 : _io_sum_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_sum_t_rec_rawIn_normDist = _io_sum_t_rec_rawIn_normDist_T_22 ? 5'h0 : _io_sum_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_sum_t_rec_rawIn_subnormFract_T = {31'h0, io_sum_t_rec_rawIn_fractIn} << io_sum_t_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_sum_t_rec_rawIn_subnormFract_T_1 = _io_sum_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_sum_t_rec_rawIn_subnormFract = {_io_sum_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_sum_t_rec_rawIn_adjustedExp_T = {4'hF, ~io_sum_t_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_sum_t_rec_rawIn_adjustedExp_T_1 = io_sum_t_rec_rawIn_isZeroExpIn ? _io_sum_t_rec_rawIn_adjustedExp_T : {1'h0, io_sum_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_sum_t_rec_rawIn_adjustedExp_T_2 = io_sum_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_sum_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_sum_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_sum_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_sum_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_sum_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_sum_t_rec_rawIn_adjustedExp = _io_sum_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_sum_t_rec_rawIn_out_sExp_T = io_sum_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_sum_t_rec_rawIn_isZero = io_sum_t_rec_rawIn_isZeroExpIn & io_sum_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_sum_t_rec_rawIn_isZero_0 = io_sum_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_sum_t_rec_rawIn_isSpecial_T = io_sum_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_sum_t_rec_rawIn_isSpecial = &_io_sum_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_sum_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_sum_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_sum_t_rec_T_2 = io_sum_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_sum_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_sum_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_sum_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_sum_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_sum_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_sum_t_rec_rawIn_out_isNaN_T = ~io_sum_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_sum_t_rec_rawIn_out_isNaN_T_1 = io_sum_t_rec_rawIn_isSpecial & _io_sum_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_sum_t_rec_rawIn_isNaN = _io_sum_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_sum_t_rec_rawIn_out_isInf_T = io_sum_t_rec_rawIn_isSpecial & io_sum_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_sum_t_rec_rawIn_isInf = _io_sum_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_sum_t_rec_rawIn_out_sExp_T_1 = {1'h0, _io_sum_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_sum_t_rec_rawIn_sExp = _io_sum_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_sum_t_rec_rawIn_out_sig_T = ~io_sum_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_sum_t_rec_rawIn_out_sig_T_1 = {1'h0, _io_sum_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_sum_t_rec_rawIn_out_sig_T_2 = io_sum_t_rec_rawIn_isZeroExpIn ? io_sum_t_rec_rawIn_subnormFract : io_sum_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_sum_t_rec_rawIn_out_sig_T_3 = {_io_sum_t_rec_rawIn_out_sig_T_1, _io_sum_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_sum_t_rec_rawIn_sig = _io_sum_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_sum_t_rec_T = io_sum_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_sum_t_rec_T_1 = io_sum_t_rec_rawIn_isZero_0 ? 3'h0 : _io_sum_t_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_sum_t_rec_T_3 = {_io_sum_t_rec_T_1[2:1], _io_sum_t_rec_T_1[0] | _io_sum_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_sum_t_rec_T_4 = {io_sum_t_rec_rawIn_sign_0, _io_sum_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_sum_t_rec_T_5 = io_sum_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_sum_t_rec_T_6 = {_io_sum_t_rec_T_4, _io_sum_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_sum_t_rec_T_7 = io_sum_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_sum_t_rec = {_io_sum_t_rec_T_6, _io_sum_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_sum_self_rec_rawIn_sign = io_op1_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_sum_self_rec_rawIn_sign_0 = io_sum_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_sum_self_rec_rawIn_expIn = io_op1_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_sum_self_rec_rawIn_fractIn = io_op1_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_sum_self_rec_rawIn_isZeroExpIn = io_sum_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_sum_self_rec_rawIn_isZeroFractIn = io_sum_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_sum_self_rec_rawIn_normDist_T = io_sum_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_1 = io_sum_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_2 = io_sum_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_3 = io_sum_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_4 = io_sum_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_5 = io_sum_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_6 = io_sum_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_7 = io_sum_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_8 = io_sum_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_9 = io_sum_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_10 = io_sum_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_11 = io_sum_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_12 = io_sum_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_13 = io_sum_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_14 = io_sum_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_15 = io_sum_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_16 = io_sum_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_17 = io_sum_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_18 = io_sum_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_19 = io_sum_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_20 = io_sum_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_21 = io_sum_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_sum_self_rec_rawIn_normDist_T_22 = io_sum_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_23 = _io_sum_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_24 = _io_sum_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_sum_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_25 = _io_sum_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_sum_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_26 = _io_sum_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_sum_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_27 = _io_sum_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_sum_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_28 = _io_sum_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_sum_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_29 = _io_sum_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_sum_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_30 = _io_sum_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_sum_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_31 = _io_sum_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_sum_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_32 = _io_sum_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_sum_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_33 = _io_sum_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_sum_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_34 = _io_sum_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_sum_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_35 = _io_sum_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_sum_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_36 = _io_sum_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_sum_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_37 = _io_sum_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_sum_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_38 = _io_sum_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_sum_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_39 = _io_sum_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_sum_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_40 = _io_sum_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_sum_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_41 = _io_sum_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_sum_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_42 = _io_sum_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_sum_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_sum_self_rec_rawIn_normDist_T_43 = _io_sum_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_sum_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_sum_self_rec_rawIn_normDist = _io_sum_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_sum_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_sum_self_rec_rawIn_subnormFract_T = {31'h0, io_sum_self_rec_rawIn_fractIn} << io_sum_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_sum_self_rec_rawIn_subnormFract_T_1 = _io_sum_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_sum_self_rec_rawIn_subnormFract = {_io_sum_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_sum_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_sum_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_sum_self_rec_rawIn_adjustedExp_T_1 = io_sum_self_rec_rawIn_isZeroExpIn ? _io_sum_self_rec_rawIn_adjustedExp_T : {1'h0, io_sum_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_sum_self_rec_rawIn_adjustedExp_T_2 = io_sum_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_sum_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_sum_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_sum_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_sum_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_sum_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_sum_self_rec_rawIn_adjustedExp = _io_sum_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_sum_self_rec_rawIn_out_sExp_T = io_sum_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_sum_self_rec_rawIn_isZero = io_sum_self_rec_rawIn_isZeroExpIn & io_sum_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_sum_self_rec_rawIn_isZero_0 = io_sum_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_sum_self_rec_rawIn_isSpecial_T = io_sum_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_sum_self_rec_rawIn_isSpecial = &_io_sum_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_sum_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_sum_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_sum_self_rec_T_2 = io_sum_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_sum_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_sum_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_sum_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_sum_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_sum_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_sum_self_rec_rawIn_out_isNaN_T = ~io_sum_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_sum_self_rec_rawIn_out_isNaN_T_1 = io_sum_self_rec_rawIn_isSpecial & _io_sum_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_sum_self_rec_rawIn_isNaN = _io_sum_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_sum_self_rec_rawIn_out_isInf_T = io_sum_self_rec_rawIn_isSpecial & io_sum_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_sum_self_rec_rawIn_isInf = _io_sum_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_sum_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_sum_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_sum_self_rec_rawIn_sExp = _io_sum_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_sum_self_rec_rawIn_out_sig_T = ~io_sum_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_sum_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_sum_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_sum_self_rec_rawIn_out_sig_T_2 = io_sum_self_rec_rawIn_isZeroExpIn ? io_sum_self_rec_rawIn_subnormFract : io_sum_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_sum_self_rec_rawIn_out_sig_T_3 = {_io_sum_self_rec_rawIn_out_sig_T_1, _io_sum_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_sum_self_rec_rawIn_sig = _io_sum_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_sum_self_rec_T = io_sum_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_sum_self_rec_T_1 = io_sum_self_rec_rawIn_isZero_0 ? 3'h0 : _io_sum_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_sum_self_rec_T_3 = {_io_sum_self_rec_T_1[2:1], _io_sum_self_rec_T_1[0] | _io_sum_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_sum_self_rec_T_4 = {io_sum_self_rec_rawIn_sign_0, _io_sum_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_sum_self_rec_T_5 = io_sum_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_sum_self_rec_T_6 = {_io_sum_self_rec_T_4, _io_sum_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_sum_self_rec_T_7 = io_sum_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_sum_self_rec = {_io_sum_self_rec_T_6, _io_sum_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_sum_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] io_sum_result_bits; // @[Arithmetic.scala:426:26]
wire [8:0] io_sum_result_bits_rawIn_exp = _io_sum_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_sum_result_bits_rawIn_isZero_T = io_sum_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_sum_result_bits_rawIn_isZero = _io_sum_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_sum_result_bits_rawIn_isZero_0 = io_sum_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_sum_result_bits_rawIn_isSpecial_T = io_sum_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_sum_result_bits_rawIn_isSpecial = &_io_sum_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_sum_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_sum_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_sum_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_sum_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_sum_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_sum_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_sum_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_sum_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_sum_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_sum_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_sum_result_bits_rawIn_out_isNaN_T = io_sum_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_sum_result_bits_rawIn_out_isInf_T = io_sum_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_sum_result_bits_rawIn_out_isNaN_T_1 = io_sum_result_bits_rawIn_isSpecial & _io_sum_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_sum_result_bits_rawIn_isNaN = _io_sum_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_sum_result_bits_rawIn_out_isInf_T_1 = ~_io_sum_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_sum_result_bits_rawIn_out_isInf_T_2 = io_sum_result_bits_rawIn_isSpecial & _io_sum_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_sum_result_bits_rawIn_isInf = _io_sum_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_sum_result_bits_rawIn_out_sign_T = _io_sum_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_sum_result_bits_rawIn_sign = _io_sum_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_sum_result_bits_rawIn_out_sExp_T = {1'h0, io_sum_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_sum_result_bits_rawIn_sExp = _io_sum_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_sum_result_bits_rawIn_out_sig_T = ~io_sum_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_sum_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_sum_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_sum_result_bits_rawIn_out_sig_T_2 = _io_sum_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_sum_result_bits_rawIn_out_sig_T_3 = {_io_sum_result_bits_rawIn_out_sig_T_1, _io_sum_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_sum_result_bits_rawIn_sig = _io_sum_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_sum_result_bits_isSubnormal = $signed(io_sum_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_sum_result_bits_denormShiftDist_T = io_sum_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_sum_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_sum_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_sum_result_bits_denormShiftDist = _io_sum_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_sum_result_bits_denormFract_T = io_sum_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_sum_result_bits_denormFract_T_1 = _io_sum_result_bits_denormFract_T >> io_sum_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_sum_result_bits_denormFract = _io_sum_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_sum_result_bits_expOut_T = io_sum_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_sum_result_bits_expOut_T_1 = {1'h0, _io_sum_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_sum_result_bits_expOut_T_2 = _io_sum_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_sum_result_bits_expOut_T_3 = io_sum_result_bits_isSubnormal ? 8'h0 : _io_sum_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_sum_result_bits_expOut_T_4 = io_sum_result_bits_rawIn_isNaN | io_sum_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_sum_result_bits_expOut_T_5 = {8{_io_sum_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_sum_result_bits_expOut = _io_sum_result_bits_expOut_T_3 | _io_sum_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_sum_result_bits_fractOut_T = io_sum_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_sum_result_bits_fractOut_T_1 = io_sum_result_bits_rawIn_isInf ? 23'h0 : _io_sum_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_sum_result_bits_fractOut = io_sum_result_bits_isSubnormal ? io_sum_result_bits_denormFract : _io_sum_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_sum_result_bits_hi = {io_sum_result_bits_rawIn_sign, io_sum_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_sum_result_bits_T = {io_sum_result_bits_hi, io_sum_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_sum_result_bits = _io_sum_result_bits_T; // @[fNFromRecFN.scala:66:12]
reg [31:0] io_sum_r_bits; // @[AccumulatorMem.scala:70:26]
assign io_sum_bits_0 = io_sum_r_bits; // @[AccumulatorMem.scala:63:7, :70:26]
always @(posedge clock) // @[AccumulatorMem.scala:63:7]
io_sum_r_bits <= io_sum_result_bits; // @[Arithmetic.scala:426:26]
INToRecFN_i1_e8_s24_48 io_sum_in_to_rec_fn (); // @[Arithmetic.scala:400:34]
RecFNToRecFN_136 io_sum_t_resizer ( // @[Arithmetic.scala:409:31]
.io_in (io_sum_t_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_sum_t_resizer_io_out)
); // @[Arithmetic.scala:409:31]
MulAddRecFN_e8_s24_60 io_sum_muladder ( // @[Arithmetic.scala:416:30]
.io_a (_io_sum_t_resizer_io_out), // @[Arithmetic.scala:409:31]
.io_c (io_sum_self_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_sum_muladder_io_out)
); // @[Arithmetic.scala:416:30]
assign io_sum_bits = io_sum_bits_0; // @[AccumulatorMem.scala:63:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_28 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_28
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h1e), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h24), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h22), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h1c), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h20), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17)
node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18)
node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<6>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_28( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_109 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_109( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_43 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_43
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_43
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h17))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_9 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_10 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_11 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_12 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_13 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_14 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_15 :
connect states[7].g, UInt<3>(0h2)
node _T_16 = and(io.router_req.ready, io.router_req.valid)
when _T_16 :
node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_29 = and(io.router_req.ready, io.router_req.valid)
when _T_29 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_31 = or(_T_30, vcalloc_vals[2])
node _T_32 = or(_T_31, vcalloc_vals[3])
node _T_33 = or(_T_32, vcalloc_vals[4])
node _T_34 = or(_T_33, vcalloc_vals[5])
node _T_35 = or(_T_34, vcalloc_vals[6])
node _T_36 = or(_T_35, vcalloc_vals[7])
when _T_36 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[5]
invalidate vcalloc_reqs[0].vc_sel.`2`[6]
invalidate vcalloc_reqs[0].vc_sel.`2`[7]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].vc_sel.`3`[1]
invalidate vcalloc_reqs[0].vc_sel.`3`[2]
invalidate vcalloc_reqs[0].vc_sel.`3`[3]
invalidate vcalloc_reqs[0].vc_sel.`3`[4]
invalidate vcalloc_reqs[0].vc_sel.`3`[5]
invalidate vcalloc_reqs[0].vc_sel.`3`[6]
invalidate vcalloc_reqs[0].vc_sel.`3`[7]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_37 = bits(vcalloc_sel, 1, 1)
node _T_38 = and(vcalloc_vals[1], _T_37)
node _T_39 = and(_T_38, io.vcalloc_req.ready)
when _T_39 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_40 = bits(vcalloc_sel, 2, 2)
node _T_41 = and(vcalloc_vals[2], _T_40)
node _T_42 = and(_T_41, io.vcalloc_req.ready)
when _T_42 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_43 = bits(vcalloc_sel, 3, 3)
node _T_44 = and(vcalloc_vals[3], _T_43)
node _T_45 = and(_T_44, io.vcalloc_req.ready)
when _T_45 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_46 = bits(vcalloc_sel, 4, 4)
node _T_47 = and(vcalloc_vals[4], _T_46)
node _T_48 = and(_T_47, io.vcalloc_req.ready)
when _T_48 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_49 = bits(vcalloc_sel, 5, 5)
node _T_50 = and(vcalloc_vals[5], _T_49)
node _T_51 = and(_T_50, io.vcalloc_req.ready)
when _T_51 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_52 = bits(vcalloc_sel, 6, 6)
node _T_53 = and(vcalloc_vals[6], _T_52)
node _T_54 = and(_T_53, io.vcalloc_req.ready)
when _T_54 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_55 = bits(vcalloc_sel, 7, 7)
node _T_56 = and(vcalloc_vals[7], _T_55)
node _T_57 = and(_T_56, io.vcalloc_req.ready)
when _T_57 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_58 :
node _T_59 = bits(vcalloc_sel, 0, 0)
when _T_59 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_60 = eq(states[0].g, UInt<3>(0h2))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_60, UInt<1>(0h1), "") : assert_3
node _T_64 = bits(vcalloc_sel, 1, 1)
when _T_64 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_65 = eq(states[1].g, UInt<3>(0h2))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_65, UInt<1>(0h1), "") : assert_4
node _T_69 = bits(vcalloc_sel, 2, 2)
when _T_69 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_70 = eq(states[2].g, UInt<3>(0h2))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_70, UInt<1>(0h1), "") : assert_5
node _T_74 = bits(vcalloc_sel, 3, 3)
when _T_74 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_75 = eq(states[3].g, UInt<3>(0h2))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_75, UInt<1>(0h1), "") : assert_6
node _T_79 = bits(vcalloc_sel, 4, 4)
when _T_79 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_80 = eq(states[4].g, UInt<3>(0h2))
node _T_81 = asUInt(reset)
node _T_82 = eq(_T_81, UInt<1>(0h0))
when _T_82 :
node _T_83 = eq(_T_80, UInt<1>(0h0))
when _T_83 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_80, UInt<1>(0h1), "") : assert_7
node _T_84 = bits(vcalloc_sel, 5, 5)
when _T_84 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_85 = eq(states[5].g, UInt<3>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_85, UInt<1>(0h1), "") : assert_8
node _T_89 = bits(vcalloc_sel, 6, 6)
when _T_89 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_90 = eq(states[6].g, UInt<3>(0h2))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = bits(vcalloc_sel, 7, 7)
when _T_94 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_95 = eq(states[7].g, UInt<3>(0h2))
node _T_96 = asUInt(reset)
node _T_97 = eq(_T_96, UInt<1>(0h0))
when _T_97 :
node _T_98 = eq(_T_95, UInt<1>(0h0))
when _T_98 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_95, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_118
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7]
node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail)
when _T_100 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail)
when _T_102 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail)
when _T_104 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail)
when _T_106 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail)
when _T_108 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail)
when _T_110 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail)
when _T_112 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_113 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].vc_sel.`2`[5]
invalidate states[0].vc_sel.`2`[6]
invalidate states[0].vc_sel.`2`[7]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].vc_sel.`3`[1]
invalidate states[0].vc_sel.`3`[2]
invalidate states[0].vc_sel.`3`[3]
invalidate states[0].vc_sel.`3`[4]
invalidate states[0].vc_sel.`3`[5]
invalidate states[0].vc_sel.`3`[6]
invalidate states[0].vc_sel.`3`[7]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[1], UInt<1>(0h0)
connect states[1].vc_sel.`2`[2], UInt<1>(0h0)
connect states[1].vc_sel.`2`[3], UInt<1>(0h0)
connect states[1].vc_sel.`2`[4], UInt<1>(0h0)
connect states[1].vc_sel.`2`[5], UInt<1>(0h0)
connect states[1].vc_sel.`2`[6], UInt<1>(0h0)
connect states[1].vc_sel.`2`[7], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`3`[2], UInt<1>(0h0)
connect states[1].vc_sel.`3`[3], UInt<1>(0h0)
connect states[1].vc_sel.`3`[4], UInt<1>(0h0)
connect states[1].vc_sel.`3`[5], UInt<1>(0h0)
connect states[1].vc_sel.`3`[6], UInt<1>(0h0)
connect states[1].vc_sel.`3`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`2`[0], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`1`[5], UInt<1>(0h0)
connect states[4].vc_sel.`1`[6], UInt<1>(0h0)
connect states[4].vc_sel.`1`[7], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`1`[5], UInt<1>(0h0)
connect states[5].vc_sel.`1`[6], UInt<1>(0h0)
connect states[5].vc_sel.`1`[7], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`1`[5], UInt<1>(0h0)
connect states[6].vc_sel.`1`[6], UInt<1>(0h0)
connect states[6].vc_sel.`1`[7], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`1`[5], UInt<1>(0h0)
connect states[7].vc_sel.`1`[6], UInt<1>(0h0)
connect states[7].vc_sel.`1`[7], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
node _T_114 = asUInt(reset)
when _T_114 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_43( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_41 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_41( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_1(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_5 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_63
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleA_a32d256s5k3z4u_3
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonIn.a
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64)
node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2)
node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0))
node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 3)
regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonOut.a.ready, anonOut.a.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
node repeat_sel = bits(cated.bits.address, 4, 3)
node repeat_index = or(repeat_sel, repeat_count)
connect anonOut.a.bits, cated.bits
connect anonOut.a.valid, cated.valid
connect cated.ready, anonOut.a.ready
node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0)
node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64)
node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128)
node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192)
wire repeat_anonOut_a_bits_data_mux : UInt<64>[4]
connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T
connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1
connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2
connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3
connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index]
node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0)
node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8)
node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16)
node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24)
wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4]
connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T
connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1
connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2
connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3
connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
node hasData = bits(anonOut.d.bits.opcode, 0, 0)
node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size)
node _limit_T_1 = bits(_limit_T, 4, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 3)
regreset count : UInt<2>, clock, reset, UInt<2>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg)
node _T = and(anonOut.d.ready, anonOut.d.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonOut_d_ready_T = eq(last, UInt<1>(0h0))
node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T)
connect anonOut.d.ready, _anonOut_d_ready_T_1
node _anonIn_d_valid_T = and(anonOut.d.valid, last)
connect anonIn.d.valid, _anonIn_d_valid_T
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T)
node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1)
node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2)
node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3)
wire anonIn_d_bits_data_odata_0 : UInt
connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_1 : UInt
connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_2 : UInt
connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_3 : UInt
connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data
reg anonIn_d_bits_data_rdata : UInt<64>[3], clock
node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0])
node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1])
node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2])
node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data)
node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid)
node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1)
when _anonIn_d_bits_data_T_2 :
connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0
connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1
connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2
node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0)
node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2)
node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo)
connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3
connect anonIn.d.bits.corrupt, corrupt_out
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget32_5( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_63 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s5k3z4u_3 repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_195 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_359
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_195( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_359 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<1>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 0, 0)
node _source_ok_T = shr(io.in.a.bits.source, 1)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<1>(0h1))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_7
node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits = bits(_uncommonBits_T, 0, 0)
node _T_4 = shr(io.in.a.bits.source, 1)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<1>(0h1))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_28 = cvt(_T_27)
node _T_29 = and(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = asSInt(_T_29)
node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0)))
node _T_32 = or(_T_26, _T_31)
node _T_33 = and(_T_16, _T_24)
node _T_34 = and(_T_33, _T_32)
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
node _T_37 = eq(_T_34, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_34, UInt<1>(0h1), "") : assert_1
node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_38 :
node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_41 = and(_T_39, _T_40)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 0, 0)
node _T_42 = shr(io.in.a.bits.source, 1)
node _T_43 = eq(_T_42, UInt<1>(0h0))
node _T_44 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_45 = and(_T_43, _T_44)
node _T_46 = leq(uncommonBits_1, UInt<1>(0h1))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_50 = or(_T_47, _T_48)
node _T_51 = or(_T_50, _T_49)
node _T_52 = and(_T_41, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_59, _T_64)
node _T_96 = or(_T_95, _T_69)
node _T_97 = or(_T_96, _T_74)
node _T_98 = or(_T_97, _T_79)
node _T_99 = or(_T_98, _T_84)
node _T_100 = or(_T_99, _T_89)
node _T_101 = or(_T_100, _T_94)
node _T_102 = and(_T_54, _T_101)
node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = or(_T_109, _T_114)
node _T_116 = and(_T_104, _T_115)
node _T_117 = or(UInt<1>(0h0), _T_102)
node _T_118 = or(_T_117, _T_116)
node _T_119 = and(_T_53, _T_118)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_119, UInt<1>(0h1), "") : assert_2
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 0, 0)
node _T_123 = shr(io.in.a.bits.source, 1)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_2, UInt<1>(0h1))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_128
connect _WIRE[1], _T_129
connect _WIRE[2], _T_130
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0))
node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_135 = or(_T_132, _T_133)
node _T_136 = or(_T_135, _T_134)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_136
node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_139 = and(_T_137, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_145, _T_150)
node _T_192 = or(_T_191, _T_155)
node _T_193 = or(_T_192, _T_160)
node _T_194 = or(_T_193, _T_165)
node _T_195 = or(_T_194, _T_170)
node _T_196 = or(_T_195, _T_175)
node _T_197 = or(_T_196, _T_180)
node _T_198 = or(_T_197, _T_185)
node _T_199 = or(_T_198, _T_190)
node _T_200 = and(_T_140, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = and(_WIRE_1, _T_201)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_202, UInt<1>(0h1), "") : assert_3
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(source_ok, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_209, UInt<1>(0h1), "") : assert_5
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(is_aligned, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_216, UInt<1>(0h1), "") : assert_7
node _T_220 = not(io.in.a.bits.mask)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_221, UInt<1>(0h1), "") : assert_8
node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_225, UInt<1>(0h1), "") : assert_9
node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_229 :
node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 0, 0)
node _T_233 = shr(io.in.a.bits.source, 1)
node _T_234 = eq(_T_233, UInt<1>(0h0))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_3, UInt<1>(0h1))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_241 = or(_T_238, _T_239)
node _T_242 = or(_T_241, _T_240)
node _T_243 = and(_T_232, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_267 = cvt(_T_266)
node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000)))
node _T_269 = asSInt(_T_268)
node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0)))
node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_250, _T_255)
node _T_287 = or(_T_286, _T_260)
node _T_288 = or(_T_287, _T_265)
node _T_289 = or(_T_288, _T_270)
node _T_290 = or(_T_289, _T_275)
node _T_291 = or(_T_290, _T_280)
node _T_292 = or(_T_291, _T_285)
node _T_293 = and(_T_245, _T_292)
node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_293)
node _T_309 = or(_T_308, _T_307)
node _T_310 = and(_T_244, _T_309)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_310, UInt<1>(0h1), "") : assert_10
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 0, 0)
node _T_314 = shr(io.in.a.bits.source, 1)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_317 = and(_T_315, _T_316)
node _T_318 = leq(uncommonBits_4, UInt<1>(0h1))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_319
connect _WIRE_2[1], _T_320
connect _WIRE_2[2], _T_321
node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0))
node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_326 = or(_T_323, _T_324)
node _T_327 = or(_T_326, _T_325)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_327
node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_330 = and(_T_328, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_358 = cvt(_T_357)
node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000)))
node _T_360 = asSInt(_T_359)
node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0)))
node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = or(_T_336, _T_341)
node _T_383 = or(_T_382, _T_346)
node _T_384 = or(_T_383, _T_351)
node _T_385 = or(_T_384, _T_356)
node _T_386 = or(_T_385, _T_361)
node _T_387 = or(_T_386, _T_366)
node _T_388 = or(_T_387, _T_371)
node _T_389 = or(_T_388, _T_376)
node _T_390 = or(_T_389, _T_381)
node _T_391 = and(_T_331, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = and(_WIRE_3, _T_392)
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_393, UInt<1>(0h1), "") : assert_11
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(source_ok, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_400, UInt<1>(0h1), "") : assert_13
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(is_aligned, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_407, UInt<1>(0h1), "") : assert_15
node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_411, UInt<1>(0h1), "") : assert_16
node _T_415 = not(io.in.a.bits.mask)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_416, UInt<1>(0h1), "") : assert_17
node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_420, UInt<1>(0h1), "") : assert_18
node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_424 :
node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_427 = and(_T_425, _T_426)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 0, 0)
node _T_428 = shr(io.in.a.bits.source, 1)
node _T_429 = eq(_T_428, UInt<1>(0h0))
node _T_430 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_431 = and(_T_429, _T_430)
node _T_432 = leq(uncommonBits_5, UInt<1>(0h1))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_436 = or(_T_433, _T_434)
node _T_437 = or(_T_436, _T_435)
node _T_438 = and(_T_427, _T_437)
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_439, UInt<1>(0h1), "") : assert_19
node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_445 = and(_T_443, _T_444)
node _T_446 = or(UInt<1>(0h0), _T_445)
node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = and(_T_446, _T_451)
node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_455 = and(_T_453, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = or(_T_461, _T_466)
node _T_503 = or(_T_502, _T_471)
node _T_504 = or(_T_503, _T_476)
node _T_505 = or(_T_504, _T_481)
node _T_506 = or(_T_505, _T_486)
node _T_507 = or(_T_506, _T_491)
node _T_508 = or(_T_507, _T_496)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_456, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_452)
node _T_512 = or(_T_511, _T_510)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_512, UInt<1>(0h1), "") : assert_20
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(source_ok, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(is_aligned, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_522, UInt<1>(0h1), "") : assert_23
node _T_526 = eq(io.in.a.bits.mask, mask)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_526, UInt<1>(0h1), "") : assert_24
node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_530, UInt<1>(0h1), "") : assert_25
node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_534 :
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_537 = and(_T_535, _T_536)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 0, 0)
node _T_538 = shr(io.in.a.bits.source, 1)
node _T_539 = eq(_T_538, UInt<1>(0h0))
node _T_540 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_541 = and(_T_539, _T_540)
node _T_542 = leq(uncommonBits_6, UInt<1>(0h1))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_546 = or(_T_543, _T_544)
node _T_547 = or(_T_546, _T_545)
node _T_548 = and(_T_537, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_552 = and(_T_550, _T_551)
node _T_553 = or(UInt<1>(0h0), _T_552)
node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = and(_T_553, _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = or(_T_568, _T_573)
node _T_605 = or(_T_604, _T_578)
node _T_606 = or(_T_605, _T_583)
node _T_607 = or(_T_606, _T_588)
node _T_608 = or(_T_607, _T_593)
node _T_609 = or(_T_608, _T_598)
node _T_610 = or(_T_609, _T_603)
node _T_611 = and(_T_563, _T_610)
node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_559)
node _T_620 = or(_T_619, _T_611)
node _T_621 = or(_T_620, _T_618)
node _T_622 = and(_T_549, _T_621)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_622, UInt<1>(0h1), "") : assert_26
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(source_ok, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(is_aligned, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_632, UInt<1>(0h1), "") : assert_29
node _T_636 = eq(io.in.a.bits.mask, mask)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_636, UInt<1>(0h1), "") : assert_30
node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 0, 0)
node _T_644 = shr(io.in.a.bits.source, 1)
node _T_645 = eq(_T_644, UInt<1>(0h0))
node _T_646 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_647 = and(_T_645, _T_646)
node _T_648 = leq(uncommonBits_7, UInt<1>(0h1))
node _T_649 = and(_T_647, _T_648)
node _T_650 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_652 = or(_T_649, _T_650)
node _T_653 = or(_T_652, _T_651)
node _T_654 = and(_T_643, _T_653)
node _T_655 = or(UInt<1>(0h0), _T_654)
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = and(_T_659, _T_664)
node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_668 = and(_T_666, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_668)
node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_671 = cvt(_T_670)
node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000)))
node _T_673 = asSInt(_T_672)
node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0)))
node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = or(_T_674, _T_679)
node _T_711 = or(_T_710, _T_684)
node _T_712 = or(_T_711, _T_689)
node _T_713 = or(_T_712, _T_694)
node _T_714 = or(_T_713, _T_699)
node _T_715 = or(_T_714, _T_704)
node _T_716 = or(_T_715, _T_709)
node _T_717 = and(_T_669, _T_716)
node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = and(_T_718, _T_723)
node _T_725 = or(UInt<1>(0h0), _T_665)
node _T_726 = or(_T_725, _T_717)
node _T_727 = or(_T_726, _T_724)
node _T_728 = and(_T_655, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_728, UInt<1>(0h1), "") : assert_31
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(source_ok, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(is_aligned, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_738, UInt<1>(0h1), "") : assert_34
node _T_742 = not(mask)
node _T_743 = and(io.in.a.bits.mask, _T_742)
node _T_744 = eq(_T_743, UInt<1>(0h0))
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(_T_744, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_744, UInt<1>(0h1), "") : assert_35
node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_748 :
node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 0, 0)
node _T_752 = shr(io.in.a.bits.source, 1)
node _T_753 = eq(_T_752, UInt<1>(0h0))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_8, UInt<1>(0h1))
node _T_757 = and(_T_755, _T_756)
node _T_758 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_760 = or(_T_757, _T_758)
node _T_761 = or(_T_760, _T_759)
node _T_762 = and(_T_751, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_766 = and(_T_764, _T_765)
node _T_767 = or(UInt<1>(0h0), _T_766)
node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_769 = cvt(_T_768)
node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000)))
node _T_771 = asSInt(_T_770)
node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0)))
node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_774 = cvt(_T_773)
node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000)))
node _T_776 = asSInt(_T_775)
node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0)))
node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_784 = cvt(_T_783)
node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000)))
node _T_786 = asSInt(_T_785)
node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0)))
node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_789 = cvt(_T_788)
node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000)))
node _T_791 = asSInt(_T_790)
node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0)))
node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_794 = cvt(_T_793)
node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000)))
node _T_796 = asSInt(_T_795)
node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0)))
node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_799 = cvt(_T_798)
node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000)))
node _T_801 = asSInt(_T_800)
node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0)))
node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_809 = cvt(_T_808)
node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000)))
node _T_811 = asSInt(_T_810)
node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0)))
node _T_813 = or(_T_772, _T_777)
node _T_814 = or(_T_813, _T_782)
node _T_815 = or(_T_814, _T_787)
node _T_816 = or(_T_815, _T_792)
node _T_817 = or(_T_816, _T_797)
node _T_818 = or(_T_817, _T_802)
node _T_819 = or(_T_818, _T_807)
node _T_820 = or(_T_819, _T_812)
node _T_821 = and(_T_767, _T_820)
node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = and(_T_822, _T_827)
node _T_829 = or(UInt<1>(0h0), _T_821)
node _T_830 = or(_T_829, _T_828)
node _T_831 = and(_T_763, _T_830)
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_831, UInt<1>(0h1), "") : assert_36
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(source_ok, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(is_aligned, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_841, UInt<1>(0h1), "") : assert_39
node _T_845 = eq(io.in.a.bits.mask, mask)
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_845, UInt<1>(0h1), "") : assert_40
node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_849 :
node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 0, 0)
node _T_853 = shr(io.in.a.bits.source, 1)
node _T_854 = eq(_T_853, UInt<1>(0h0))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_9, UInt<1>(0h1))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_861 = or(_T_858, _T_859)
node _T_862 = or(_T_861, _T_860)
node _T_863 = and(_T_852, _T_862)
node _T_864 = or(UInt<1>(0h0), _T_863)
node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_867 = and(_T_865, _T_866)
node _T_868 = or(UInt<1>(0h0), _T_867)
node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = or(_T_873, _T_878)
node _T_915 = or(_T_914, _T_883)
node _T_916 = or(_T_915, _T_888)
node _T_917 = or(_T_916, _T_893)
node _T_918 = or(_T_917, _T_898)
node _T_919 = or(_T_918, _T_903)
node _T_920 = or(_T_919, _T_908)
node _T_921 = or(_T_920, _T_913)
node _T_922 = and(_T_868, _T_921)
node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = and(_T_923, _T_928)
node _T_930 = or(UInt<1>(0h0), _T_922)
node _T_931 = or(_T_930, _T_929)
node _T_932 = and(_T_864, _T_931)
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_932, UInt<1>(0h1), "") : assert_41
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(source_ok, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(is_aligned, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_942, UInt<1>(0h1), "") : assert_44
node _T_946 = eq(io.in.a.bits.mask, mask)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_946, UInt<1>(0h1), "") : assert_45
node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_950 :
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_953 = and(_T_951, _T_952)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<1>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 0, 0)
node _T_954 = shr(io.in.a.bits.source, 1)
node _T_955 = eq(_T_954, UInt<1>(0h0))
node _T_956 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_957 = and(_T_955, _T_956)
node _T_958 = leq(uncommonBits_10, UInt<1>(0h1))
node _T_959 = and(_T_957, _T_958)
node _T_960 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_962 = or(_T_959, _T_960)
node _T_963 = or(_T_962, _T_961)
node _T_964 = and(_T_953, _T_963)
node _T_965 = or(UInt<1>(0h0), _T_964)
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_968 = and(_T_966, _T_967)
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = and(_T_969, _T_974)
node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_988 = cvt(_T_987)
node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000)))
node _T_990 = asSInt(_T_989)
node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0)))
node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = or(_T_981, _T_986)
node _T_1013 = or(_T_1012, _T_991)
node _T_1014 = or(_T_1013, _T_996)
node _T_1015 = or(_T_1014, _T_1001)
node _T_1016 = or(_T_1015, _T_1006)
node _T_1017 = or(_T_1016, _T_1011)
node _T_1018 = and(_T_976, _T_1017)
node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1024 = cvt(_T_1023)
node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000)))
node _T_1026 = asSInt(_T_1025)
node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0)))
node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1029 = cvt(_T_1028)
node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000)))
node _T_1031 = asSInt(_T_1030)
node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0)))
node _T_1033 = or(_T_1027, _T_1032)
node _T_1034 = and(_T_1022, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_975)
node _T_1036 = or(_T_1035, _T_1018)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_965, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49
node _T_1052 = eq(io.in.a.bits.mask, mask)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50
node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<1>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 0, 0)
node _source_ok_T_9 = shr(io.in.d.bits.source, 1)
node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0))
node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<1>(0h1))
node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13)
node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<2>(0h2))
node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_14
connect _source_ok_WIRE_1[1], _source_ok_T_15
connect _source_ok_WIRE_1[2], _source_ok_T_16
node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1064 :
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(source_ok_1, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54
node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55
node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57
node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1084 :
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(source_ok_1, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(sink_ok, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60
node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(_T_1095, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61
node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62
node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63
node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1108 = or(UInt<1>(0h1), _T_1107)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64
node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1112 :
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok_1, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(sink_ok, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67
node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68
node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69
node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1132 = or(_T_1131, io.in.d.bits.corrupt)
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70
node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1137 = or(UInt<1>(0h1), _T_1136)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71
node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(source_ok_1, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73
node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74
node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1154 = or(UInt<1>(0h1), _T_1153)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75
node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1158 :
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok_1, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77
node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1167 = or(_T_1166, io.in.d.bits.corrupt)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78
node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1172 = or(UInt<1>(0h1), _T_1171)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79
node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1176 :
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(source_ok_1, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81
node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82
node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1189 = or(UInt<1>(0h1), _T_1188)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<1>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 0, 0)
node _T_1197 = shr(io.in.b.bits.source, 1)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_1200 = and(_T_1198, _T_1199)
node _T_1201 = leq(uncommonBits_11, UInt<1>(0h1))
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
node _T_1204 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1205 = cvt(_T_1204)
node _T_1206 = and(_T_1205, asSInt(UInt<1>(0h0)))
node _T_1207 = asSInt(_T_1206)
node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0)))
node _T_1209 = or(_T_1203, _T_1208)
node _T_1210 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1213 = cvt(_T_1212)
node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = asSInt(_T_1214)
node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0)))
node _T_1217 = or(_T_1211, _T_1216)
node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4))
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = or(_T_1219, _T_1224)
node _T_1226 = and(_T_1209, _T_1217)
node _T_1227 = and(_T_1226, _T_1225)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<1>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 0, 0)
node _legal_source_T = shr(io.in.b.bits.source, 1)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<1>(0h1))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T_5
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_7
node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<2>(0h2), UInt<1>(0h0))
node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10)
wire _legal_source_WIRE_1 : UInt<3>
connect _legal_source_WIRE_1, _legal_source_T_12
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1231 :
node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<1>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 0, 0)
node _T_1232 = shr(io.in.b.bits.source, 1)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
node _T_1234 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1235 = and(_T_1233, _T_1234)
node _T_1236 = leq(uncommonBits_12, UInt<1>(0h1))
node _T_1237 = and(_T_1235, _T_1236)
node _T_1238 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1237
connect _WIRE_4[1], _T_1238
connect _WIRE_4[2], _T_1239
node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1241 = mux(_WIRE_4[0], _T_1240, UInt<1>(0h0))
node _T_1242 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1242)
node _T_1245 = or(_T_1244, _T_1243)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1245
node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1248 = and(_T_1246, _T_1247)
node _T_1249 = or(UInt<1>(0h0), _T_1248)
node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1251 = cvt(_T_1250)
node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000)))
node _T_1253 = asSInt(_T_1252)
node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0)))
node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1256 = cvt(_T_1255)
node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000)))
node _T_1258 = asSInt(_T_1257)
node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0)))
node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1261 = cvt(_T_1260)
node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000)))
node _T_1263 = asSInt(_T_1262)
node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0)))
node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1266 = cvt(_T_1265)
node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000)))
node _T_1268 = asSInt(_T_1267)
node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0)))
node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1271 = cvt(_T_1270)
node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000)))
node _T_1273 = asSInt(_T_1272)
node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0)))
node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1276 = cvt(_T_1275)
node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000)))
node _T_1278 = asSInt(_T_1277)
node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0)))
node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1281 = cvt(_T_1280)
node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000)))
node _T_1283 = asSInt(_T_1282)
node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0)))
node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1286 = cvt(_T_1285)
node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000)))
node _T_1288 = asSInt(_T_1287)
node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0)))
node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1291 = cvt(_T_1290)
node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000)))
node _T_1293 = asSInt(_T_1292)
node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0)))
node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1296 = cvt(_T_1295)
node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000)))
node _T_1298 = asSInt(_T_1297)
node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0)))
node _T_1300 = or(_T_1254, _T_1259)
node _T_1301 = or(_T_1300, _T_1264)
node _T_1302 = or(_T_1301, _T_1269)
node _T_1303 = or(_T_1302, _T_1274)
node _T_1304 = or(_T_1303, _T_1279)
node _T_1305 = or(_T_1304, _T_1284)
node _T_1306 = or(_T_1305, _T_1289)
node _T_1307 = or(_T_1306, _T_1294)
node _T_1308 = or(_T_1307, _T_1299)
node _T_1309 = and(_T_1249, _T_1308)
node _T_1310 = or(UInt<1>(0h0), _T_1309)
node _T_1311 = and(_WIRE_5, _T_1310)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(address_ok, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(legal_source, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90
node _T_1328 = eq(io.in.b.bits.mask, mask_1)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91
node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92
node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1336 :
node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1339 = and(_T_1337, _T_1338)
node _T_1340 = or(UInt<1>(0h0), _T_1339)
node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1342 = cvt(_T_1341)
node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000)))
node _T_1344 = asSInt(_T_1343)
node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0)))
node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1347 = cvt(_T_1346)
node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000)))
node _T_1349 = asSInt(_T_1348)
node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0)))
node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1357 = cvt(_T_1356)
node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000)))
node _T_1359 = asSInt(_T_1358)
node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0)))
node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1362 = cvt(_T_1361)
node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000)))
node _T_1364 = asSInt(_T_1363)
node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0)))
node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1367 = cvt(_T_1366)
node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000)))
node _T_1369 = asSInt(_T_1368)
node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0)))
node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1372 = cvt(_T_1371)
node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000)))
node _T_1374 = asSInt(_T_1373)
node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0)))
node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1377 = cvt(_T_1376)
node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000)))
node _T_1379 = asSInt(_T_1378)
node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0)))
node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1382 = cvt(_T_1381)
node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000)))
node _T_1384 = asSInt(_T_1383)
node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0)))
node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = or(_T_1345, _T_1350)
node _T_1392 = or(_T_1391, _T_1355)
node _T_1393 = or(_T_1392, _T_1360)
node _T_1394 = or(_T_1393, _T_1365)
node _T_1395 = or(_T_1394, _T_1370)
node _T_1396 = or(_T_1395, _T_1375)
node _T_1397 = or(_T_1396, _T_1380)
node _T_1398 = or(_T_1397, _T_1385)
node _T_1399 = or(_T_1398, _T_1390)
node _T_1400 = and(_T_1340, _T_1399)
node _T_1401 = or(UInt<1>(0h0), _T_1400)
node _T_1402 = and(UInt<1>(0h0), _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(address_ok, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(legal_source, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1412 = asUInt(reset)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
when _T_1413 :
node _T_1414 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1416 = asUInt(reset)
node _T_1417 = eq(_T_1416, UInt<1>(0h0))
when _T_1417 :
node _T_1418 = eq(_T_1415, UInt<1>(0h0))
when _T_1418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97
node _T_1419 = eq(io.in.b.bits.mask, mask_1)
node _T_1420 = asUInt(reset)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(_T_1419, UInt<1>(0h0))
when _T_1422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98
node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99
node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1430 = and(_T_1428, _T_1429)
node _T_1431 = or(UInt<1>(0h0), _T_1430)
node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1433 = cvt(_T_1432)
node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000)))
node _T_1435 = asSInt(_T_1434)
node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0)))
node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1438 = cvt(_T_1437)
node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000)))
node _T_1440 = asSInt(_T_1439)
node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0)))
node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1443 = cvt(_T_1442)
node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000)))
node _T_1445 = asSInt(_T_1444)
node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0)))
node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1448 = cvt(_T_1447)
node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000)))
node _T_1450 = asSInt(_T_1449)
node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0)))
node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1453 = cvt(_T_1452)
node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000)))
node _T_1455 = asSInt(_T_1454)
node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0)))
node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1458 = cvt(_T_1457)
node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000)))
node _T_1460 = asSInt(_T_1459)
node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0)))
node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1468 = cvt(_T_1467)
node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000)))
node _T_1470 = asSInt(_T_1469)
node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0)))
node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1473 = cvt(_T_1472)
node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000)))
node _T_1475 = asSInt(_T_1474)
node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0)))
node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1478 = cvt(_T_1477)
node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000)))
node _T_1480 = asSInt(_T_1479)
node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0)))
node _T_1482 = or(_T_1436, _T_1441)
node _T_1483 = or(_T_1482, _T_1446)
node _T_1484 = or(_T_1483, _T_1451)
node _T_1485 = or(_T_1484, _T_1456)
node _T_1486 = or(_T_1485, _T_1461)
node _T_1487 = or(_T_1486, _T_1466)
node _T_1488 = or(_T_1487, _T_1471)
node _T_1489 = or(_T_1488, _T_1476)
node _T_1490 = or(_T_1489, _T_1481)
node _T_1491 = and(_T_1431, _T_1490)
node _T_1492 = or(UInt<1>(0h0), _T_1491)
node _T_1493 = and(UInt<1>(0h0), _T_1492)
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100
node _T_1497 = asUInt(reset)
node _T_1498 = eq(_T_1497, UInt<1>(0h0))
when _T_1498 :
node _T_1499 = eq(address_ok, UInt<1>(0h0))
when _T_1499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(legal_source, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104
node _T_1510 = eq(io.in.b.bits.mask, mask_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105
node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1514 :
node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1517 = and(_T_1515, _T_1516)
node _T_1518 = or(UInt<1>(0h0), _T_1517)
node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1520 = cvt(_T_1519)
node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000)))
node _T_1522 = asSInt(_T_1521)
node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0)))
node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1525 = cvt(_T_1524)
node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000)))
node _T_1527 = asSInt(_T_1526)
node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0)))
node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1530 = cvt(_T_1529)
node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000)))
node _T_1532 = asSInt(_T_1531)
node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0)))
node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1535 = cvt(_T_1534)
node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000)))
node _T_1537 = asSInt(_T_1536)
node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0)))
node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1540 = cvt(_T_1539)
node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000)))
node _T_1542 = asSInt(_T_1541)
node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0)))
node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1545 = cvt(_T_1544)
node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000)))
node _T_1547 = asSInt(_T_1546)
node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0)))
node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1550 = cvt(_T_1549)
node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000)))
node _T_1552 = asSInt(_T_1551)
node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0)))
node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1555 = cvt(_T_1554)
node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000)))
node _T_1557 = asSInt(_T_1556)
node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0)))
node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1560 = cvt(_T_1559)
node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000)))
node _T_1562 = asSInt(_T_1561)
node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0)))
node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1565 = cvt(_T_1564)
node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000)))
node _T_1567 = asSInt(_T_1566)
node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0)))
node _T_1569 = or(_T_1523, _T_1528)
node _T_1570 = or(_T_1569, _T_1533)
node _T_1571 = or(_T_1570, _T_1538)
node _T_1572 = or(_T_1571, _T_1543)
node _T_1573 = or(_T_1572, _T_1548)
node _T_1574 = or(_T_1573, _T_1553)
node _T_1575 = or(_T_1574, _T_1558)
node _T_1576 = or(_T_1575, _T_1563)
node _T_1577 = or(_T_1576, _T_1568)
node _T_1578 = and(_T_1518, _T_1577)
node _T_1579 = or(UInt<1>(0h0), _T_1578)
node _T_1580 = and(UInt<1>(0h0), _T_1579)
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(address_ok, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1587 = asUInt(reset)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
when _T_1588 :
node _T_1589 = eq(legal_source, UInt<1>(0h0))
when _T_1589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110
node _T_1597 = not(mask_1)
node _T_1598 = and(io.in.b.bits.mask, _T_1597)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111
node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1603 :
node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1606 = and(_T_1604, _T_1605)
node _T_1607 = or(UInt<1>(0h0), _T_1606)
node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1609 = cvt(_T_1608)
node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000)))
node _T_1611 = asSInt(_T_1610)
node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0)))
node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1614 = cvt(_T_1613)
node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000)))
node _T_1616 = asSInt(_T_1615)
node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0)))
node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1619 = cvt(_T_1618)
node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000)))
node _T_1621 = asSInt(_T_1620)
node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0)))
node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1624 = cvt(_T_1623)
node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000)))
node _T_1626 = asSInt(_T_1625)
node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0)))
node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1629 = cvt(_T_1628)
node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000)))
node _T_1631 = asSInt(_T_1630)
node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0)))
node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1634 = cvt(_T_1633)
node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000)))
node _T_1636 = asSInt(_T_1635)
node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0)))
node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1639 = cvt(_T_1638)
node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000)))
node _T_1641 = asSInt(_T_1640)
node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0)))
node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1644 = cvt(_T_1643)
node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000)))
node _T_1646 = asSInt(_T_1645)
node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0)))
node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1649 = cvt(_T_1648)
node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000)))
node _T_1651 = asSInt(_T_1650)
node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0)))
node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1654 = cvt(_T_1653)
node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000)))
node _T_1656 = asSInt(_T_1655)
node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0)))
node _T_1658 = or(_T_1612, _T_1617)
node _T_1659 = or(_T_1658, _T_1622)
node _T_1660 = or(_T_1659, _T_1627)
node _T_1661 = or(_T_1660, _T_1632)
node _T_1662 = or(_T_1661, _T_1637)
node _T_1663 = or(_T_1662, _T_1642)
node _T_1664 = or(_T_1663, _T_1647)
node _T_1665 = or(_T_1664, _T_1652)
node _T_1666 = or(_T_1665, _T_1657)
node _T_1667 = and(_T_1607, _T_1666)
node _T_1668 = or(UInt<1>(0h0), _T_1667)
node _T_1669 = and(UInt<1>(0h0), _T_1668)
node _T_1670 = asUInt(reset)
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(_T_1669, UInt<1>(0h0))
when _T_1672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112
node _T_1673 = asUInt(reset)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
when _T_1674 :
node _T_1675 = eq(address_ok, UInt<1>(0h0))
when _T_1675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(legal_source, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116
node _T_1686 = eq(io.in.b.bits.mask, mask_1)
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(_T_1686, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117
node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1690 :
node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1693 = and(_T_1691, _T_1692)
node _T_1694 = or(UInt<1>(0h0), _T_1693)
node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1696 = cvt(_T_1695)
node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000)))
node _T_1698 = asSInt(_T_1697)
node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0)))
node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1701 = cvt(_T_1700)
node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000)))
node _T_1703 = asSInt(_T_1702)
node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0)))
node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1706 = cvt(_T_1705)
node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000)))
node _T_1708 = asSInt(_T_1707)
node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0)))
node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1711 = cvt(_T_1710)
node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000)))
node _T_1713 = asSInt(_T_1712)
node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0)))
node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1716 = cvt(_T_1715)
node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000)))
node _T_1718 = asSInt(_T_1717)
node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0)))
node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1721 = cvt(_T_1720)
node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000)))
node _T_1723 = asSInt(_T_1722)
node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0)))
node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1726 = cvt(_T_1725)
node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000)))
node _T_1728 = asSInt(_T_1727)
node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0)))
node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1731 = cvt(_T_1730)
node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000)))
node _T_1733 = asSInt(_T_1732)
node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0)))
node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1736 = cvt(_T_1735)
node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000)))
node _T_1738 = asSInt(_T_1737)
node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0)))
node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1741 = cvt(_T_1740)
node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000)))
node _T_1743 = asSInt(_T_1742)
node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0)))
node _T_1745 = or(_T_1699, _T_1704)
node _T_1746 = or(_T_1745, _T_1709)
node _T_1747 = or(_T_1746, _T_1714)
node _T_1748 = or(_T_1747, _T_1719)
node _T_1749 = or(_T_1748, _T_1724)
node _T_1750 = or(_T_1749, _T_1729)
node _T_1751 = or(_T_1750, _T_1734)
node _T_1752 = or(_T_1751, _T_1739)
node _T_1753 = or(_T_1752, _T_1744)
node _T_1754 = and(_T_1694, _T_1753)
node _T_1755 = or(UInt<1>(0h0), _T_1754)
node _T_1756 = and(UInt<1>(0h0), _T_1755)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(address_ok, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(legal_source, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122
node _T_1773 = eq(io.in.b.bits.mask, mask_1)
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123
node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1777 :
node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = or(UInt<1>(0h0), _T_1780)
node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1783 = cvt(_T_1782)
node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000)))
node _T_1785 = asSInt(_T_1784)
node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0)))
node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1788 = cvt(_T_1787)
node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000)))
node _T_1790 = asSInt(_T_1789)
node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0)))
node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1793 = cvt(_T_1792)
node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000)))
node _T_1795 = asSInt(_T_1794)
node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0)))
node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1798 = cvt(_T_1797)
node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000)))
node _T_1800 = asSInt(_T_1799)
node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0)))
node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1803 = cvt(_T_1802)
node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000)))
node _T_1805 = asSInt(_T_1804)
node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0)))
node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1808 = cvt(_T_1807)
node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000)))
node _T_1810 = asSInt(_T_1809)
node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0)))
node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1813 = cvt(_T_1812)
node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000)))
node _T_1815 = asSInt(_T_1814)
node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0)))
node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1818 = cvt(_T_1817)
node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000)))
node _T_1820 = asSInt(_T_1819)
node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0)))
node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1823 = cvt(_T_1822)
node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000)))
node _T_1825 = asSInt(_T_1824)
node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0)))
node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1828 = cvt(_T_1827)
node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000)))
node _T_1830 = asSInt(_T_1829)
node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0)))
node _T_1832 = or(_T_1786, _T_1791)
node _T_1833 = or(_T_1832, _T_1796)
node _T_1834 = or(_T_1833, _T_1801)
node _T_1835 = or(_T_1834, _T_1806)
node _T_1836 = or(_T_1835, _T_1811)
node _T_1837 = or(_T_1836, _T_1816)
node _T_1838 = or(_T_1837, _T_1821)
node _T_1839 = or(_T_1838, _T_1826)
node _T_1840 = or(_T_1839, _T_1831)
node _T_1841 = and(_T_1781, _T_1840)
node _T_1842 = or(UInt<1>(0h0), _T_1841)
node _T_1843 = and(UInt<1>(0h0), _T_1842)
node _T_1844 = asUInt(reset)
node _T_1845 = eq(_T_1844, UInt<1>(0h0))
when _T_1845 :
node _T_1846 = eq(_T_1843, UInt<1>(0h0))
when _T_1846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(address_ok, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1850 = asUInt(reset)
node _T_1851 = eq(_T_1850, UInt<1>(0h0))
when _T_1851 :
node _T_1852 = eq(legal_source, UInt<1>(0h0))
when _T_1852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1853 = asUInt(reset)
node _T_1854 = eq(_T_1853, UInt<1>(0h0))
when _T_1854 :
node _T_1855 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1855 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1856 = eq(io.in.b.bits.mask, mask_1)
node _T_1857 = asUInt(reset)
node _T_1858 = eq(_T_1857, UInt<1>(0h0))
when _T_1858 :
node _T_1859 = eq(_T_1856, UInt<1>(0h0))
when _T_1859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128
node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1861 = asUInt(reset)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
node _T_1863 = eq(_T_1860, UInt<1>(0h0))
when _T_1863 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(_T_1864, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<1>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 0, 0)
node _source_ok_T_18 = shr(io.in.c.bits.source, 1)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<1>(0h1))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_23
connect _source_ok_WIRE_2[1], _source_ok_T_24
connect _source_ok_WIRE_2[2], _source_ok_T_25
node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<1>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 0, 0)
node _T_1868 = shr(io.in.c.bits.source, 1)
node _T_1869 = eq(_T_1868, UInt<1>(0h0))
node _T_1870 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_1871 = and(_T_1869, _T_1870)
node _T_1872 = leq(uncommonBits_13, UInt<1>(0h1))
node _T_1873 = and(_T_1871, _T_1872)
node _T_1874 = eq(_T_1873, UInt<1>(0h0))
node _T_1875 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1876 = cvt(_T_1875)
node _T_1877 = and(_T_1876, asSInt(UInt<1>(0h0)))
node _T_1878 = asSInt(_T_1877)
node _T_1879 = eq(_T_1878, asSInt(UInt<1>(0h0)))
node _T_1880 = or(_T_1874, _T_1879)
node _T_1881 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1882 = eq(_T_1881, UInt<1>(0h0))
node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1884 = cvt(_T_1883)
node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0)))
node _T_1886 = asSInt(_T_1885)
node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0)))
node _T_1888 = or(_T_1882, _T_1887)
node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1890 = eq(_T_1889, UInt<1>(0h0))
node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1892 = cvt(_T_1891)
node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = asSInt(_T_1893)
node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0)))
node _T_1896 = or(_T_1890, _T_1895)
node _T_1897 = and(_T_1880, _T_1888)
node _T_1898 = and(_T_1897, _T_1896)
node _T_1899 = asUInt(reset)
node _T_1900 = eq(_T_1899, UInt<1>(0h0))
when _T_1900 :
node _T_1901 = eq(_T_1898, UInt<1>(0h0))
when _T_1901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131
node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1902 :
node _T_1903 = asUInt(reset)
node _T_1904 = eq(_T_1903, UInt<1>(0h0))
when _T_1904 :
node _T_1905 = eq(address_ok_1, UInt<1>(0h0))
when _T_1905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1906 = asUInt(reset)
node _T_1907 = eq(_T_1906, UInt<1>(0h0))
when _T_1907 :
node _T_1908 = eq(source_ok_2, UInt<1>(0h0))
when _T_1908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1910 = asUInt(reset)
node _T_1911 = eq(_T_1910, UInt<1>(0h0))
when _T_1911 :
node _T_1912 = eq(_T_1909, UInt<1>(0h0))
when _T_1912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134
node _T_1913 = asUInt(reset)
node _T_1914 = eq(_T_1913, UInt<1>(0h0))
when _T_1914 :
node _T_1915 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1917 = asUInt(reset)
node _T_1918 = eq(_T_1917, UInt<1>(0h0))
when _T_1918 :
node _T_1919 = eq(_T_1916, UInt<1>(0h0))
when _T_1919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136
node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1921 = asUInt(reset)
node _T_1922 = eq(_T_1921, UInt<1>(0h0))
when _T_1922 :
node _T_1923 = eq(_T_1920, UInt<1>(0h0))
when _T_1923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137
node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1924 :
node _T_1925 = asUInt(reset)
node _T_1926 = eq(_T_1925, UInt<1>(0h0))
when _T_1926 :
node _T_1927 = eq(address_ok_1, UInt<1>(0h0))
when _T_1927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1928 = asUInt(reset)
node _T_1929 = eq(_T_1928, UInt<1>(0h0))
when _T_1929 :
node _T_1930 = eq(source_ok_2, UInt<1>(0h0))
when _T_1930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1932 = asUInt(reset)
node _T_1933 = eq(_T_1932, UInt<1>(0h0))
when _T_1933 :
node _T_1934 = eq(_T_1931, UInt<1>(0h0))
when _T_1934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140
node _T_1935 = asUInt(reset)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
when _T_1936 :
node _T_1937 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1939 = asUInt(reset)
node _T_1940 = eq(_T_1939, UInt<1>(0h0))
when _T_1940 :
node _T_1941 = eq(_T_1938, UInt<1>(0h0))
when _T_1941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142
node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1942 :
node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1945 = and(_T_1943, _T_1944)
node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<1>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 0, 0)
node _T_1946 = shr(io.in.c.bits.source, 1)
node _T_1947 = eq(_T_1946, UInt<1>(0h0))
node _T_1948 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_1949 = and(_T_1947, _T_1948)
node _T_1950 = leq(uncommonBits_14, UInt<1>(0h1))
node _T_1951 = and(_T_1949, _T_1950)
node _T_1952 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1954 = or(_T_1951, _T_1952)
node _T_1955 = or(_T_1954, _T_1953)
node _T_1956 = and(_T_1945, _T_1955)
node _T_1957 = or(UInt<1>(0h0), _T_1956)
node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1960 = cvt(_T_1959)
node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000)))
node _T_1962 = asSInt(_T_1961)
node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0)))
node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1965 = cvt(_T_1964)
node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000)))
node _T_1967 = asSInt(_T_1966)
node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0)))
node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1970 = cvt(_T_1969)
node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000)))
node _T_1972 = asSInt(_T_1971)
node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0)))
node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1975 = cvt(_T_1974)
node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000)))
node _T_1977 = asSInt(_T_1976)
node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0)))
node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1980 = cvt(_T_1979)
node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000)))
node _T_1982 = asSInt(_T_1981)
node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0)))
node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1985 = cvt(_T_1984)
node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000)))
node _T_1987 = asSInt(_T_1986)
node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0)))
node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1990 = cvt(_T_1989)
node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000)))
node _T_1992 = asSInt(_T_1991)
node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0)))
node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1995 = cvt(_T_1994)
node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000)))
node _T_1997 = asSInt(_T_1996)
node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0)))
node _T_1999 = or(_T_1963, _T_1968)
node _T_2000 = or(_T_1999, _T_1973)
node _T_2001 = or(_T_2000, _T_1978)
node _T_2002 = or(_T_2001, _T_1983)
node _T_2003 = or(_T_2002, _T_1988)
node _T_2004 = or(_T_2003, _T_1993)
node _T_2005 = or(_T_2004, _T_1998)
node _T_2006 = and(_T_1958, _T_2005)
node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2008 = or(UInt<1>(0h0), _T_2007)
node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2010 = cvt(_T_2009)
node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000)))
node _T_2012 = asSInt(_T_2011)
node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0)))
node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2015 = cvt(_T_2014)
node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000)))
node _T_2017 = asSInt(_T_2016)
node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0)))
node _T_2019 = or(_T_2013, _T_2018)
node _T_2020 = and(_T_2008, _T_2019)
node _T_2021 = or(UInt<1>(0h0), _T_2006)
node _T_2022 = or(_T_2021, _T_2020)
node _T_2023 = and(_T_1957, _T_2022)
node _T_2024 = asUInt(reset)
node _T_2025 = eq(_T_2024, UInt<1>(0h0))
when _T_2025 :
node _T_2026 = eq(_T_2023, UInt<1>(0h0))
when _T_2026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143
node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<1>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 0, 0)
node _T_2027 = shr(io.in.c.bits.source, 1)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
node _T_2029 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_2030 = and(_T_2028, _T_2029)
node _T_2031 = leq(uncommonBits_15, UInt<1>(0h1))
node _T_2032 = and(_T_2030, _T_2031)
node _T_2033 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_2032
connect _WIRE_6[1], _T_2033
connect _WIRE_6[2], _T_2034
node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2036 = mux(_WIRE_6[0], _T_2035, UInt<1>(0h0))
node _T_2037 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2039 = or(_T_2036, _T_2037)
node _T_2040 = or(_T_2039, _T_2038)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2040
node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2043 = and(_T_2041, _T_2042)
node _T_2044 = or(UInt<1>(0h0), _T_2043)
node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2046 = cvt(_T_2045)
node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000)))
node _T_2048 = asSInt(_T_2047)
node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0)))
node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2051 = cvt(_T_2050)
node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000)))
node _T_2053 = asSInt(_T_2052)
node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0)))
node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2056 = cvt(_T_2055)
node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000)))
node _T_2058 = asSInt(_T_2057)
node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0)))
node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = or(_T_2049, _T_2054)
node _T_2096 = or(_T_2095, _T_2059)
node _T_2097 = or(_T_2096, _T_2064)
node _T_2098 = or(_T_2097, _T_2069)
node _T_2099 = or(_T_2098, _T_2074)
node _T_2100 = or(_T_2099, _T_2079)
node _T_2101 = or(_T_2100, _T_2084)
node _T_2102 = or(_T_2101, _T_2089)
node _T_2103 = or(_T_2102, _T_2094)
node _T_2104 = and(_T_2044, _T_2103)
node _T_2105 = or(UInt<1>(0h0), _T_2104)
node _T_2106 = and(_WIRE_7, _T_2105)
node _T_2107 = asUInt(reset)
node _T_2108 = eq(_T_2107, UInt<1>(0h0))
when _T_2108 :
node _T_2109 = eq(_T_2106, UInt<1>(0h0))
when _T_2109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144
node _T_2110 = asUInt(reset)
node _T_2111 = eq(_T_2110, UInt<1>(0h0))
when _T_2111 :
node _T_2112 = eq(source_ok_2, UInt<1>(0h0))
when _T_2112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146
node _T_2117 = asUInt(reset)
node _T_2118 = eq(_T_2117, UInt<1>(0h0))
when _T_2118 :
node _T_2119 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2121 = asUInt(reset)
node _T_2122 = eq(_T_2121, UInt<1>(0h0))
when _T_2122 :
node _T_2123 = eq(_T_2120, UInt<1>(0h0))
when _T_2123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148
node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149
node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2128 :
node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2131 = and(_T_2129, _T_2130)
node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<1>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 0, 0)
node _T_2132 = shr(io.in.c.bits.source, 1)
node _T_2133 = eq(_T_2132, UInt<1>(0h0))
node _T_2134 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_2135 = and(_T_2133, _T_2134)
node _T_2136 = leq(uncommonBits_16, UInt<1>(0h1))
node _T_2137 = and(_T_2135, _T_2136)
node _T_2138 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_2140 = or(_T_2137, _T_2138)
node _T_2141 = or(_T_2140, _T_2139)
node _T_2142 = and(_T_2131, _T_2141)
node _T_2143 = or(UInt<1>(0h0), _T_2142)
node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2146 = cvt(_T_2145)
node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000)))
node _T_2148 = asSInt(_T_2147)
node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0)))
node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2156 = cvt(_T_2155)
node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000)))
node _T_2158 = asSInt(_T_2157)
node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0)))
node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2161 = cvt(_T_2160)
node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000)))
node _T_2163 = asSInt(_T_2162)
node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0)))
node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2166 = cvt(_T_2165)
node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000)))
node _T_2168 = asSInt(_T_2167)
node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0)))
node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2171 = cvt(_T_2170)
node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000)))
node _T_2173 = asSInt(_T_2172)
node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0)))
node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2176 = cvt(_T_2175)
node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000)))
node _T_2178 = asSInt(_T_2177)
node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0)))
node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2181 = cvt(_T_2180)
node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000)))
node _T_2183 = asSInt(_T_2182)
node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0)))
node _T_2185 = or(_T_2149, _T_2154)
node _T_2186 = or(_T_2185, _T_2159)
node _T_2187 = or(_T_2186, _T_2164)
node _T_2188 = or(_T_2187, _T_2169)
node _T_2189 = or(_T_2188, _T_2174)
node _T_2190 = or(_T_2189, _T_2179)
node _T_2191 = or(_T_2190, _T_2184)
node _T_2192 = and(_T_2144, _T_2191)
node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2194 = or(UInt<1>(0h0), _T_2193)
node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2196 = cvt(_T_2195)
node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000)))
node _T_2198 = asSInt(_T_2197)
node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0)))
node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2201 = cvt(_T_2200)
node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000)))
node _T_2203 = asSInt(_T_2202)
node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0)))
node _T_2205 = or(_T_2199, _T_2204)
node _T_2206 = and(_T_2194, _T_2205)
node _T_2207 = or(UInt<1>(0h0), _T_2192)
node _T_2208 = or(_T_2207, _T_2206)
node _T_2209 = and(_T_2143, _T_2208)
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150
node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<1>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 0, 0)
node _T_2213 = shr(io.in.c.bits.source, 1)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
node _T_2215 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_2216 = and(_T_2214, _T_2215)
node _T_2217 = leq(uncommonBits_17, UInt<1>(0h1))
node _T_2218 = and(_T_2216, _T_2217)
node _T_2219 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2218
connect _WIRE_8[1], _T_2219
connect _WIRE_8[2], _T_2220
node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2222 = mux(_WIRE_8[0], _T_2221, UInt<1>(0h0))
node _T_2223 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2225 = or(_T_2222, _T_2223)
node _T_2226 = or(_T_2225, _T_2224)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2226
node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2229 = and(_T_2227, _T_2228)
node _T_2230 = or(UInt<1>(0h0), _T_2229)
node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2232 = cvt(_T_2231)
node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000)))
node _T_2234 = asSInt(_T_2233)
node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0)))
node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2237 = cvt(_T_2236)
node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000)))
node _T_2239 = asSInt(_T_2238)
node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0)))
node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2242 = cvt(_T_2241)
node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000)))
node _T_2244 = asSInt(_T_2243)
node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0)))
node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2247 = cvt(_T_2246)
node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000)))
node _T_2249 = asSInt(_T_2248)
node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0)))
node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2252 = cvt(_T_2251)
node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000)))
node _T_2254 = asSInt(_T_2253)
node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0)))
node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2257 = cvt(_T_2256)
node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000)))
node _T_2259 = asSInt(_T_2258)
node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0)))
node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2262 = cvt(_T_2261)
node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000)))
node _T_2264 = asSInt(_T_2263)
node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0)))
node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2267 = cvt(_T_2266)
node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000)))
node _T_2269 = asSInt(_T_2268)
node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0)))
node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2272 = cvt(_T_2271)
node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000)))
node _T_2274 = asSInt(_T_2273)
node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0)))
node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2277 = cvt(_T_2276)
node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000)))
node _T_2279 = asSInt(_T_2278)
node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0)))
node _T_2281 = or(_T_2235, _T_2240)
node _T_2282 = or(_T_2281, _T_2245)
node _T_2283 = or(_T_2282, _T_2250)
node _T_2284 = or(_T_2283, _T_2255)
node _T_2285 = or(_T_2284, _T_2260)
node _T_2286 = or(_T_2285, _T_2265)
node _T_2287 = or(_T_2286, _T_2270)
node _T_2288 = or(_T_2287, _T_2275)
node _T_2289 = or(_T_2288, _T_2280)
node _T_2290 = and(_T_2230, _T_2289)
node _T_2291 = or(UInt<1>(0h0), _T_2290)
node _T_2292 = and(_WIRE_9, _T_2291)
node _T_2293 = asUInt(reset)
node _T_2294 = eq(_T_2293, UInt<1>(0h0))
when _T_2294 :
node _T_2295 = eq(_T_2292, UInt<1>(0h0))
when _T_2295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
node _T_2298 = eq(source_ok_2, UInt<1>(0h0))
when _T_2298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153
node _T_2303 = asUInt(reset)
node _T_2304 = eq(_T_2303, UInt<1>(0h0))
when _T_2304 :
node _T_2305 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2307 = asUInt(reset)
node _T_2308 = eq(_T_2307, UInt<1>(0h0))
when _T_2308 :
node _T_2309 = eq(_T_2306, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155
node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2310 :
node _T_2311 = asUInt(reset)
node _T_2312 = eq(_T_2311, UInt<1>(0h0))
when _T_2312 :
node _T_2313 = eq(address_ok_1, UInt<1>(0h0))
when _T_2313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(source_ok_2, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2317 = asUInt(reset)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
when _T_2318 :
node _T_2319 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2321 = asUInt(reset)
node _T_2322 = eq(_T_2321, UInt<1>(0h0))
when _T_2322 :
node _T_2323 = eq(_T_2320, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159
node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2325 = asUInt(reset)
node _T_2326 = eq(_T_2325, UInt<1>(0h0))
when _T_2326 :
node _T_2327 = eq(_T_2324, UInt<1>(0h0))
when _T_2327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160
node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2328 :
node _T_2329 = asUInt(reset)
node _T_2330 = eq(_T_2329, UInt<1>(0h0))
when _T_2330 :
node _T_2331 = eq(address_ok_1, UInt<1>(0h0))
when _T_2331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(source_ok_2, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2335 = asUInt(reset)
node _T_2336 = eq(_T_2335, UInt<1>(0h0))
when _T_2336 :
node _T_2337 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2339 = asUInt(reset)
node _T_2340 = eq(_T_2339, UInt<1>(0h0))
when _T_2340 :
node _T_2341 = eq(_T_2338, UInt<1>(0h0))
when _T_2341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164
node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2342 :
node _T_2343 = asUInt(reset)
node _T_2344 = eq(_T_2343, UInt<1>(0h0))
when _T_2344 :
node _T_2345 = eq(address_ok_1, UInt<1>(0h0))
when _T_2345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2346 = asUInt(reset)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
when _T_2347 :
node _T_2348 = eq(source_ok_2, UInt<1>(0h0))
when _T_2348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2349 = asUInt(reset)
node _T_2350 = eq(_T_2349, UInt<1>(0h0))
when _T_2350 :
node _T_2351 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(_T_2352, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168
node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2363 = eq(a_first, UInt<1>(0h0))
node _T_2364 = and(io.in.a.valid, _T_2363)
when _T_2364 :
node _T_2365 = eq(io.in.a.bits.opcode, opcode)
node _T_2366 = asUInt(reset)
node _T_2367 = eq(_T_2366, UInt<1>(0h0))
when _T_2367 :
node _T_2368 = eq(_T_2365, UInt<1>(0h0))
when _T_2368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171
node _T_2369 = eq(io.in.a.bits.param, param)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172
node _T_2373 = eq(io.in.a.bits.size, size)
node _T_2374 = asUInt(reset)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
when _T_2375 :
node _T_2376 = eq(_T_2373, UInt<1>(0h0))
when _T_2376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173
node _T_2377 = eq(io.in.a.bits.source, source)
node _T_2378 = asUInt(reset)
node _T_2379 = eq(_T_2378, UInt<1>(0h0))
when _T_2379 :
node _T_2380 = eq(_T_2377, UInt<1>(0h0))
when _T_2380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174
node _T_2381 = eq(io.in.a.bits.address, address)
node _T_2382 = asUInt(reset)
node _T_2383 = eq(_T_2382, UInt<1>(0h0))
when _T_2383 :
node _T_2384 = eq(_T_2381, UInt<1>(0h0))
when _T_2384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175
node _T_2385 = and(io.in.a.ready, io.in.a.valid)
node _T_2386 = and(_T_2385, a_first)
when _T_2386 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2387 = eq(d_first, UInt<1>(0h0))
node _T_2388 = and(io.in.d.valid, _T_2387)
when _T_2388 :
node _T_2389 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2390 = asUInt(reset)
node _T_2391 = eq(_T_2390, UInt<1>(0h0))
when _T_2391 :
node _T_2392 = eq(_T_2389, UInt<1>(0h0))
when _T_2392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176
node _T_2393 = eq(io.in.d.bits.param, param_1)
node _T_2394 = asUInt(reset)
node _T_2395 = eq(_T_2394, UInt<1>(0h0))
when _T_2395 :
node _T_2396 = eq(_T_2393, UInt<1>(0h0))
when _T_2396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177
node _T_2397 = eq(io.in.d.bits.size, size_1)
node _T_2398 = asUInt(reset)
node _T_2399 = eq(_T_2398, UInt<1>(0h0))
when _T_2399 :
node _T_2400 = eq(_T_2397, UInt<1>(0h0))
when _T_2400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178
node _T_2401 = eq(io.in.d.bits.source, source_1)
node _T_2402 = asUInt(reset)
node _T_2403 = eq(_T_2402, UInt<1>(0h0))
when _T_2403 :
node _T_2404 = eq(_T_2401, UInt<1>(0h0))
when _T_2404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179
node _T_2405 = eq(io.in.d.bits.sink, sink)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180
node _T_2409 = eq(io.in.d.bits.denied, denied)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181
node _T_2413 = and(io.in.d.ready, io.in.d.valid)
node _T_2414 = and(_T_2413, d_first)
when _T_2414 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2415 = eq(b_first, UInt<1>(0h0))
node _T_2416 = and(io.in.b.valid, _T_2415)
when _T_2416 :
node _T_2417 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2418 = asUInt(reset)
node _T_2419 = eq(_T_2418, UInt<1>(0h0))
when _T_2419 :
node _T_2420 = eq(_T_2417, UInt<1>(0h0))
when _T_2420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182
node _T_2421 = eq(io.in.b.bits.param, param_2)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183
node _T_2425 = eq(io.in.b.bits.size, size_2)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184
node _T_2429 = eq(io.in.b.bits.source, source_2)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185
node _T_2433 = eq(io.in.b.bits.address, address_1)
node _T_2434 = asUInt(reset)
node _T_2435 = eq(_T_2434, UInt<1>(0h0))
when _T_2435 :
node _T_2436 = eq(_T_2433, UInt<1>(0h0))
when _T_2436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186
node _T_2437 = and(io.in.b.ready, io.in.b.valid)
node _T_2438 = and(_T_2437, b_first)
when _T_2438 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2439 = eq(c_first, UInt<1>(0h0))
node _T_2440 = and(io.in.c.valid, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2442 = asUInt(reset)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
when _T_2443 :
node _T_2444 = eq(_T_2441, UInt<1>(0h0))
when _T_2444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187
node _T_2445 = eq(io.in.c.bits.param, param_3)
node _T_2446 = asUInt(reset)
node _T_2447 = eq(_T_2446, UInt<1>(0h0))
when _T_2447 :
node _T_2448 = eq(_T_2445, UInt<1>(0h0))
when _T_2448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188
node _T_2449 = eq(io.in.c.bits.size, size_3)
node _T_2450 = asUInt(reset)
node _T_2451 = eq(_T_2450, UInt<1>(0h0))
when _T_2451 :
node _T_2452 = eq(_T_2449, UInt<1>(0h0))
when _T_2452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189
node _T_2453 = eq(io.in.c.bits.source, source_3)
node _T_2454 = asUInt(reset)
node _T_2455 = eq(_T_2454, UInt<1>(0h0))
when _T_2455 :
node _T_2456 = eq(_T_2453, UInt<1>(0h0))
when _T_2456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190
node _T_2457 = eq(io.in.c.bits.address, address_2)
node _T_2458 = asUInt(reset)
node _T_2459 = eq(_T_2458, UInt<1>(0h0))
when _T_2459 :
node _T_2460 = eq(_T_2457, UInt<1>(0h0))
when _T_2460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191
node _T_2461 = and(io.in.c.ready, io.in.c.valid)
node _T_2462 = and(_T_2461, c_first)
when _T_2462 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<5>
connect a_set, UInt<5>(0h0)
wire a_set_wo_ready : UInt<5>
connect a_set_wo_ready, UInt<5>(0h0)
wire a_opcodes_set : UInt<20>
connect a_opcodes_set, UInt<20>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2463 = and(io.in.a.valid, a_first_1)
node _T_2464 = and(_T_2463, UInt<1>(0h1))
when _T_2464 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2465 = and(io.in.a.ready, io.in.a.valid)
node _T_2466 = and(_T_2465, a_first_1)
node _T_2467 = and(_T_2466, UInt<1>(0h1))
when _T_2467 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2468 = dshr(inflight, io.in.a.bits.source)
node _T_2469 = bits(_T_2468, 0, 0)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
node _T_2471 = asUInt(reset)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
when _T_2472 :
node _T_2473 = eq(_T_2470, UInt<1>(0h0))
when _T_2473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<5>
connect d_clr, UInt<5>(0h0)
wire d_clr_wo_ready : UInt<5>
connect d_clr_wo_ready, UInt<5>(0h0)
wire d_opcodes_clr : UInt<20>
connect d_opcodes_clr, UInt<20>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2474 = and(io.in.d.valid, d_first_1)
node _T_2475 = and(_T_2474, UInt<1>(0h1))
node _T_2476 = eq(d_release_ack, UInt<1>(0h0))
node _T_2477 = and(_T_2475, _T_2476)
when _T_2477 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2478 = and(io.in.d.ready, io.in.d.valid)
node _T_2479 = and(_T_2478, d_first_1)
node _T_2480 = and(_T_2479, UInt<1>(0h1))
node _T_2481 = eq(d_release_ack, UInt<1>(0h0))
node _T_2482 = and(_T_2480, _T_2481)
when _T_2482 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2483 = and(io.in.d.valid, d_first_1)
node _T_2484 = and(_T_2483, UInt<1>(0h1))
node _T_2485 = eq(d_release_ack, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2487 = dshr(inflight, io.in.d.bits.source)
node _T_2488 = bits(_T_2487, 0, 0)
node _T_2489 = or(_T_2488, same_cycle_resp)
node _T_2490 = asUInt(reset)
node _T_2491 = eq(_T_2490, UInt<1>(0h0))
when _T_2491 :
node _T_2492 = eq(_T_2489, UInt<1>(0h0))
when _T_2492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2495 = or(_T_2493, _T_2494)
node _T_2496 = asUInt(reset)
node _T_2497 = eq(_T_2496, UInt<1>(0h0))
when _T_2497 :
node _T_2498 = eq(_T_2495, UInt<1>(0h0))
when _T_2498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194
node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2500 = asUInt(reset)
node _T_2501 = eq(_T_2500, UInt<1>(0h0))
when _T_2501 :
node _T_2502 = eq(_T_2499, UInt<1>(0h0))
when _T_2502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195
else :
node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2505 = or(_T_2503, _T_2504)
node _T_2506 = asUInt(reset)
node _T_2507 = eq(_T_2506, UInt<1>(0h0))
when _T_2507 :
node _T_2508 = eq(_T_2505, UInt<1>(0h0))
when _T_2508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196
node _T_2509 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197
node _T_2513 = and(io.in.d.valid, d_first_1)
node _T_2514 = and(_T_2513, a_first_1)
node _T_2515 = and(_T_2514, io.in.a.valid)
node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2517 = and(_T_2515, _T_2516)
node _T_2518 = eq(d_release_ack, UInt<1>(0h0))
node _T_2519 = and(_T_2517, _T_2518)
when _T_2519 :
node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2521 = or(_T_2520, io.in.a.ready)
node _T_2522 = asUInt(reset)
node _T_2523 = eq(_T_2522, UInt<1>(0h0))
when _T_2523 :
node _T_2524 = eq(_T_2521, UInt<1>(0h0))
when _T_2524 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198
node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2526 = orr(a_set_wo_ready)
node _T_2527 = eq(_T_2526, UInt<1>(0h0))
node _T_2528 = or(_T_2525, _T_2527)
node _T_2529 = asUInt(reset)
node _T_2530 = eq(_T_2529, UInt<1>(0h0))
when _T_2530 :
node _T_2531 = eq(_T_2528, UInt<1>(0h0))
when _T_2531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_8
node _T_2532 = orr(inflight)
node _T_2533 = eq(_T_2532, UInt<1>(0h0))
node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2535 = or(_T_2533, _T_2534)
node _T_2536 = lt(watchdog, plusarg_reader.out)
node _T_2537 = or(_T_2535, _T_2536)
node _T_2538 = asUInt(reset)
node _T_2539 = eq(_T_2538, UInt<1>(0h0))
when _T_2539 :
node _T_2540 = eq(_T_2537, UInt<1>(0h0))
when _T_2540 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2541 = and(io.in.a.ready, io.in.a.valid)
node _T_2542 = and(io.in.d.ready, io.in.d.valid)
node _T_2543 = or(_T_2541, _T_2542)
when _T_2543 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<5>
connect c_set, UInt<5>(0h0)
wire c_set_wo_ready : UInt<5>
connect c_set_wo_ready, UInt<5>(0h0)
wire c_opcodes_set : UInt<20>
connect c_opcodes_set, UInt<20>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2544 = and(io.in.c.valid, c_first_1)
node _T_2545 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2546 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2547 = and(_T_2545, _T_2546)
node _T_2548 = and(_T_2544, _T_2547)
when _T_2548 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2549 = and(io.in.c.ready, io.in.c.valid)
node _T_2550 = and(_T_2549, c_first_1)
node _T_2551 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2552 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2553 = and(_T_2551, _T_2552)
node _T_2554 = and(_T_2550, _T_2553)
when _T_2554 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2555 = dshr(inflight_1, io.in.c.bits.source)
node _T_2556 = bits(_T_2555, 0, 0)
node _T_2557 = eq(_T_2556, UInt<1>(0h0))
node _T_2558 = asUInt(reset)
node _T_2559 = eq(_T_2558, UInt<1>(0h0))
when _T_2559 :
node _T_2560 = eq(_T_2557, UInt<1>(0h0))
when _T_2560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<5>
connect d_clr_1, UInt<5>(0h0)
wire d_clr_wo_ready_1 : UInt<5>
connect d_clr_wo_ready_1, UInt<5>(0h0)
wire d_opcodes_clr_1 : UInt<20>
connect d_opcodes_clr_1, UInt<20>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2561 = and(io.in.d.valid, d_first_2)
node _T_2562 = and(_T_2561, UInt<1>(0h1))
node _T_2563 = and(_T_2562, d_release_ack_1)
when _T_2563 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2564 = and(io.in.d.ready, io.in.d.valid)
node _T_2565 = and(_T_2564, d_first_2)
node _T_2566 = and(_T_2565, UInt<1>(0h1))
node _T_2567 = and(_T_2566, d_release_ack_1)
when _T_2567 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2568 = and(io.in.d.valid, d_first_2)
node _T_2569 = and(_T_2568, UInt<1>(0h1))
node _T_2570 = and(_T_2569, d_release_ack_1)
when _T_2570 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2571 = dshr(inflight_1, io.in.d.bits.source)
node _T_2572 = bits(_T_2571, 0, 0)
node _T_2573 = or(_T_2572, same_cycle_resp_1)
node _T_2574 = asUInt(reset)
node _T_2575 = eq(_T_2574, UInt<1>(0h0))
when _T_2575 :
node _T_2576 = eq(_T_2573, UInt<1>(0h0))
when _T_2576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2578 = asUInt(reset)
node _T_2579 = eq(_T_2578, UInt<1>(0h0))
when _T_2579 :
node _T_2580 = eq(_T_2577, UInt<1>(0h0))
when _T_2580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203
else :
node _T_2581 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2582 = asUInt(reset)
node _T_2583 = eq(_T_2582, UInt<1>(0h0))
when _T_2583 :
node _T_2584 = eq(_T_2581, UInt<1>(0h0))
when _T_2584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204
node _T_2585 = and(io.in.d.valid, d_first_2)
node _T_2586 = and(_T_2585, c_first_1)
node _T_2587 = and(_T_2586, io.in.c.valid)
node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2589 = and(_T_2587, _T_2588)
node _T_2590 = and(_T_2589, d_release_ack_1)
node _T_2591 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2592 = and(_T_2590, _T_2591)
when _T_2592 :
node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2594 = or(_T_2593, io.in.c.ready)
node _T_2595 = asUInt(reset)
node _T_2596 = eq(_T_2595, UInt<1>(0h0))
when _T_2596 :
node _T_2597 = eq(_T_2594, UInt<1>(0h0))
when _T_2597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205
node _T_2598 = orr(c_set_wo_ready)
when _T_2598 :
node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2600 = asUInt(reset)
node _T_2601 = eq(_T_2600, UInt<1>(0h0))
when _T_2601 :
node _T_2602 = eq(_T_2599, UInt<1>(0h0))
when _T_2602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_9
node _T_2603 = orr(inflight_1)
node _T_2604 = eq(_T_2603, UInt<1>(0h0))
node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2606 = or(_T_2604, _T_2605)
node _T_2607 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2608 = or(_T_2606, _T_2607)
node _T_2609 = asUInt(reset)
node _T_2610 = eq(_T_2609, UInt<1>(0h0))
when _T_2610 :
node _T_2611 = eq(_T_2608, UInt<1>(0h0))
when _T_2611 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2612 = and(io.in.c.ready, io.in.c.valid)
node _T_2613 = and(io.in.d.ready, io.in.d.valid)
node _T_2614 = or(_T_2612, _T_2613)
when _T_2614 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2615 = and(io.in.d.ready, io.in.d.valid)
node _T_2616 = and(_T_2615, d_first_3)
node _T_2617 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2618 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2619 = eq(_T_2618, UInt<1>(0h0))
node _T_2620 = and(_T_2617, _T_2619)
node _T_2621 = and(_T_2616, _T_2620)
when _T_2621 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2622 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2623 = bits(_T_2622, 0, 0)
node _T_2624 = eq(_T_2623, UInt<1>(0h0))
node _T_2625 = asUInt(reset)
node _T_2626 = eq(_T_2625, UInt<1>(0h0))
when _T_2626 :
node _T_2627 = eq(_T_2624, UInt<1>(0h0))
when _T_2627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2628 = and(io.in.e.ready, io.in.e.valid)
node _T_2629 = and(_T_2628, UInt<1>(0h1))
node _T_2630 = and(_T_2629, UInt<1>(0h1))
when _T_2630 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2631 = or(d_set, inflight_2)
node _T_2632 = dshr(_T_2631, io.in.e.bits.sink)
node _T_2633 = bits(_T_2632, 0, 0)
node _T_2634 = asUInt(reset)
node _T_2635 = eq(_T_2634, UInt<1>(0h0))
when _T_2635 :
node _T_2636 = eq(_T_2633, UInt<1>(0h0))
when _T_2636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/bar-fetchers/src/main/scala/TLPrefetcher.scala:128:20)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_4( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] io_in_b_bits_source = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_11 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] _legal_source_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] _legal_source_T_10 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _legal_source_T_12 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _legal_source_WIRE_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _uncommonBits_T_12 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire uncommonBits_11 = 1'h0; // @[Parameters.scala:52:56]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire legal_source_uncommonBits = 1'h0; // @[Parameters.scala:52:56]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_7 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73]
wire uncommonBits_12 = 1'h0; // @[Parameters.scala:52:56]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [1:0] _legal_source_T = 2'h0; // @[Parameters.scala:54:10]
wire [1:0] _legal_source_T_9 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_11 = 2'h0; // @[Mux.scala:30:73]
wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire source_ok_uncommonBits = _source_ok_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[2:1]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31]
wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire uncommonBits = _uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_1 = _uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_2 = _uncommonBits_T_2[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_3 = _uncommonBits_T_3[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_4 = _uncommonBits_T_4[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_5 = _uncommonBits_T_5[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_6 = _uncommonBits_T_6[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_7 = _uncommonBits_T_7[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_8 = _uncommonBits_T_8[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_9 = _uncommonBits_T_9[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_10 = _uncommonBits_T_10[0]; // @[Parameters.scala:52:{29,56}]
wire source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_9 = io_in_d_bits_source_0[2:1]; // @[Monitor.scala:36:7]
wire _source_ok_T_10 = _source_ok_T_9 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_14 = _source_ok_T_12; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31]
wire _source_ok_T_15 = io_in_d_bits_source_0 == 3'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31]
wire _source_ok_T_16 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31]
wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_18 = io_in_c_bits_source_0[2:1]; // @[Monitor.scala:36:7]
wire _source_ok_T_19 = _source_ok_T_18 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = io_in_c_bits_source_0 == 3'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire uncommonBits_13 = _uncommonBits_T_13[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_14 = _uncommonBits_T_14[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_15 = _uncommonBits_T_15[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_16 = _uncommonBits_T_16[0]; // @[Parameters.scala:52:{29,56}]
wire uncommonBits_17 = _uncommonBits_T_17[0]; // @[Parameters.scala:52:{29,56}]
wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [2:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [2:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [4:0] inflight; // @[Monitor.scala:614:27]
reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [4:0] a_set; // @[Monitor.scala:626:34]
wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [5:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69]
wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101]
wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69]
wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101]
wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [5:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65]
wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99]
wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67]
wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [7:0] _GEN_20 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35]
wire [7:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2467 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [4:0] d_clr; // @[Monitor.scala:664:34]
wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46]
wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [7:0] _GEN_22 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35]
wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2482 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [4:0] inflight_1; // @[Monitor.scala:726:35]
reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [4:0] c_set; // @[Monitor.scala:738:34]
wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [7:0] _GEN_23 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [7:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2554 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [4:0] d_clr_1; // @[Monitor.scala:774:34]
wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2567 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35]
wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35]
assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h8))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 4)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<4>(0h8))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_T_13 = eq(io.in.a.bits.source, UInt<4>(0h9))
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_13
node _source_ok_T_14 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_15 = or(_source_ok_T_14, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_15, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h1))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h8))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_25 = shr(io.in.a.bits.source, 4)
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<4>(0h8))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _T_38 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = or(_T_39, _T_44)
node _T_46 = and(_T_16, _T_24)
node _T_47 = and(_T_46, _T_37)
node _T_48 = and(_T_47, _T_45)
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_48, UInt<1>(0h1), "") : assert_1
node _T_52 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_52 :
node _T_53 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_54 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_55 = and(_T_53, _T_54)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_56 = shr(io.in.a.bits.source, 4)
node _T_57 = eq(_T_56, UInt<1>(0h1))
node _T_58 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_59 = and(_T_57, _T_58)
node _T_60 = leq(uncommonBits_2, UInt<4>(0h8))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_63 = shr(io.in.a.bits.source, 4)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_66 = and(_T_64, _T_65)
node _T_67 = leq(uncommonBits_3, UInt<4>(0h8))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_70 = or(_T_61, _T_62)
node _T_71 = or(_T_70, _T_68)
node _T_72 = or(_T_71, _T_69)
node _T_73 = and(_T_55, _T_72)
node _T_74 = or(UInt<1>(0h0), _T_73)
node _T_75 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_76 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_77 = cvt(_T_76)
node _T_78 = and(_T_77, asSInt(UInt<13>(0h1000)))
node _T_79 = asSInt(_T_78)
node _T_80 = eq(_T_79, asSInt(UInt<1>(0h0)))
node _T_81 = and(_T_75, _T_80)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = and(_T_74, _T_82)
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_83, UInt<1>(0h1), "") : assert_2
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_87 = shr(io.in.a.bits.source, 4)
node _T_88 = eq(_T_87, UInt<1>(0h1))
node _T_89 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_90 = and(_T_88, _T_89)
node _T_91 = leq(uncommonBits_4, UInt<4>(0h8))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_94 = shr(io.in.a.bits.source, 4)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_5, UInt<4>(0h8))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.a.bits.source, UInt<4>(0h9))
wire _WIRE : UInt<1>[4]
connect _WIRE[0], _T_92
connect _WIRE[1], _T_93
connect _WIRE[2], _T_99
connect _WIRE[3], _T_100
node _T_101 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_102 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_103 = mux(_WIRE[0], _T_101, UInt<1>(0h0))
node _T_104 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_105 = mux(_WIRE[2], _T_102, UInt<1>(0h0))
node _T_106 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = or(_T_103, _T_104)
node _T_108 = or(_T_107, _T_105)
node _T_109 = or(_T_108, _T_106)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_109
node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_111 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_112 = and(_T_110, _T_111)
node _T_113 = or(UInt<1>(0h0), _T_112)
node _T_114 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<13>(0h1000)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = and(_T_113, _T_118)
node _T_120 = or(UInt<1>(0h0), _T_119)
node _T_121 = and(_WIRE_1, _T_120)
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_121, UInt<1>(0h1), "") : assert_3
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(source_ok, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_128 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_129 = asUInt(reset)
node _T_130 = eq(_T_129, UInt<1>(0h0))
when _T_130 :
node _T_131 = eq(_T_128, UInt<1>(0h0))
when _T_131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_128, UInt<1>(0h1), "") : assert_5
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(is_aligned, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_135 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_135, UInt<1>(0h1), "") : assert_7
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_140, UInt<1>(0h1), "") : assert_8
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_144, UInt<1>(0h1), "") : assert_9
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h1))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_6, UInt<4>(0h8))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_159 = shr(io.in.a.bits.source, 4)
node _T_160 = eq(_T_159, UInt<1>(0h0))
node _T_161 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_162 = and(_T_160, _T_161)
node _T_163 = leq(uncommonBits_7, UInt<4>(0h8))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_166 = or(_T_157, _T_158)
node _T_167 = or(_T_166, _T_164)
node _T_168 = or(_T_167, _T_165)
node _T_169 = and(_T_151, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_172 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<13>(0h1000)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = and(_T_171, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = and(_T_170, _T_178)
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_179, UInt<1>(0h1), "") : assert_10
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_183 = shr(io.in.a.bits.source, 4)
node _T_184 = eq(_T_183, UInt<1>(0h1))
node _T_185 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_186 = and(_T_184, _T_185)
node _T_187 = leq(uncommonBits_8, UInt<4>(0h8))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0)
node _T_190 = shr(io.in.a.bits.source, 4)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_193 = and(_T_191, _T_192)
node _T_194 = leq(uncommonBits_9, UInt<4>(0h8))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.a.bits.source, UInt<4>(0h9))
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], _T_188
connect _WIRE_2[1], _T_189
connect _WIRE_2[2], _T_195
connect _WIRE_2[3], _T_196
node _T_197 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_198 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_199 = mux(_WIRE_2[0], _T_197, UInt<1>(0h0))
node _T_200 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = mux(_WIRE_2[2], _T_198, UInt<1>(0h0))
node _T_202 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = or(_T_199, _T_200)
node _T_204 = or(_T_203, _T_201)
node _T_205 = or(_T_204, _T_202)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_205
node _T_206 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_207 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_208 = and(_T_206, _T_207)
node _T_209 = or(UInt<1>(0h0), _T_208)
node _T_210 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<13>(0h1000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = and(_T_209, _T_214)
node _T_216 = or(UInt<1>(0h0), _T_215)
node _T_217 = and(_WIRE_3, _T_216)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_217, UInt<1>(0h1), "") : assert_11
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(source_ok, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_224 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(_T_224, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_224, UInt<1>(0h1), "") : assert_13
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(is_aligned, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_231 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_232 = asUInt(reset)
node _T_233 = eq(_T_232, UInt<1>(0h0))
when _T_233 :
node _T_234 = eq(_T_231, UInt<1>(0h0))
when _T_234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_231, UInt<1>(0h1), "") : assert_15
node _T_235 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_235, UInt<1>(0h1), "") : assert_16
node _T_239 = not(io.in.a.bits.mask)
node _T_240 = eq(_T_239, UInt<1>(0h0))
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_240, UInt<1>(0h1), "") : assert_17
node _T_244 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(_T_244, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_244, UInt<1>(0h1), "") : assert_18
node _T_248 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_248 :
node _T_249 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_250 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_251 = and(_T_249, _T_250)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_252 = shr(io.in.a.bits.source, 4)
node _T_253 = eq(_T_252, UInt<1>(0h1))
node _T_254 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_255 = and(_T_253, _T_254)
node _T_256 = leq(uncommonBits_10, UInt<4>(0h8))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_259 = shr(io.in.a.bits.source, 4)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_11, UInt<4>(0h8))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_266 = or(_T_257, _T_258)
node _T_267 = or(_T_266, _T_264)
node _T_268 = or(_T_267, _T_265)
node _T_269 = and(_T_251, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_270, UInt<1>(0h1), "") : assert_19
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<13>(0h1000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = and(_T_277, _T_282)
node _T_284 = or(UInt<1>(0h0), _T_283)
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_284, UInt<1>(0h1), "") : assert_20
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(source_ok, UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(is_aligned, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_294 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_294, UInt<1>(0h1), "") : assert_23
node _T_298 = eq(io.in.a.bits.mask, mask)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_298, UInt<1>(0h1), "") : assert_24
node _T_302 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_T_302, UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_302, UInt<1>(0h1), "") : assert_25
node _T_306 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_306 :
node _T_307 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_308 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_309 = and(_T_307, _T_308)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0)
node _T_310 = shr(io.in.a.bits.source, 4)
node _T_311 = eq(_T_310, UInt<1>(0h1))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_12, UInt<4>(0h8))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0)
node _T_317 = shr(io.in.a.bits.source, 4)
node _T_318 = eq(_T_317, UInt<1>(0h0))
node _T_319 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_320 = and(_T_318, _T_319)
node _T_321 = leq(uncommonBits_13, UInt<4>(0h8))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_324 = or(_T_315, _T_316)
node _T_325 = or(_T_324, _T_322)
node _T_326 = or(_T_325, _T_323)
node _T_327 = and(_T_309, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_330 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_331 = and(_T_329, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<13>(0h1000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = and(_T_332, _T_337)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = and(_T_328, _T_339)
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_340, UInt<1>(0h1), "") : assert_26
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(source_ok, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(is_aligned, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_350 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_350, UInt<1>(0h1), "") : assert_29
node _T_354 = eq(io.in.a.bits.mask, mask)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_354, UInt<1>(0h1), "") : assert_30
node _T_358 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_358 :
node _T_359 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_360 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_361 = and(_T_359, _T_360)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0)
node _T_362 = shr(io.in.a.bits.source, 4)
node _T_363 = eq(_T_362, UInt<1>(0h1))
node _T_364 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_365 = and(_T_363, _T_364)
node _T_366 = leq(uncommonBits_14, UInt<4>(0h8))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_15, UInt<4>(0h8))
node _T_374 = and(_T_372, _T_373)
node _T_375 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_376 = or(_T_367, _T_368)
node _T_377 = or(_T_376, _T_374)
node _T_378 = or(_T_377, _T_375)
node _T_379 = and(_T_361, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_383 = and(_T_381, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_386 = cvt(_T_385)
node _T_387 = and(_T_386, asSInt(UInt<13>(0h1000)))
node _T_388 = asSInt(_T_387)
node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0)))
node _T_390 = and(_T_384, _T_389)
node _T_391 = or(UInt<1>(0h0), _T_390)
node _T_392 = and(_T_380, _T_391)
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_392, UInt<1>(0h1), "") : assert_31
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(source_ok, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(is_aligned, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_402 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_402, UInt<1>(0h1), "") : assert_34
node _T_406 = not(mask)
node _T_407 = and(io.in.a.bits.mask, _T_406)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_408, UInt<1>(0h1), "") : assert_35
node _T_412 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_412 :
node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_415 = and(_T_413, _T_414)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_416 = shr(io.in.a.bits.source, 4)
node _T_417 = eq(_T_416, UInt<1>(0h1))
node _T_418 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_419 = and(_T_417, _T_418)
node _T_420 = leq(uncommonBits_16, UInt<4>(0h8))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_423 = shr(io.in.a.bits.source, 4)
node _T_424 = eq(_T_423, UInt<1>(0h0))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_17, UInt<4>(0h8))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_430 = or(_T_421, _T_422)
node _T_431 = or(_T_430, _T_428)
node _T_432 = or(_T_431, _T_429)
node _T_433 = and(_T_415, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_436 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_437 = and(_T_435, _T_436)
node _T_438 = or(UInt<1>(0h0), _T_437)
node _T_439 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<13>(0h1000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = and(_T_438, _T_443)
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = and(_T_434, _T_445)
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_446, UInt<1>(0h1), "") : assert_36
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(source_ok, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(is_aligned, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_456 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_456, UInt<1>(0h1), "") : assert_39
node _T_460 = eq(io.in.a.bits.mask, mask)
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_460, UInt<1>(0h1), "") : assert_40
node _T_464 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_464 :
node _T_465 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_466 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_467 = and(_T_465, _T_466)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0)
node _T_468 = shr(io.in.a.bits.source, 4)
node _T_469 = eq(_T_468, UInt<1>(0h1))
node _T_470 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_471 = and(_T_469, _T_470)
node _T_472 = leq(uncommonBits_18, UInt<4>(0h8))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0)
node _T_475 = shr(io.in.a.bits.source, 4)
node _T_476 = eq(_T_475, UInt<1>(0h0))
node _T_477 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_478 = and(_T_476, _T_477)
node _T_479 = leq(uncommonBits_19, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_482 = or(_T_473, _T_474)
node _T_483 = or(_T_482, _T_480)
node _T_484 = or(_T_483, _T_481)
node _T_485 = and(_T_467, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_488 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _T_490 = or(UInt<1>(0h0), _T_489)
node _T_491 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_492 = cvt(_T_491)
node _T_493 = and(_T_492, asSInt(UInt<13>(0h1000)))
node _T_494 = asSInt(_T_493)
node _T_495 = eq(_T_494, asSInt(UInt<1>(0h0)))
node _T_496 = and(_T_490, _T_495)
node _T_497 = or(UInt<1>(0h0), _T_496)
node _T_498 = and(_T_486, _T_497)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_498, UInt<1>(0h1), "") : assert_41
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(source_ok, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(is_aligned, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_508 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_508, UInt<1>(0h1), "") : assert_44
node _T_512 = eq(io.in.a.bits.mask, mask)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_512, UInt<1>(0h1), "") : assert_45
node _T_516 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_516 :
node _T_517 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_518 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_519 = and(_T_517, _T_518)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0)
node _T_520 = shr(io.in.a.bits.source, 4)
node _T_521 = eq(_T_520, UInt<1>(0h1))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_20, UInt<4>(0h8))
node _T_525 = and(_T_523, _T_524)
node _T_526 = eq(io.in.a.bits.source, UInt<5>(0h19))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0)
node _T_527 = shr(io.in.a.bits.source, 4)
node _T_528 = eq(_T_527, UInt<1>(0h0))
node _T_529 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_530 = and(_T_528, _T_529)
node _T_531 = leq(uncommonBits_21, UInt<4>(0h8))
node _T_532 = and(_T_530, _T_531)
node _T_533 = eq(io.in.a.bits.source, UInt<4>(0h9))
node _T_534 = or(_T_525, _T_526)
node _T_535 = or(_T_534, _T_532)
node _T_536 = or(_T_535, _T_533)
node _T_537 = and(_T_519, _T_536)
node _T_538 = or(UInt<1>(0h0), _T_537)
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = and(_T_538, _T_549)
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_550, UInt<1>(0h1), "") : assert_46
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(source_ok, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(is_aligned, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_560 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_560, UInt<1>(0h1), "") : assert_49
node _T_564 = eq(io.in.a.bits.mask, mask)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_564, UInt<1>(0h1), "") : assert_50
node _T_568 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_568, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_572 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_572, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0)
node _source_ok_T_16 = shr(io.in.d.bits.source, 4)
node _source_ok_T_17 = eq(_source_ok_T_16, UInt<1>(0h1))
node _source_ok_T_18 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18)
node _source_ok_T_20 = leq(source_ok_uncommonBits_2, UInt<4>(0h8))
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = eq(io.in.d.bits.source, UInt<5>(0h19))
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0)
node _source_ok_T_23 = shr(io.in.d.bits.source, 4)
node _source_ok_T_24 = eq(_source_ok_T_23, UInt<1>(0h0))
node _source_ok_T_25 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_26 = and(_source_ok_T_24, _source_ok_T_25)
node _source_ok_T_27 = leq(source_ok_uncommonBits_3, UInt<4>(0h8))
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = eq(io.in.d.bits.source, UInt<4>(0h9))
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_21
connect _source_ok_WIRE_1[1], _source_ok_T_22
connect _source_ok_WIRE_1[2], _source_ok_T_28
connect _source_ok_WIRE_1[3], _source_ok_T_29
node _source_ok_T_30 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_31, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_576 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_576 :
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(source_ok_1, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_580 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_580, UInt<1>(0h1), "") : assert_54
node _T_584 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_584, UInt<1>(0h1), "") : assert_55
node _T_588 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_588, UInt<1>(0h1), "") : assert_56
node _T_592 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_593 = asUInt(reset)
node _T_594 = eq(_T_593, UInt<1>(0h0))
when _T_594 :
node _T_595 = eq(_T_592, UInt<1>(0h0))
when _T_595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_592, UInt<1>(0h1), "") : assert_57
node _T_596 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_596 :
node _T_597 = asUInt(reset)
node _T_598 = eq(_T_597, UInt<1>(0h0))
when _T_598 :
node _T_599 = eq(source_ok_1, UInt<1>(0h0))
when _T_599 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_600 = asUInt(reset)
node _T_601 = eq(_T_600, UInt<1>(0h0))
when _T_601 :
node _T_602 = eq(sink_ok, UInt<1>(0h0))
when _T_602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_603 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_603, UInt<1>(0h1), "") : assert_60
node _T_607 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(_T_607, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_607, UInt<1>(0h1), "") : assert_61
node _T_611 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_611, UInt<1>(0h1), "") : assert_62
node _T_615 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_616 = asUInt(reset)
node _T_617 = eq(_T_616, UInt<1>(0h0))
when _T_617 :
node _T_618 = eq(_T_615, UInt<1>(0h0))
when _T_618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_615, UInt<1>(0h1), "") : assert_63
node _T_619 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_620 = or(UInt<1>(0h1), _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_620, UInt<1>(0h1), "") : assert_64
node _T_624 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_624 :
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(source_ok_1, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_628 = asUInt(reset)
node _T_629 = eq(_T_628, UInt<1>(0h0))
when _T_629 :
node _T_630 = eq(sink_ok, UInt<1>(0h0))
when _T_630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_631 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(_T_631, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_631, UInt<1>(0h1), "") : assert_67
node _T_635 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_635, UInt<1>(0h1), "") : assert_68
node _T_639 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_639, UInt<1>(0h1), "") : assert_69
node _T_643 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_644 = or(_T_643, io.in.d.bits.corrupt)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_644, UInt<1>(0h1), "") : assert_70
node _T_648 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_649 = or(UInt<1>(0h1), _T_648)
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_649, UInt<1>(0h1), "") : assert_71
node _T_653 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_653 :
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(source_ok_1, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_657 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(_T_657, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_657, UInt<1>(0h1), "") : assert_73
node _T_661 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_661, UInt<1>(0h1), "") : assert_74
node _T_665 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_666 = or(UInt<1>(0h1), _T_665)
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_666, UInt<1>(0h1), "") : assert_75
node _T_670 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_670 :
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(source_ok_1, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_674 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_674, UInt<1>(0h1), "") : assert_77
node _T_678 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_679 = or(_T_678, io.in.d.bits.corrupt)
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_679, UInt<1>(0h1), "") : assert_78
node _T_683 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_684 = or(UInt<1>(0h1), _T_683)
node _T_685 = asUInt(reset)
node _T_686 = eq(_T_685, UInt<1>(0h0))
when _T_686 :
node _T_687 = eq(_T_684, UInt<1>(0h0))
when _T_687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_684, UInt<1>(0h1), "") : assert_79
node _T_688 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_688 :
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(source_ok_1, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_692 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(_T_692, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_692, UInt<1>(0h1), "") : assert_81
node _T_696 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_696, UInt<1>(0h1), "") : assert_82
node _T_700 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_701 = or(UInt<1>(0h1), _T_700)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_701, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<14>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_705 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_705, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_709 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_710 = asUInt(reset)
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(_T_709, UInt<1>(0h0))
when _T_712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_709, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_713 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_714 = asUInt(reset)
node _T_715 = eq(_T_714, UInt<1>(0h0))
when _T_715 :
node _T_716 = eq(_T_713, UInt<1>(0h0))
when _T_716 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_713, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_717 = eq(a_first, UInt<1>(0h0))
node _T_718 = and(io.in.a.valid, _T_717)
when _T_718 :
node _T_719 = eq(io.in.a.bits.opcode, opcode)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_719, UInt<1>(0h1), "") : assert_87
node _T_723 = eq(io.in.a.bits.param, param)
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_723, UInt<1>(0h1), "") : assert_88
node _T_727 = eq(io.in.a.bits.size, size)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_727, UInt<1>(0h1), "") : assert_89
node _T_731 = eq(io.in.a.bits.source, source)
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_731, UInt<1>(0h1), "") : assert_90
node _T_735 = eq(io.in.a.bits.address, address)
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_735, UInt<1>(0h1), "") : assert_91
node _T_739 = and(io.in.a.ready, io.in.a.valid)
node _T_740 = and(_T_739, a_first)
when _T_740 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_741 = eq(d_first, UInt<1>(0h0))
node _T_742 = and(io.in.d.valid, _T_741)
when _T_742 :
node _T_743 = eq(io.in.d.bits.opcode, opcode_1)
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(_T_743, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_743, UInt<1>(0h1), "") : assert_92
node _T_747 = eq(io.in.d.bits.param, param_1)
node _T_748 = asUInt(reset)
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(_T_747, UInt<1>(0h0))
when _T_750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_747, UInt<1>(0h1), "") : assert_93
node _T_751 = eq(io.in.d.bits.size, size_1)
node _T_752 = asUInt(reset)
node _T_753 = eq(_T_752, UInt<1>(0h0))
when _T_753 :
node _T_754 = eq(_T_751, UInt<1>(0h0))
when _T_754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_751, UInt<1>(0h1), "") : assert_94
node _T_755 = eq(io.in.d.bits.source, source_1)
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(_T_755, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_755, UInt<1>(0h1), "") : assert_95
node _T_759 = eq(io.in.d.bits.sink, sink)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_759, UInt<1>(0h1), "") : assert_96
node _T_763 = eq(io.in.d.bits.denied, denied)
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_763, UInt<1>(0h1), "") : assert_97
node _T_767 = and(io.in.d.ready, io.in.d.valid)
node _T_768 = and(_T_767, d_first)
when _T_768 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<26>, clock, reset, UInt<26>(0h0)
regreset inflight_opcodes : UInt<104>, clock, reset, UInt<104>(0h0)
regreset inflight_sizes : UInt<208>, clock, reset, UInt<208>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<26>
connect a_set, UInt<26>(0h0)
wire a_set_wo_ready : UInt<26>
connect a_set_wo_ready, UInt<26>(0h0)
wire a_opcodes_set : UInt<104>
connect a_opcodes_set, UInt<104>(0h0)
wire a_sizes_set : UInt<208>
connect a_sizes_set, UInt<208>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_769 = and(io.in.a.valid, a_first_1)
node _T_770 = and(_T_769, UInt<1>(0h1))
when _T_770 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_771 = and(io.in.a.ready, io.in.a.valid)
node _T_772 = and(_T_771, a_first_1)
node _T_773 = and(_T_772, UInt<1>(0h1))
when _T_773 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_774 = dshr(inflight, io.in.a.bits.source)
node _T_775 = bits(_T_774, 0, 0)
node _T_776 = eq(_T_775, UInt<1>(0h0))
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_776, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<26>
connect d_clr, UInt<26>(0h0)
wire d_clr_wo_ready : UInt<26>
connect d_clr_wo_ready, UInt<26>(0h0)
wire d_opcodes_clr : UInt<104>
connect d_opcodes_clr, UInt<104>(0h0)
wire d_sizes_clr : UInt<208>
connect d_sizes_clr, UInt<208>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_780 = and(io.in.d.valid, d_first_1)
node _T_781 = and(_T_780, UInt<1>(0h1))
node _T_782 = eq(d_release_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_784 = and(io.in.d.ready, io.in.d.valid)
node _T_785 = and(_T_784, d_first_1)
node _T_786 = and(_T_785, UInt<1>(0h1))
node _T_787 = eq(d_release_ack, UInt<1>(0h0))
node _T_788 = and(_T_786, _T_787)
when _T_788 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_789 = and(io.in.d.valid, d_first_1)
node _T_790 = and(_T_789, UInt<1>(0h1))
node _T_791 = eq(d_release_ack, UInt<1>(0h0))
node _T_792 = and(_T_790, _T_791)
when _T_792 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_793 = dshr(inflight, io.in.d.bits.source)
node _T_794 = bits(_T_793, 0, 0)
node _T_795 = or(_T_794, same_cycle_resp)
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_795, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_799 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_800 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_801 = or(_T_799, _T_800)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_801, UInt<1>(0h1), "") : assert_100
node _T_805 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_805, UInt<1>(0h1), "") : assert_101
else :
node _T_809 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_810 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_811 = or(_T_809, _T_810)
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_811, UInt<1>(0h1), "") : assert_102
node _T_815 = eq(io.in.d.bits.size, a_size_lookup)
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(_T_815, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_815, UInt<1>(0h1), "") : assert_103
node _T_819 = and(io.in.d.valid, d_first_1)
node _T_820 = and(_T_819, a_first_1)
node _T_821 = and(_T_820, io.in.a.valid)
node _T_822 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_823 = and(_T_821, _T_822)
node _T_824 = eq(d_release_ack, UInt<1>(0h0))
node _T_825 = and(_T_823, _T_824)
when _T_825 :
node _T_826 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_827 = or(_T_826, io.in.a.ready)
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(_T_827, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_827, UInt<1>(0h1), "") : assert_104
node _T_831 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_832 = orr(a_set_wo_ready)
node _T_833 = eq(_T_832, UInt<1>(0h0))
node _T_834 = or(_T_831, _T_833)
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_834, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_10
node _T_838 = orr(inflight)
node _T_839 = eq(_T_838, UInt<1>(0h0))
node _T_840 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_841 = or(_T_839, _T_840)
node _T_842 = lt(watchdog, plusarg_reader.out)
node _T_843 = or(_T_841, _T_842)
node _T_844 = asUInt(reset)
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(_T_843, UInt<1>(0h0))
when _T_846 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_843, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_847 = and(io.in.a.ready, io.in.a.valid)
node _T_848 = and(io.in.d.ready, io.in.d.valid)
node _T_849 = or(_T_847, _T_848)
when _T_849 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<26>, clock, reset, UInt<26>(0h0)
regreset inflight_opcodes_1 : UInt<104>, clock, reset, UInt<104>(0h0)
regreset inflight_sizes_1 : UInt<208>, clock, reset, UInt<208>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<26>
connect c_set, UInt<26>(0h0)
wire c_set_wo_ready : UInt<26>
connect c_set_wo_ready, UInt<26>(0h0)
wire c_opcodes_set : UInt<104>
connect c_opcodes_set, UInt<104>(0h0)
wire c_sizes_set : UInt<208>
connect c_sizes_set, UInt<208>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_850 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_851 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_852 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_853 = and(_T_851, _T_852)
node _T_854 = and(_T_850, _T_853)
when _T_854 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_855 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_856 = and(_T_855, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_857 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_858 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_859 = and(_T_857, _T_858)
node _T_860 = and(_T_856, _T_859)
when _T_860 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_861 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_862 = bits(_T_861, 0, 0)
node _T_863 = eq(_T_862, UInt<1>(0h0))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_863, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<26>
connect d_clr_1, UInt<26>(0h0)
wire d_clr_wo_ready_1 : UInt<26>
connect d_clr_wo_ready_1, UInt<26>(0h0)
wire d_opcodes_clr_1 : UInt<104>
connect d_opcodes_clr_1, UInt<104>(0h0)
wire d_sizes_clr_1 : UInt<208>
connect d_sizes_clr_1, UInt<208>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_867 = and(io.in.d.valid, d_first_2)
node _T_868 = and(_T_867, UInt<1>(0h1))
node _T_869 = and(_T_868, d_release_ack_1)
when _T_869 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_870 = and(io.in.d.ready, io.in.d.valid)
node _T_871 = and(_T_870, d_first_2)
node _T_872 = and(_T_871, UInt<1>(0h1))
node _T_873 = and(_T_872, d_release_ack_1)
when _T_873 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_874 = and(io.in.d.valid, d_first_2)
node _T_875 = and(_T_874, UInt<1>(0h1))
node _T_876 = and(_T_875, d_release_ack_1)
when _T_876 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_877 = dshr(inflight_1, io.in.d.bits.source)
node _T_878 = bits(_T_877, 0, 0)
node _T_879 = or(_T_878, same_cycle_resp_1)
node _T_880 = asUInt(reset)
node _T_881 = eq(_T_880, UInt<1>(0h0))
when _T_881 :
node _T_882 = eq(_T_879, UInt<1>(0h0))
when _T_882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_879, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_883 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(_T_883, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_883, UInt<1>(0h1), "") : assert_109
else :
node _T_887 = eq(io.in.d.bits.size, c_size_lookup)
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(_T_887, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_887, UInt<1>(0h1), "") : assert_110
node _T_891 = and(io.in.d.valid, d_first_2)
node _T_892 = and(_T_891, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_893 = and(_T_892, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_894 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_895 = and(_T_893, _T_894)
node _T_896 = and(_T_895, d_release_ack_1)
node _T_897 = eq(c_probe_ack, UInt<1>(0h0))
node _T_898 = and(_T_896, _T_897)
when _T_898 :
node _T_899 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<14>(0h0)
connect _WIRE_26.bits.source, UInt<5>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_900 = or(_T_899, _WIRE_27.ready)
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_900, UInt<1>(0h1), "") : assert_111
node _T_904 = orr(c_set_wo_ready)
when _T_904 :
node _T_905 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_905, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_11
node _T_909 = orr(inflight_1)
node _T_910 = eq(_T_909, UInt<1>(0h0))
node _T_911 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_912 = or(_T_910, _T_911)
node _T_913 = lt(watchdog_1, plusarg_reader_1.out)
node _T_914 = or(_T_912, _T_913)
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_914, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<14>(0h0)
connect _WIRE_28.bits.source, UInt<5>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_918 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_919 = and(io.in.d.ready, io.in.d.valid)
node _T_920 = or(_T_918, _T_919)
when _T_920 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_5( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [207:0] c_sizes_set = 208'h0; // @[Monitor.scala:741:34]
wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34]
wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34]
wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31]
wire _source_ok_T_14 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_15 = _source_ok_T_14 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_15 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31]
wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_31 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_847 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_847; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_847; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_920 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_920; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_920; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_920; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [25:0] inflight; // @[Monitor.scala:614:27]
reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [207:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [25:0] a_set; // @[Monitor.scala:626:34]
wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [207:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [207:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [207:0] _a_size_lookup_T_6 = {200'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [207:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[207:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_773 = _T_847 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_773 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_773 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_773 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_773 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_773 ? _a_sizes_set_T_1[207:0] : 208'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [25:0] d_clr; // @[Monitor.scala:664:34]
wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [207:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_819 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_819 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_788 = _T_920 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_788 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_788 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_788 ? _d_sizes_clr_T_5[207:0] : 208'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [25:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [103:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [207:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [207:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [207:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [25:0] inflight_1; // @[Monitor.scala:726:35]
wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [207:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [207:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [207:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [207:0] _c_size_lookup_T_6 = {200'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [207:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[207:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [25:0] d_clr_1; // @[Monitor.scala:774:34]
wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [207:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_891 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_891 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_873 = _T_920 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_873 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_873 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_873 ? _d_sizes_clr_T_11[207:0] : 208'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [207:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [207:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_3 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_3
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_3( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_3 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_232 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_232( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_52 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_52
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_52( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_52 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e8_s24_3 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst divSqrtRawFN of DivSqrtRawFN_small_e8_s24_3
connect divSqrtRawFN.clock, clock
connect divSqrtRawFN.reset, reset
connect io.inReady, divSqrtRawFN.io.inReady
connect divSqrtRawFN.io.inValid, io.inValid
connect divSqrtRawFN.io.sqrtOp, io.sqrtOp
node divSqrtRawFN_io_a_exp = bits(io.a, 31, 23)
node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 8, 6)
node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 8, 7)
node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 6, 6)
node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T)
connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1
node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 6, 6)
node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1)
connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2
connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero
node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T
node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp)
connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T
node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T)
node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2)
connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3
connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig
connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp
connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign
connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero
connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf
connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN
node divSqrtRawFN_io_b_exp = bits(io.b, 31, 23)
node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 8, 6)
node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 8, 7)
node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 6, 6)
node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T)
connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1
node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 6, 6)
node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1)
connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2
connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero
node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T
node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp)
connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T
node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T)
node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2)
connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3
connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig
connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp
connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign
connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero
connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf
connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN
connect divSqrtRawFN.io.roundingMode, io.roundingMode
connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div
connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt
connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut
connect io.invalidExc, divSqrtRawFN.io.invalidExc
connect io.infiniteExc, divSqrtRawFN.io.infiniteExc
connect io.rawOut, divSqrtRawFN.io.rawOut | module DivSqrtRecFMToRaw_small_e8_s24_3( // @[DivSqrtRecFN_small.scala:422:5]
input clock, // @[DivSqrtRecFN_small.scala:422:5]
input reset, // @[DivSqrtRecFN_small.scala:422:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:426:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:426:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16]
input [32:0] io_a, // @[DivSqrtRecFN_small.scala:426:16]
input [32:0] io_b, // @[DivSqrtRecFN_small.scala:426:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16]
output [9:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16]
output [26:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5]
wire [32:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5]
wire [32:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [9:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [26:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [8:0] divSqrtRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] divSqrtRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
DivSqrtRawFN_small_e8_s24_3 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_rawOutValid_div (io_rawOutValid_div_0),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),
.io_roundingModeOut (io_roundingModeOut_0),
.io_invalidExc (io_invalidExc_0),
.io_infiniteExc (io_infiniteExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (io_rawOut_sig_0)
); // @[DivSqrtRecFN_small.scala:446:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_28 = shr(io.in.a.bits.source, 5)
node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0))
node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f))
node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_34 = shr(io.in.a.bits.source, 5)
node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1))
node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f))
node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_40 = shr(io.in.a.bits.source, 5)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_46 = shr(io.in.a.bits.source, 5)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_52 = shr(io.in.a.bits.source, 5)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_58 = shr(io.in.a.bits.source, 5)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_64 = shr(io.in.a.bits.source, 5)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_70 = shr(io.in.a.bits.source, 5)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE : UInt<1>[17]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_33
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_45
connect _source_ok_WIRE[11], _source_ok_T_51
connect _source_ok_WIRE[12], _source_ok_T_57
connect _source_ok_WIRE[13], _source_ok_T_63
connect _source_ok_WIRE[14], _source_ok_T_69
connect _source_ok_WIRE[15], _source_ok_T_75
connect _source_ok_WIRE[16], _source_ok_T_76
node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15])
node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<7>(0h40))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<7>(0h41))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<7>(0h42))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<7>(0h43))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_88 = shr(io.in.a.bits.source, 5)
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_101 = shr(io.in.a.bits.source, 5)
node _T_102 = eq(_T_101, UInt<1>(0h1))
node _T_103 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_104 = and(_T_102, _T_103)
node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_114 = shr(io.in.a.bits.source, 5)
node _T_115 = eq(_T_114, UInt<2>(0h2))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_127 = shr(io.in.a.bits.source, 5)
node _T_128 = eq(_T_127, UInt<2>(0h3))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(_T_132, UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = or(_T_133, _T_138)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_140 = shr(io.in.a.bits.source, 5)
node _T_141 = eq(_T_140, UInt<3>(0h4))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = or(_T_146, _T_151)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_153 = shr(io.in.a.bits.source, 5)
node _T_154 = eq(_T_153, UInt<3>(0h5))
node _T_155 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_156 = and(_T_154, _T_155)
node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(_T_158, UInt<1>(0h0))
node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_161 = cvt(_T_160)
node _T_162 = and(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = asSInt(_T_162)
node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = or(_T_159, _T_164)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_166 = shr(io.in.a.bits.source, 5)
node _T_167 = eq(_T_166, UInt<3>(0h6))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = or(_T_172, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_179 = shr(io.in.a.bits.source, 5)
node _T_180 = eq(_T_179, UInt<3>(0h7))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = and(_T_11, _T_24)
node _T_201 = and(_T_200, _T_37)
node _T_202 = and(_T_201, _T_50)
node _T_203 = and(_T_202, _T_63)
node _T_204 = and(_T_203, _T_71)
node _T_205 = and(_T_204, _T_79)
node _T_206 = and(_T_205, _T_87)
node _T_207 = and(_T_206, _T_100)
node _T_208 = and(_T_207, _T_113)
node _T_209 = and(_T_208, _T_126)
node _T_210 = and(_T_209, _T_139)
node _T_211 = and(_T_210, _T_152)
node _T_212 = and(_T_211, _T_165)
node _T_213 = and(_T_212, _T_178)
node _T_214 = and(_T_213, _T_191)
node _T_215 = and(_T_214, _T_199)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_215, UInt<1>(0h1), "") : assert_1
node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_219 :
node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_224 = shr(io.in.a.bits.source, 2)
node _T_225 = eq(_T_224, UInt<7>(0h40))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_229 = and(_T_227, _T_228)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_230 = shr(io.in.a.bits.source, 2)
node _T_231 = eq(_T_230, UInt<7>(0h41))
node _T_232 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_233 = and(_T_231, _T_232)
node _T_234 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_236 = shr(io.in.a.bits.source, 2)
node _T_237 = eq(_T_236, UInt<7>(0h42))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_242 = shr(io.in.a.bits.source, 2)
node _T_243 = eq(_T_242, UInt<7>(0h43))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_251 = shr(io.in.a.bits.source, 5)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_257 = shr(io.in.a.bits.source, 5)
node _T_258 = eq(_T_257, UInt<1>(0h1))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_263 = shr(io.in.a.bits.source, 5)
node _T_264 = eq(_T_263, UInt<2>(0h2))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f))
node _T_268 = and(_T_266, _T_267)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_269 = shr(io.in.a.bits.source, 5)
node _T_270 = eq(_T_269, UInt<2>(0h3))
node _T_271 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_272 = and(_T_270, _T_271)
node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f))
node _T_274 = and(_T_272, _T_273)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_275 = shr(io.in.a.bits.source, 5)
node _T_276 = eq(_T_275, UInt<3>(0h4))
node _T_277 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_278 = and(_T_276, _T_277)
node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f))
node _T_280 = and(_T_278, _T_279)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_281 = shr(io.in.a.bits.source, 5)
node _T_282 = eq(_T_281, UInt<3>(0h5))
node _T_283 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_284 = and(_T_282, _T_283)
node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f))
node _T_286 = and(_T_284, _T_285)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_287 = shr(io.in.a.bits.source, 5)
node _T_288 = eq(_T_287, UInt<3>(0h6))
node _T_289 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_290 = and(_T_288, _T_289)
node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f))
node _T_292 = and(_T_290, _T_291)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_293 = shr(io.in.a.bits.source, 5)
node _T_294 = eq(_T_293, UInt<3>(0h7))
node _T_295 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_296 = and(_T_294, _T_295)
node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_300 = or(_T_223, _T_229)
node _T_301 = or(_T_300, _T_235)
node _T_302 = or(_T_301, _T_241)
node _T_303 = or(_T_302, _T_247)
node _T_304 = or(_T_303, _T_248)
node _T_305 = or(_T_304, _T_249)
node _T_306 = or(_T_305, _T_250)
node _T_307 = or(_T_306, _T_256)
node _T_308 = or(_T_307, _T_262)
node _T_309 = or(_T_308, _T_268)
node _T_310 = or(_T_309, _T_274)
node _T_311 = or(_T_310, _T_280)
node _T_312 = or(_T_311, _T_286)
node _T_313 = or(_T_312, _T_292)
node _T_314 = or(_T_313, _T_298)
node _T_315 = or(_T_314, _T_299)
node _T_316 = and(_T_222, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<19>(0h40000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = or(_T_323, _T_328)
node _T_335 = or(_T_334, _T_333)
node _T_336 = and(_T_318, _T_335)
node _T_337 = or(UInt<1>(0h0), _T_336)
node _T_338 = and(_T_317, _T_337)
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_338, UInt<1>(0h1), "") : assert_2
node _T_342 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<7>(0h40))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<7>(0h41))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_354 = and(_T_352, _T_353)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_355 = shr(io.in.a.bits.source, 2)
node _T_356 = eq(_T_355, UInt<7>(0h42))
node _T_357 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_358 = and(_T_356, _T_357)
node _T_359 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_360 = and(_T_358, _T_359)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_361 = shr(io.in.a.bits.source, 2)
node _T_362 = eq(_T_361, UInt<7>(0h43))
node _T_363 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_364 = and(_T_362, _T_363)
node _T_365 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_368 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_369 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_370 = shr(io.in.a.bits.source, 5)
node _T_371 = eq(_T_370, UInt<1>(0h0))
node _T_372 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_373 = and(_T_371, _T_372)
node _T_374 = leq(uncommonBits_28, UInt<5>(0h1f))
node _T_375 = and(_T_373, _T_374)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_376 = shr(io.in.a.bits.source, 5)
node _T_377 = eq(_T_376, UInt<1>(0h1))
node _T_378 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_379 = and(_T_377, _T_378)
node _T_380 = leq(uncommonBits_29, UInt<5>(0h1f))
node _T_381 = and(_T_379, _T_380)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_382 = shr(io.in.a.bits.source, 5)
node _T_383 = eq(_T_382, UInt<2>(0h2))
node _T_384 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_385 = and(_T_383, _T_384)
node _T_386 = leq(uncommonBits_30, UInt<5>(0h1f))
node _T_387 = and(_T_385, _T_386)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_388 = shr(io.in.a.bits.source, 5)
node _T_389 = eq(_T_388, UInt<2>(0h3))
node _T_390 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_391 = and(_T_389, _T_390)
node _T_392 = leq(uncommonBits_31, UInt<5>(0h1f))
node _T_393 = and(_T_391, _T_392)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_394 = shr(io.in.a.bits.source, 5)
node _T_395 = eq(_T_394, UInt<3>(0h4))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_32, UInt<5>(0h1f))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_400 = shr(io.in.a.bits.source, 5)
node _T_401 = eq(_T_400, UInt<3>(0h5))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_33, UInt<5>(0h1f))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_406 = shr(io.in.a.bits.source, 5)
node _T_407 = eq(_T_406, UInt<3>(0h6))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_34, UInt<5>(0h1f))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_412 = shr(io.in.a.bits.source, 5)
node _T_413 = eq(_T_412, UInt<3>(0h7))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_35, UInt<5>(0h1f))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE : UInt<1>[17]
connect _WIRE[0], _T_342
connect _WIRE[1], _T_348
connect _WIRE[2], _T_354
connect _WIRE[3], _T_360
connect _WIRE[4], _T_366
connect _WIRE[5], _T_367
connect _WIRE[6], _T_368
connect _WIRE[7], _T_369
connect _WIRE[8], _T_375
connect _WIRE[9], _T_381
connect _WIRE[10], _T_387
connect _WIRE[11], _T_393
connect _WIRE[12], _T_399
connect _WIRE[13], _T_405
connect _WIRE[14], _T_411
connect _WIRE[15], _T_417
connect _WIRE[16], _T_418
node _T_419 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_420 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE[5], _T_419, UInt<1>(0h0))
node _T_426 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_428 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_429 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_431 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_432 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_433 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_434 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_435 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_437 = or(_T_420, _T_421)
node _T_438 = or(_T_437, _T_422)
node _T_439 = or(_T_438, _T_423)
node _T_440 = or(_T_439, _T_424)
node _T_441 = or(_T_440, _T_425)
node _T_442 = or(_T_441, _T_426)
node _T_443 = or(_T_442, _T_427)
node _T_444 = or(_T_443, _T_428)
node _T_445 = or(_T_444, _T_429)
node _T_446 = or(_T_445, _T_430)
node _T_447 = or(_T_446, _T_431)
node _T_448 = or(_T_447, _T_432)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_434)
node _T_451 = or(_T_450, _T_435)
node _T_452 = or(_T_451, _T_436)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_452
node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_455 = and(_T_453, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<13>(0h1000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<19>(0h40000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = or(_T_461, _T_466)
node _T_473 = or(_T_472, _T_471)
node _T_474 = and(_T_456, _T_473)
node _T_475 = or(UInt<1>(0h0), _T_474)
node _T_476 = and(_WIRE_1, _T_475)
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_476, UInt<1>(0h1), "") : assert_3
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(source_ok, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_483 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(_T_483, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_483, UInt<1>(0h1), "") : assert_5
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(is_aligned, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_490 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_490, UInt<1>(0h1), "") : assert_7
node _T_494 = not(io.in.a.bits.mask)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_495, UInt<1>(0h1), "") : assert_8
node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_499, UInt<1>(0h1), "") : assert_9
node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_503 :
node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<7>(0h40))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_514 = shr(io.in.a.bits.source, 2)
node _T_515 = eq(_T_514, UInt<7>(0h41))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_519 = and(_T_517, _T_518)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_520 = shr(io.in.a.bits.source, 2)
node _T_521 = eq(_T_520, UInt<7>(0h42))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_525 = and(_T_523, _T_524)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_526 = shr(io.in.a.bits.source, 2)
node _T_527 = eq(_T_526, UInt<7>(0h43))
node _T_528 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_529 = and(_T_527, _T_528)
node _T_530 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_531 = and(_T_529, _T_530)
node _T_532 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_533 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_534 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_535 = shr(io.in.a.bits.source, 5)
node _T_536 = eq(_T_535, UInt<1>(0h0))
node _T_537 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_538 = and(_T_536, _T_537)
node _T_539 = leq(uncommonBits_40, UInt<5>(0h1f))
node _T_540 = and(_T_538, _T_539)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_541 = shr(io.in.a.bits.source, 5)
node _T_542 = eq(_T_541, UInt<1>(0h1))
node _T_543 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_544 = and(_T_542, _T_543)
node _T_545 = leq(uncommonBits_41, UInt<5>(0h1f))
node _T_546 = and(_T_544, _T_545)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_547 = shr(io.in.a.bits.source, 5)
node _T_548 = eq(_T_547, UInt<2>(0h2))
node _T_549 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_550 = and(_T_548, _T_549)
node _T_551 = leq(uncommonBits_42, UInt<5>(0h1f))
node _T_552 = and(_T_550, _T_551)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_553 = shr(io.in.a.bits.source, 5)
node _T_554 = eq(_T_553, UInt<2>(0h3))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_43, UInt<5>(0h1f))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0)
node _T_559 = shr(io.in.a.bits.source, 5)
node _T_560 = eq(_T_559, UInt<3>(0h4))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_44, UInt<5>(0h1f))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0)
node _T_565 = shr(io.in.a.bits.source, 5)
node _T_566 = eq(_T_565, UInt<3>(0h5))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_45, UInt<5>(0h1f))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0)
node _T_571 = shr(io.in.a.bits.source, 5)
node _T_572 = eq(_T_571, UInt<3>(0h6))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_46, UInt<5>(0h1f))
node _T_576 = and(_T_574, _T_575)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0)
node _T_577 = shr(io.in.a.bits.source, 5)
node _T_578 = eq(_T_577, UInt<3>(0h7))
node _T_579 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_580 = and(_T_578, _T_579)
node _T_581 = leq(uncommonBits_47, UInt<5>(0h1f))
node _T_582 = and(_T_580, _T_581)
node _T_583 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_584 = or(_T_507, _T_513)
node _T_585 = or(_T_584, _T_519)
node _T_586 = or(_T_585, _T_525)
node _T_587 = or(_T_586, _T_531)
node _T_588 = or(_T_587, _T_532)
node _T_589 = or(_T_588, _T_533)
node _T_590 = or(_T_589, _T_534)
node _T_591 = or(_T_590, _T_540)
node _T_592 = or(_T_591, _T_546)
node _T_593 = or(_T_592, _T_552)
node _T_594 = or(_T_593, _T_558)
node _T_595 = or(_T_594, _T_564)
node _T_596 = or(_T_595, _T_570)
node _T_597 = or(_T_596, _T_576)
node _T_598 = or(_T_597, _T_582)
node _T_599 = or(_T_598, _T_583)
node _T_600 = and(_T_506, _T_599)
node _T_601 = or(UInt<1>(0h0), _T_600)
node _T_602 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_603 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_604 = cvt(_T_603)
node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000)))
node _T_606 = asSInt(_T_605)
node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0)))
node _T_608 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_609 = cvt(_T_608)
node _T_610 = and(_T_609, asSInt(UInt<13>(0h1000)))
node _T_611 = asSInt(_T_610)
node _T_612 = eq(_T_611, asSInt(UInt<1>(0h0)))
node _T_613 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<19>(0h40000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = or(_T_607, _T_612)
node _T_619 = or(_T_618, _T_617)
node _T_620 = and(_T_602, _T_619)
node _T_621 = or(UInt<1>(0h0), _T_620)
node _T_622 = and(_T_601, _T_621)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_622, UInt<1>(0h1), "") : assert_10
node _T_626 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_627 = shr(io.in.a.bits.source, 2)
node _T_628 = eq(_T_627, UInt<7>(0h40))
node _T_629 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_630 = and(_T_628, _T_629)
node _T_631 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_632 = and(_T_630, _T_631)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_633 = shr(io.in.a.bits.source, 2)
node _T_634 = eq(_T_633, UInt<7>(0h41))
node _T_635 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_636 = and(_T_634, _T_635)
node _T_637 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_638 = and(_T_636, _T_637)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_639 = shr(io.in.a.bits.source, 2)
node _T_640 = eq(_T_639, UInt<7>(0h42))
node _T_641 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_642 = and(_T_640, _T_641)
node _T_643 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_644 = and(_T_642, _T_643)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<7>(0h43))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_652 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_653 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_654 = shr(io.in.a.bits.source, 5)
node _T_655 = eq(_T_654, UInt<1>(0h0))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_52, UInt<5>(0h1f))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_660 = shr(io.in.a.bits.source, 5)
node _T_661 = eq(_T_660, UInt<1>(0h1))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_53, UInt<5>(0h1f))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_666 = shr(io.in.a.bits.source, 5)
node _T_667 = eq(_T_666, UInt<2>(0h2))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_54, UInt<5>(0h1f))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_672 = shr(io.in.a.bits.source, 5)
node _T_673 = eq(_T_672, UInt<2>(0h3))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_55, UInt<5>(0h1f))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0)
node _T_678 = shr(io.in.a.bits.source, 5)
node _T_679 = eq(_T_678, UInt<3>(0h4))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_56, UInt<5>(0h1f))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0)
node _T_684 = shr(io.in.a.bits.source, 5)
node _T_685 = eq(_T_684, UInt<3>(0h5))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_57, UInt<5>(0h1f))
node _T_689 = and(_T_687, _T_688)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_690 = shr(io.in.a.bits.source, 5)
node _T_691 = eq(_T_690, UInt<3>(0h6))
node _T_692 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_693 = and(_T_691, _T_692)
node _T_694 = leq(uncommonBits_58, UInt<5>(0h1f))
node _T_695 = and(_T_693, _T_694)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_696 = shr(io.in.a.bits.source, 5)
node _T_697 = eq(_T_696, UInt<3>(0h7))
node _T_698 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_699 = and(_T_697, _T_698)
node _T_700 = leq(uncommonBits_59, UInt<5>(0h1f))
node _T_701 = and(_T_699, _T_700)
node _T_702 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE_2 : UInt<1>[17]
connect _WIRE_2[0], _T_626
connect _WIRE_2[1], _T_632
connect _WIRE_2[2], _T_638
connect _WIRE_2[3], _T_644
connect _WIRE_2[4], _T_650
connect _WIRE_2[5], _T_651
connect _WIRE_2[6], _T_652
connect _WIRE_2[7], _T_653
connect _WIRE_2[8], _T_659
connect _WIRE_2[9], _T_665
connect _WIRE_2[10], _T_671
connect _WIRE_2[11], _T_677
connect _WIRE_2[12], _T_683
connect _WIRE_2[13], _T_689
connect _WIRE_2[14], _T_695
connect _WIRE_2[15], _T_701
connect _WIRE_2[16], _T_702
node _T_703 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_704 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_708 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_709 = mux(_WIRE_2[5], _T_703, UInt<1>(0h0))
node _T_710 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_711 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_712 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_713 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_714 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_715 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_716 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_717 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_720 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_721 = or(_T_704, _T_705)
node _T_722 = or(_T_721, _T_706)
node _T_723 = or(_T_722, _T_707)
node _T_724 = or(_T_723, _T_708)
node _T_725 = or(_T_724, _T_709)
node _T_726 = or(_T_725, _T_710)
node _T_727 = or(_T_726, _T_711)
node _T_728 = or(_T_727, _T_712)
node _T_729 = or(_T_728, _T_713)
node _T_730 = or(_T_729, _T_714)
node _T_731 = or(_T_730, _T_715)
node _T_732 = or(_T_731, _T_716)
node _T_733 = or(_T_732, _T_717)
node _T_734 = or(_T_733, _T_718)
node _T_735 = or(_T_734, _T_719)
node _T_736 = or(_T_735, _T_720)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_736
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<19>(0h40000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_745, _T_750)
node _T_757 = or(_T_756, _T_755)
node _T_758 = and(_T_740, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = and(_WIRE_3, _T_759)
node _T_761 = asUInt(reset)
node _T_762 = eq(_T_761, UInt<1>(0h0))
when _T_762 :
node _T_763 = eq(_T_760, UInt<1>(0h0))
when _T_763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_760, UInt<1>(0h1), "") : assert_11
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(source_ok, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_767 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_767, UInt<1>(0h1), "") : assert_13
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_774 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_774, UInt<1>(0h1), "") : assert_15
node _T_778 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_778, UInt<1>(0h1), "") : assert_16
node _T_782 = not(io.in.a.bits.mask)
node _T_783 = eq(_T_782, UInt<1>(0h0))
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(_T_783, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_783, UInt<1>(0h1), "") : assert_17
node _T_787 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_787, UInt<1>(0h1), "") : assert_18
node _T_791 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_791 :
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_794 = and(_T_792, _T_793)
node _T_795 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_796 = shr(io.in.a.bits.source, 2)
node _T_797 = eq(_T_796, UInt<7>(0h40))
node _T_798 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_799 = and(_T_797, _T_798)
node _T_800 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_802 = shr(io.in.a.bits.source, 2)
node _T_803 = eq(_T_802, UInt<7>(0h41))
node _T_804 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_805 = and(_T_803, _T_804)
node _T_806 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_807 = and(_T_805, _T_806)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<7>(0h42))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<7>(0h43))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _T_820 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_821 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_822 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_823 = shr(io.in.a.bits.source, 5)
node _T_824 = eq(_T_823, UInt<1>(0h0))
node _T_825 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_826 = and(_T_824, _T_825)
node _T_827 = leq(uncommonBits_64, UInt<5>(0h1f))
node _T_828 = and(_T_826, _T_827)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_829 = shr(io.in.a.bits.source, 5)
node _T_830 = eq(_T_829, UInt<1>(0h1))
node _T_831 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_832 = and(_T_830, _T_831)
node _T_833 = leq(uncommonBits_65, UInt<5>(0h1f))
node _T_834 = and(_T_832, _T_833)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0)
node _T_835 = shr(io.in.a.bits.source, 5)
node _T_836 = eq(_T_835, UInt<2>(0h2))
node _T_837 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_838 = and(_T_836, _T_837)
node _T_839 = leq(uncommonBits_66, UInt<5>(0h1f))
node _T_840 = and(_T_838, _T_839)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0)
node _T_841 = shr(io.in.a.bits.source, 5)
node _T_842 = eq(_T_841, UInt<2>(0h3))
node _T_843 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_844 = and(_T_842, _T_843)
node _T_845 = leq(uncommonBits_67, UInt<5>(0h1f))
node _T_846 = and(_T_844, _T_845)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0)
node _T_847 = shr(io.in.a.bits.source, 5)
node _T_848 = eq(_T_847, UInt<3>(0h4))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_68, UInt<5>(0h1f))
node _T_852 = and(_T_850, _T_851)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0)
node _T_853 = shr(io.in.a.bits.source, 5)
node _T_854 = eq(_T_853, UInt<3>(0h5))
node _T_855 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_856 = and(_T_854, _T_855)
node _T_857 = leq(uncommonBits_69, UInt<5>(0h1f))
node _T_858 = and(_T_856, _T_857)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0)
node _T_859 = shr(io.in.a.bits.source, 5)
node _T_860 = eq(_T_859, UInt<3>(0h6))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_70, UInt<5>(0h1f))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0)
node _T_865 = shr(io.in.a.bits.source, 5)
node _T_866 = eq(_T_865, UInt<3>(0h7))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_71, UInt<5>(0h1f))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_872 = or(_T_795, _T_801)
node _T_873 = or(_T_872, _T_807)
node _T_874 = or(_T_873, _T_813)
node _T_875 = or(_T_874, _T_819)
node _T_876 = or(_T_875, _T_820)
node _T_877 = or(_T_876, _T_821)
node _T_878 = or(_T_877, _T_822)
node _T_879 = or(_T_878, _T_828)
node _T_880 = or(_T_879, _T_834)
node _T_881 = or(_T_880, _T_840)
node _T_882 = or(_T_881, _T_846)
node _T_883 = or(_T_882, _T_852)
node _T_884 = or(_T_883, _T_858)
node _T_885 = or(_T_884, _T_864)
node _T_886 = or(_T_885, _T_870)
node _T_887 = or(_T_886, _T_871)
node _T_888 = and(_T_794, _T_887)
node _T_889 = or(UInt<1>(0h0), _T_888)
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_889, UInt<1>(0h1), "") : assert_19
node _T_893 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_894 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_895 = and(_T_893, _T_894)
node _T_896 = or(UInt<1>(0h0), _T_895)
node _T_897 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_898 = cvt(_T_897)
node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000)))
node _T_900 = asSInt(_T_899)
node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0)))
node _T_902 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_903 = cvt(_T_902)
node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000)))
node _T_905 = asSInt(_T_904)
node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0)))
node _T_907 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_908 = cvt(_T_907)
node _T_909 = and(_T_908, asSInt(UInt<19>(0h40000)))
node _T_910 = asSInt(_T_909)
node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0)))
node _T_912 = or(_T_901, _T_906)
node _T_913 = or(_T_912, _T_911)
node _T_914 = and(_T_896, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_915, UInt<1>(0h1), "") : assert_20
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(source_ok, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_925 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_925, UInt<1>(0h1), "") : assert_23
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_929, UInt<1>(0h1), "") : assert_24
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_933, UInt<1>(0h1), "") : assert_25
node _T_937 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_937 :
node _T_938 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_939 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_940 = and(_T_938, _T_939)
node _T_941 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_942 = shr(io.in.a.bits.source, 2)
node _T_943 = eq(_T_942, UInt<7>(0h40))
node _T_944 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_945 = and(_T_943, _T_944)
node _T_946 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_947 = and(_T_945, _T_946)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_948 = shr(io.in.a.bits.source, 2)
node _T_949 = eq(_T_948, UInt<7>(0h41))
node _T_950 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_951 = and(_T_949, _T_950)
node _T_952 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_953 = and(_T_951, _T_952)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_954 = shr(io.in.a.bits.source, 2)
node _T_955 = eq(_T_954, UInt<7>(0h42))
node _T_956 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_957 = and(_T_955, _T_956)
node _T_958 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_959 = and(_T_957, _T_958)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_960 = shr(io.in.a.bits.source, 2)
node _T_961 = eq(_T_960, UInt<7>(0h43))
node _T_962 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_963 = and(_T_961, _T_962)
node _T_964 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_965 = and(_T_963, _T_964)
node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_967 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_968 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0)
node _T_969 = shr(io.in.a.bits.source, 5)
node _T_970 = eq(_T_969, UInt<1>(0h0))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_76, UInt<5>(0h1f))
node _T_974 = and(_T_972, _T_973)
node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0)
node _T_975 = shr(io.in.a.bits.source, 5)
node _T_976 = eq(_T_975, UInt<1>(0h1))
node _T_977 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_978 = and(_T_976, _T_977)
node _T_979 = leq(uncommonBits_77, UInt<5>(0h1f))
node _T_980 = and(_T_978, _T_979)
node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0)
node _T_981 = shr(io.in.a.bits.source, 5)
node _T_982 = eq(_T_981, UInt<2>(0h2))
node _T_983 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_984 = and(_T_982, _T_983)
node _T_985 = leq(uncommonBits_78, UInt<5>(0h1f))
node _T_986 = and(_T_984, _T_985)
node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0)
node _T_987 = shr(io.in.a.bits.source, 5)
node _T_988 = eq(_T_987, UInt<2>(0h3))
node _T_989 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_990 = and(_T_988, _T_989)
node _T_991 = leq(uncommonBits_79, UInt<5>(0h1f))
node _T_992 = and(_T_990, _T_991)
node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0)
node _T_993 = shr(io.in.a.bits.source, 5)
node _T_994 = eq(_T_993, UInt<3>(0h4))
node _T_995 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_996 = and(_T_994, _T_995)
node _T_997 = leq(uncommonBits_80, UInt<5>(0h1f))
node _T_998 = and(_T_996, _T_997)
node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0)
node _T_999 = shr(io.in.a.bits.source, 5)
node _T_1000 = eq(_T_999, UInt<3>(0h5))
node _T_1001 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1002 = and(_T_1000, _T_1001)
node _T_1003 = leq(uncommonBits_81, UInt<5>(0h1f))
node _T_1004 = and(_T_1002, _T_1003)
node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0)
node _T_1005 = shr(io.in.a.bits.source, 5)
node _T_1006 = eq(_T_1005, UInt<3>(0h6))
node _T_1007 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = leq(uncommonBits_82, UInt<5>(0h1f))
node _T_1010 = and(_T_1008, _T_1009)
node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0)
node _T_1011 = shr(io.in.a.bits.source, 5)
node _T_1012 = eq(_T_1011, UInt<3>(0h7))
node _T_1013 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1014 = and(_T_1012, _T_1013)
node _T_1015 = leq(uncommonBits_83, UInt<5>(0h1f))
node _T_1016 = and(_T_1014, _T_1015)
node _T_1017 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1018 = or(_T_941, _T_947)
node _T_1019 = or(_T_1018, _T_953)
node _T_1020 = or(_T_1019, _T_959)
node _T_1021 = or(_T_1020, _T_965)
node _T_1022 = or(_T_1021, _T_966)
node _T_1023 = or(_T_1022, _T_967)
node _T_1024 = or(_T_1023, _T_968)
node _T_1025 = or(_T_1024, _T_974)
node _T_1026 = or(_T_1025, _T_980)
node _T_1027 = or(_T_1026, _T_986)
node _T_1028 = or(_T_1027, _T_992)
node _T_1029 = or(_T_1028, _T_998)
node _T_1030 = or(_T_1029, _T_1004)
node _T_1031 = or(_T_1030, _T_1010)
node _T_1032 = or(_T_1031, _T_1016)
node _T_1033 = or(_T_1032, _T_1017)
node _T_1034 = and(_T_940, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_1034)
node _T_1036 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1037 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1038 = and(_T_1036, _T_1037)
node _T_1039 = or(UInt<1>(0h0), _T_1038)
node _T_1040 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1041 = cvt(_T_1040)
node _T_1042 = and(_T_1041, asSInt(UInt<13>(0h1000)))
node _T_1043 = asSInt(_T_1042)
node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0)))
node _T_1045 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1046 = cvt(_T_1045)
node _T_1047 = and(_T_1046, asSInt(UInt<13>(0h1000)))
node _T_1048 = asSInt(_T_1047)
node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0)))
node _T_1050 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1051 = cvt(_T_1050)
node _T_1052 = and(_T_1051, asSInt(UInt<19>(0h40000)))
node _T_1053 = asSInt(_T_1052)
node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0)))
node _T_1055 = or(_T_1044, _T_1049)
node _T_1056 = or(_T_1055, _T_1054)
node _T_1057 = and(_T_1039, _T_1056)
node _T_1058 = or(UInt<1>(0h0), _T_1057)
node _T_1059 = and(_T_1035, _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_26
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(source_ok, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(is_aligned, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1069 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_29
node _T_1073 = eq(io.in.a.bits.mask, mask)
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_T_1073, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1073, UInt<1>(0h1), "") : assert_30
node _T_1077 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1077 :
node _T_1078 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1079 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1082 = shr(io.in.a.bits.source, 2)
node _T_1083 = eq(_T_1082, UInt<7>(0h40))
node _T_1084 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1085 = and(_T_1083, _T_1084)
node _T_1086 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1087 = and(_T_1085, _T_1086)
node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1088 = shr(io.in.a.bits.source, 2)
node _T_1089 = eq(_T_1088, UInt<7>(0h41))
node _T_1090 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1091 = and(_T_1089, _T_1090)
node _T_1092 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1093 = and(_T_1091, _T_1092)
node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1094 = shr(io.in.a.bits.source, 2)
node _T_1095 = eq(_T_1094, UInt<7>(0h42))
node _T_1096 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1097 = and(_T_1095, _T_1096)
node _T_1098 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1099 = and(_T_1097, _T_1098)
node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1100 = shr(io.in.a.bits.source, 2)
node _T_1101 = eq(_T_1100, UInt<7>(0h43))
node _T_1102 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1103 = and(_T_1101, _T_1102)
node _T_1104 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1105 = and(_T_1103, _T_1104)
node _T_1106 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1107 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1108 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0)
node _T_1109 = shr(io.in.a.bits.source, 5)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
node _T_1111 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1112 = and(_T_1110, _T_1111)
node _T_1113 = leq(uncommonBits_88, UInt<5>(0h1f))
node _T_1114 = and(_T_1112, _T_1113)
node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0)
node _T_1115 = shr(io.in.a.bits.source, 5)
node _T_1116 = eq(_T_1115, UInt<1>(0h1))
node _T_1117 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1118 = and(_T_1116, _T_1117)
node _T_1119 = leq(uncommonBits_89, UInt<5>(0h1f))
node _T_1120 = and(_T_1118, _T_1119)
node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0)
node _T_1121 = shr(io.in.a.bits.source, 5)
node _T_1122 = eq(_T_1121, UInt<2>(0h2))
node _T_1123 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1124 = and(_T_1122, _T_1123)
node _T_1125 = leq(uncommonBits_90, UInt<5>(0h1f))
node _T_1126 = and(_T_1124, _T_1125)
node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0)
node _T_1127 = shr(io.in.a.bits.source, 5)
node _T_1128 = eq(_T_1127, UInt<2>(0h3))
node _T_1129 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1130 = and(_T_1128, _T_1129)
node _T_1131 = leq(uncommonBits_91, UInt<5>(0h1f))
node _T_1132 = and(_T_1130, _T_1131)
node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0)
node _T_1133 = shr(io.in.a.bits.source, 5)
node _T_1134 = eq(_T_1133, UInt<3>(0h4))
node _T_1135 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = leq(uncommonBits_92, UInt<5>(0h1f))
node _T_1138 = and(_T_1136, _T_1137)
node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0)
node _T_1139 = shr(io.in.a.bits.source, 5)
node _T_1140 = eq(_T_1139, UInt<3>(0h5))
node _T_1141 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = leq(uncommonBits_93, UInt<5>(0h1f))
node _T_1144 = and(_T_1142, _T_1143)
node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0)
node _T_1145 = shr(io.in.a.bits.source, 5)
node _T_1146 = eq(_T_1145, UInt<3>(0h6))
node _T_1147 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = leq(uncommonBits_94, UInt<5>(0h1f))
node _T_1150 = and(_T_1148, _T_1149)
node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0)
node _T_1151 = shr(io.in.a.bits.source, 5)
node _T_1152 = eq(_T_1151, UInt<3>(0h7))
node _T_1153 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1154 = and(_T_1152, _T_1153)
node _T_1155 = leq(uncommonBits_95, UInt<5>(0h1f))
node _T_1156 = and(_T_1154, _T_1155)
node _T_1157 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1158 = or(_T_1081, _T_1087)
node _T_1159 = or(_T_1158, _T_1093)
node _T_1160 = or(_T_1159, _T_1099)
node _T_1161 = or(_T_1160, _T_1105)
node _T_1162 = or(_T_1161, _T_1106)
node _T_1163 = or(_T_1162, _T_1107)
node _T_1164 = or(_T_1163, _T_1108)
node _T_1165 = or(_T_1164, _T_1114)
node _T_1166 = or(_T_1165, _T_1120)
node _T_1167 = or(_T_1166, _T_1126)
node _T_1168 = or(_T_1167, _T_1132)
node _T_1169 = or(_T_1168, _T_1138)
node _T_1170 = or(_T_1169, _T_1144)
node _T_1171 = or(_T_1170, _T_1150)
node _T_1172 = or(_T_1171, _T_1156)
node _T_1173 = or(_T_1172, _T_1157)
node _T_1174 = and(_T_1080, _T_1173)
node _T_1175 = or(UInt<1>(0h0), _T_1174)
node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = or(UInt<1>(0h0), _T_1178)
node _T_1180 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1181 = cvt(_T_1180)
node _T_1182 = and(_T_1181, asSInt(UInt<13>(0h1000)))
node _T_1183 = asSInt(_T_1182)
node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0)))
node _T_1185 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1191 = cvt(_T_1190)
node _T_1192 = and(_T_1191, asSInt(UInt<19>(0h40000)))
node _T_1193 = asSInt(_T_1192)
node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0)))
node _T_1195 = or(_T_1184, _T_1189)
node _T_1196 = or(_T_1195, _T_1194)
node _T_1197 = and(_T_1179, _T_1196)
node _T_1198 = or(UInt<1>(0h0), _T_1197)
node _T_1199 = and(_T_1175, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_31
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(source_ok, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(is_aligned, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1209 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_34
node _T_1213 = not(mask)
node _T_1214 = and(io.in.a.bits.mask, _T_1213)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_35
node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1219 :
node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1222 = and(_T_1220, _T_1221)
node _T_1223 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1224 = shr(io.in.a.bits.source, 2)
node _T_1225 = eq(_T_1224, UInt<7>(0h40))
node _T_1226 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1227 = and(_T_1225, _T_1226)
node _T_1228 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1229 = and(_T_1227, _T_1228)
node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1230 = shr(io.in.a.bits.source, 2)
node _T_1231 = eq(_T_1230, UInt<7>(0h41))
node _T_1232 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1235 = and(_T_1233, _T_1234)
node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1236 = shr(io.in.a.bits.source, 2)
node _T_1237 = eq(_T_1236, UInt<7>(0h42))
node _T_1238 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1239 = and(_T_1237, _T_1238)
node _T_1240 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1241 = and(_T_1239, _T_1240)
node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1242 = shr(io.in.a.bits.source, 2)
node _T_1243 = eq(_T_1242, UInt<7>(0h43))
node _T_1244 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1245 = and(_T_1243, _T_1244)
node _T_1246 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1249 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1250 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0)
node _T_1251 = shr(io.in.a.bits.source, 5)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
node _T_1253 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1254 = and(_T_1252, _T_1253)
node _T_1255 = leq(uncommonBits_100, UInt<5>(0h1f))
node _T_1256 = and(_T_1254, _T_1255)
node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0)
node _T_1257 = shr(io.in.a.bits.source, 5)
node _T_1258 = eq(_T_1257, UInt<1>(0h1))
node _T_1259 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = leq(uncommonBits_101, UInt<5>(0h1f))
node _T_1262 = and(_T_1260, _T_1261)
node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0)
node _T_1263 = shr(io.in.a.bits.source, 5)
node _T_1264 = eq(_T_1263, UInt<2>(0h2))
node _T_1265 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1266 = and(_T_1264, _T_1265)
node _T_1267 = leq(uncommonBits_102, UInt<5>(0h1f))
node _T_1268 = and(_T_1266, _T_1267)
node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0)
node _T_1269 = shr(io.in.a.bits.source, 5)
node _T_1270 = eq(_T_1269, UInt<2>(0h3))
node _T_1271 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1272 = and(_T_1270, _T_1271)
node _T_1273 = leq(uncommonBits_103, UInt<5>(0h1f))
node _T_1274 = and(_T_1272, _T_1273)
node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0)
node _T_1275 = shr(io.in.a.bits.source, 5)
node _T_1276 = eq(_T_1275, UInt<3>(0h4))
node _T_1277 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = leq(uncommonBits_104, UInt<5>(0h1f))
node _T_1280 = and(_T_1278, _T_1279)
node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0)
node _T_1281 = shr(io.in.a.bits.source, 5)
node _T_1282 = eq(_T_1281, UInt<3>(0h5))
node _T_1283 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1284 = and(_T_1282, _T_1283)
node _T_1285 = leq(uncommonBits_105, UInt<5>(0h1f))
node _T_1286 = and(_T_1284, _T_1285)
node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0)
node _T_1287 = shr(io.in.a.bits.source, 5)
node _T_1288 = eq(_T_1287, UInt<3>(0h6))
node _T_1289 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1290 = and(_T_1288, _T_1289)
node _T_1291 = leq(uncommonBits_106, UInt<5>(0h1f))
node _T_1292 = and(_T_1290, _T_1291)
node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0)
node _T_1293 = shr(io.in.a.bits.source, 5)
node _T_1294 = eq(_T_1293, UInt<3>(0h7))
node _T_1295 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1296 = and(_T_1294, _T_1295)
node _T_1297 = leq(uncommonBits_107, UInt<5>(0h1f))
node _T_1298 = and(_T_1296, _T_1297)
node _T_1299 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1300 = or(_T_1223, _T_1229)
node _T_1301 = or(_T_1300, _T_1235)
node _T_1302 = or(_T_1301, _T_1241)
node _T_1303 = or(_T_1302, _T_1247)
node _T_1304 = or(_T_1303, _T_1248)
node _T_1305 = or(_T_1304, _T_1249)
node _T_1306 = or(_T_1305, _T_1250)
node _T_1307 = or(_T_1306, _T_1256)
node _T_1308 = or(_T_1307, _T_1262)
node _T_1309 = or(_T_1308, _T_1268)
node _T_1310 = or(_T_1309, _T_1274)
node _T_1311 = or(_T_1310, _T_1280)
node _T_1312 = or(_T_1311, _T_1286)
node _T_1313 = or(_T_1312, _T_1292)
node _T_1314 = or(_T_1313, _T_1298)
node _T_1315 = or(_T_1314, _T_1299)
node _T_1316 = and(_T_1222, _T_1315)
node _T_1317 = or(UInt<1>(0h0), _T_1316)
node _T_1318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1319 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1320 = and(_T_1318, _T_1319)
node _T_1321 = or(UInt<1>(0h0), _T_1320)
node _T_1322 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1323 = cvt(_T_1322)
node _T_1324 = and(_T_1323, asSInt(UInt<13>(0h1000)))
node _T_1325 = asSInt(_T_1324)
node _T_1326 = eq(_T_1325, asSInt(UInt<1>(0h0)))
node _T_1327 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1328 = cvt(_T_1327)
node _T_1329 = and(_T_1328, asSInt(UInt<13>(0h1000)))
node _T_1330 = asSInt(_T_1329)
node _T_1331 = eq(_T_1330, asSInt(UInt<1>(0h0)))
node _T_1332 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1333 = cvt(_T_1332)
node _T_1334 = and(_T_1333, asSInt(UInt<19>(0h40000)))
node _T_1335 = asSInt(_T_1334)
node _T_1336 = eq(_T_1335, asSInt(UInt<1>(0h0)))
node _T_1337 = or(_T_1326, _T_1331)
node _T_1338 = or(_T_1337, _T_1336)
node _T_1339 = and(_T_1321, _T_1338)
node _T_1340 = or(UInt<1>(0h0), _T_1339)
node _T_1341 = and(_T_1317, _T_1340)
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(_T_1341, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1341, UInt<1>(0h1), "") : assert_36
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(source_ok, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(is_aligned, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1351 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_39
node _T_1355 = eq(io.in.a.bits.mask, mask)
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_40
node _T_1359 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1359 :
node _T_1360 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1361 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1362 = and(_T_1360, _T_1361)
node _T_1363 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0)
node _T_1364 = shr(io.in.a.bits.source, 2)
node _T_1365 = eq(_T_1364, UInt<7>(0h40))
node _T_1366 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1367 = and(_T_1365, _T_1366)
node _T_1368 = leq(uncommonBits_108, UInt<2>(0h3))
node _T_1369 = and(_T_1367, _T_1368)
node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0)
node _T_1370 = shr(io.in.a.bits.source, 2)
node _T_1371 = eq(_T_1370, UInt<7>(0h41))
node _T_1372 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1373 = and(_T_1371, _T_1372)
node _T_1374 = leq(uncommonBits_109, UInt<2>(0h3))
node _T_1375 = and(_T_1373, _T_1374)
node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0)
node _T_1376 = shr(io.in.a.bits.source, 2)
node _T_1377 = eq(_T_1376, UInt<7>(0h42))
node _T_1378 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1379 = and(_T_1377, _T_1378)
node _T_1380 = leq(uncommonBits_110, UInt<2>(0h3))
node _T_1381 = and(_T_1379, _T_1380)
node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0)
node _T_1382 = shr(io.in.a.bits.source, 2)
node _T_1383 = eq(_T_1382, UInt<7>(0h43))
node _T_1384 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1385 = and(_T_1383, _T_1384)
node _T_1386 = leq(uncommonBits_111, UInt<2>(0h3))
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1389 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1390 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0)
node _T_1391 = shr(io.in.a.bits.source, 5)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
node _T_1393 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_1394 = and(_T_1392, _T_1393)
node _T_1395 = leq(uncommonBits_112, UInt<5>(0h1f))
node _T_1396 = and(_T_1394, _T_1395)
node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0)
node _T_1397 = shr(io.in.a.bits.source, 5)
node _T_1398 = eq(_T_1397, UInt<1>(0h1))
node _T_1399 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_1400 = and(_T_1398, _T_1399)
node _T_1401 = leq(uncommonBits_113, UInt<5>(0h1f))
node _T_1402 = and(_T_1400, _T_1401)
node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0)
node _T_1403 = shr(io.in.a.bits.source, 5)
node _T_1404 = eq(_T_1403, UInt<2>(0h2))
node _T_1405 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_1406 = and(_T_1404, _T_1405)
node _T_1407 = leq(uncommonBits_114, UInt<5>(0h1f))
node _T_1408 = and(_T_1406, _T_1407)
node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0)
node _T_1409 = shr(io.in.a.bits.source, 5)
node _T_1410 = eq(_T_1409, UInt<2>(0h3))
node _T_1411 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_1412 = and(_T_1410, _T_1411)
node _T_1413 = leq(uncommonBits_115, UInt<5>(0h1f))
node _T_1414 = and(_T_1412, _T_1413)
node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0)
node _T_1415 = shr(io.in.a.bits.source, 5)
node _T_1416 = eq(_T_1415, UInt<3>(0h4))
node _T_1417 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_1418 = and(_T_1416, _T_1417)
node _T_1419 = leq(uncommonBits_116, UInt<5>(0h1f))
node _T_1420 = and(_T_1418, _T_1419)
node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0)
node _T_1421 = shr(io.in.a.bits.source, 5)
node _T_1422 = eq(_T_1421, UInt<3>(0h5))
node _T_1423 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_1424 = and(_T_1422, _T_1423)
node _T_1425 = leq(uncommonBits_117, UInt<5>(0h1f))
node _T_1426 = and(_T_1424, _T_1425)
node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0)
node _T_1427 = shr(io.in.a.bits.source, 5)
node _T_1428 = eq(_T_1427, UInt<3>(0h6))
node _T_1429 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_1430 = and(_T_1428, _T_1429)
node _T_1431 = leq(uncommonBits_118, UInt<5>(0h1f))
node _T_1432 = and(_T_1430, _T_1431)
node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0)
node _T_1433 = shr(io.in.a.bits.source, 5)
node _T_1434 = eq(_T_1433, UInt<3>(0h7))
node _T_1435 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_1436 = and(_T_1434, _T_1435)
node _T_1437 = leq(uncommonBits_119, UInt<5>(0h1f))
node _T_1438 = and(_T_1436, _T_1437)
node _T_1439 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1440 = or(_T_1363, _T_1369)
node _T_1441 = or(_T_1440, _T_1375)
node _T_1442 = or(_T_1441, _T_1381)
node _T_1443 = or(_T_1442, _T_1387)
node _T_1444 = or(_T_1443, _T_1388)
node _T_1445 = or(_T_1444, _T_1389)
node _T_1446 = or(_T_1445, _T_1390)
node _T_1447 = or(_T_1446, _T_1396)
node _T_1448 = or(_T_1447, _T_1402)
node _T_1449 = or(_T_1448, _T_1408)
node _T_1450 = or(_T_1449, _T_1414)
node _T_1451 = or(_T_1450, _T_1420)
node _T_1452 = or(_T_1451, _T_1426)
node _T_1453 = or(_T_1452, _T_1432)
node _T_1454 = or(_T_1453, _T_1438)
node _T_1455 = or(_T_1454, _T_1439)
node _T_1456 = and(_T_1362, _T_1455)
node _T_1457 = or(UInt<1>(0h0), _T_1456)
node _T_1458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1459 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1460 = and(_T_1458, _T_1459)
node _T_1461 = or(UInt<1>(0h0), _T_1460)
node _T_1462 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<13>(0h1000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1468 = cvt(_T_1467)
node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000)))
node _T_1470 = asSInt(_T_1469)
node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0)))
node _T_1472 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1473 = cvt(_T_1472)
node _T_1474 = and(_T_1473, asSInt(UInt<19>(0h40000)))
node _T_1475 = asSInt(_T_1474)
node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0)))
node _T_1477 = or(_T_1466, _T_1471)
node _T_1478 = or(_T_1477, _T_1476)
node _T_1479 = and(_T_1461, _T_1478)
node _T_1480 = or(UInt<1>(0h0), _T_1479)
node _T_1481 = and(_T_1457, _T_1480)
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_41
node _T_1485 = asUInt(reset)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
when _T_1486 :
node _T_1487 = eq(source_ok, UInt<1>(0h0))
when _T_1487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(is_aligned, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1491 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_44
node _T_1495 = eq(io.in.a.bits.mask, mask)
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_45
node _T_1499 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1499 :
node _T_1500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1502 = and(_T_1500, _T_1501)
node _T_1503 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0)
node _T_1504 = shr(io.in.a.bits.source, 2)
node _T_1505 = eq(_T_1504, UInt<7>(0h40))
node _T_1506 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_1507 = and(_T_1505, _T_1506)
node _T_1508 = leq(uncommonBits_120, UInt<2>(0h3))
node _T_1509 = and(_T_1507, _T_1508)
node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0)
node _T_1510 = shr(io.in.a.bits.source, 2)
node _T_1511 = eq(_T_1510, UInt<7>(0h41))
node _T_1512 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_1513 = and(_T_1511, _T_1512)
node _T_1514 = leq(uncommonBits_121, UInt<2>(0h3))
node _T_1515 = and(_T_1513, _T_1514)
node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_1516 = shr(io.in.a.bits.source, 2)
node _T_1517 = eq(_T_1516, UInt<7>(0h42))
node _T_1518 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_1519 = and(_T_1517, _T_1518)
node _T_1520 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_1521 = and(_T_1519, _T_1520)
node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0)
node _T_1522 = shr(io.in.a.bits.source, 2)
node _T_1523 = eq(_T_1522, UInt<7>(0h43))
node _T_1524 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_1525 = and(_T_1523, _T_1524)
node _T_1526 = leq(uncommonBits_123, UInt<2>(0h3))
node _T_1527 = and(_T_1525, _T_1526)
node _T_1528 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1529 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1530 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0)
node _T_1531 = shr(io.in.a.bits.source, 5)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
node _T_1533 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_1534 = and(_T_1532, _T_1533)
node _T_1535 = leq(uncommonBits_124, UInt<5>(0h1f))
node _T_1536 = and(_T_1534, _T_1535)
node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0)
node _T_1537 = shr(io.in.a.bits.source, 5)
node _T_1538 = eq(_T_1537, UInt<1>(0h1))
node _T_1539 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_1540 = and(_T_1538, _T_1539)
node _T_1541 = leq(uncommonBits_125, UInt<5>(0h1f))
node _T_1542 = and(_T_1540, _T_1541)
node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0)
node _T_1543 = shr(io.in.a.bits.source, 5)
node _T_1544 = eq(_T_1543, UInt<2>(0h2))
node _T_1545 = leq(UInt<1>(0h0), uncommonBits_126)
node _T_1546 = and(_T_1544, _T_1545)
node _T_1547 = leq(uncommonBits_126, UInt<5>(0h1f))
node _T_1548 = and(_T_1546, _T_1547)
node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0)
node _T_1549 = shr(io.in.a.bits.source, 5)
node _T_1550 = eq(_T_1549, UInt<2>(0h3))
node _T_1551 = leq(UInt<1>(0h0), uncommonBits_127)
node _T_1552 = and(_T_1550, _T_1551)
node _T_1553 = leq(uncommonBits_127, UInt<5>(0h1f))
node _T_1554 = and(_T_1552, _T_1553)
node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0)
node _T_1555 = shr(io.in.a.bits.source, 5)
node _T_1556 = eq(_T_1555, UInt<3>(0h4))
node _T_1557 = leq(UInt<1>(0h0), uncommonBits_128)
node _T_1558 = and(_T_1556, _T_1557)
node _T_1559 = leq(uncommonBits_128, UInt<5>(0h1f))
node _T_1560 = and(_T_1558, _T_1559)
node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0)
node _T_1561 = shr(io.in.a.bits.source, 5)
node _T_1562 = eq(_T_1561, UInt<3>(0h5))
node _T_1563 = leq(UInt<1>(0h0), uncommonBits_129)
node _T_1564 = and(_T_1562, _T_1563)
node _T_1565 = leq(uncommonBits_129, UInt<5>(0h1f))
node _T_1566 = and(_T_1564, _T_1565)
node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0)
node _T_1567 = shr(io.in.a.bits.source, 5)
node _T_1568 = eq(_T_1567, UInt<3>(0h6))
node _T_1569 = leq(UInt<1>(0h0), uncommonBits_130)
node _T_1570 = and(_T_1568, _T_1569)
node _T_1571 = leq(uncommonBits_130, UInt<5>(0h1f))
node _T_1572 = and(_T_1570, _T_1571)
node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0)
node _T_1573 = shr(io.in.a.bits.source, 5)
node _T_1574 = eq(_T_1573, UInt<3>(0h7))
node _T_1575 = leq(UInt<1>(0h0), uncommonBits_131)
node _T_1576 = and(_T_1574, _T_1575)
node _T_1577 = leq(uncommonBits_131, UInt<5>(0h1f))
node _T_1578 = and(_T_1576, _T_1577)
node _T_1579 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1580 = or(_T_1503, _T_1509)
node _T_1581 = or(_T_1580, _T_1515)
node _T_1582 = or(_T_1581, _T_1521)
node _T_1583 = or(_T_1582, _T_1527)
node _T_1584 = or(_T_1583, _T_1528)
node _T_1585 = or(_T_1584, _T_1529)
node _T_1586 = or(_T_1585, _T_1530)
node _T_1587 = or(_T_1586, _T_1536)
node _T_1588 = or(_T_1587, _T_1542)
node _T_1589 = or(_T_1588, _T_1548)
node _T_1590 = or(_T_1589, _T_1554)
node _T_1591 = or(_T_1590, _T_1560)
node _T_1592 = or(_T_1591, _T_1566)
node _T_1593 = or(_T_1592, _T_1572)
node _T_1594 = or(_T_1593, _T_1578)
node _T_1595 = or(_T_1594, _T_1579)
node _T_1596 = and(_T_1502, _T_1595)
node _T_1597 = or(UInt<1>(0h0), _T_1596)
node _T_1598 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1599 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1600 = cvt(_T_1599)
node _T_1601 = and(_T_1600, asSInt(UInt<13>(0h1000)))
node _T_1602 = asSInt(_T_1601)
node _T_1603 = eq(_T_1602, asSInt(UInt<1>(0h0)))
node _T_1604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1605 = cvt(_T_1604)
node _T_1606 = and(_T_1605, asSInt(UInt<13>(0h1000)))
node _T_1607 = asSInt(_T_1606)
node _T_1608 = eq(_T_1607, asSInt(UInt<1>(0h0)))
node _T_1609 = xor(io.in.a.bits.address, UInt<29>(0h10040000))
node _T_1610 = cvt(_T_1609)
node _T_1611 = and(_T_1610, asSInt(UInt<19>(0h40000)))
node _T_1612 = asSInt(_T_1611)
node _T_1613 = eq(_T_1612, asSInt(UInt<1>(0h0)))
node _T_1614 = or(_T_1603, _T_1608)
node _T_1615 = or(_T_1614, _T_1613)
node _T_1616 = and(_T_1598, _T_1615)
node _T_1617 = or(UInt<1>(0h0), _T_1616)
node _T_1618 = and(_T_1597, _T_1617)
node _T_1619 = asUInt(reset)
node _T_1620 = eq(_T_1619, UInt<1>(0h0))
when _T_1620 :
node _T_1621 = eq(_T_1618, UInt<1>(0h0))
when _T_1621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1618, UInt<1>(0h1), "") : assert_46
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(source_ok, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(is_aligned, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1628 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_49
node _T_1632 = eq(io.in.a.bits.mask, mask)
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_50
node _T_1636 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1637 = asUInt(reset)
node _T_1638 = eq(_T_1637, UInt<1>(0h0))
when _T_1638 :
node _T_1639 = eq(_T_1636, UInt<1>(0h0))
when _T_1639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1636, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1640 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1641 = asUInt(reset)
node _T_1642 = eq(_T_1641, UInt<1>(0h0))
when _T_1642 :
node _T_1643 = eq(_T_1640, UInt<1>(0h0))
when _T_1643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1640, UInt<1>(0h1), "") : assert_52
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.d.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.d.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.d.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.d.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0)
node _source_ok_T_120 = shr(io.in.d.bits.source, 5)
node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0))
node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122)
node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f))
node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124)
node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0)
node _source_ok_T_126 = shr(io.in.d.bits.source, 5)
node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1))
node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128)
node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f))
node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130)
node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0)
node _source_ok_T_132 = shr(io.in.d.bits.source, 5)
node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2))
node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134)
node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f))
node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136)
node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0)
node _source_ok_T_138 = shr(io.in.d.bits.source, 5)
node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3))
node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140)
node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f))
node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142)
node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0)
node _source_ok_T_144 = shr(io.in.d.bits.source, 5)
node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4))
node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146)
node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f))
node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148)
node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0)
node _source_ok_T_150 = shr(io.in.d.bits.source, 5)
node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5))
node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21)
node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152)
node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f))
node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154)
node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0)
node _source_ok_T_156 = shr(io.in.d.bits.source, 5)
node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6))
node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22)
node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158)
node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f))
node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160)
node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0)
node _source_ok_T_162 = shr(io.in.d.bits.source, 5)
node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7))
node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23)
node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164)
node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f))
node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166)
node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE_1 : UInt<1>[17]
connect _source_ok_WIRE_1[0], _source_ok_T_92
connect _source_ok_WIRE_1[1], _source_ok_T_98
connect _source_ok_WIRE_1[2], _source_ok_T_104
connect _source_ok_WIRE_1[3], _source_ok_T_110
connect _source_ok_WIRE_1[4], _source_ok_T_116
connect _source_ok_WIRE_1[5], _source_ok_T_117
connect _source_ok_WIRE_1[6], _source_ok_T_118
connect _source_ok_WIRE_1[7], _source_ok_T_119
connect _source_ok_WIRE_1[8], _source_ok_T_125
connect _source_ok_WIRE_1[9], _source_ok_T_131
connect _source_ok_WIRE_1[10], _source_ok_T_137
connect _source_ok_WIRE_1[11], _source_ok_T_143
connect _source_ok_WIRE_1[12], _source_ok_T_149
connect _source_ok_WIRE_1[13], _source_ok_T_155
connect _source_ok_WIRE_1[14], _source_ok_T_161
connect _source_ok_WIRE_1[15], _source_ok_T_167
connect _source_ok_WIRE_1[16], _source_ok_T_168
node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11])
node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12])
node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13])
node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14])
node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15])
node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1644 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1644 :
node _T_1645 = asUInt(reset)
node _T_1646 = eq(_T_1645, UInt<1>(0h0))
when _T_1646 :
node _T_1647 = eq(source_ok_1, UInt<1>(0h0))
when _T_1647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1648 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1649 = asUInt(reset)
node _T_1650 = eq(_T_1649, UInt<1>(0h0))
when _T_1650 :
node _T_1651 = eq(_T_1648, UInt<1>(0h0))
when _T_1651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1648, UInt<1>(0h1), "") : assert_54
node _T_1652 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1653 = asUInt(reset)
node _T_1654 = eq(_T_1653, UInt<1>(0h0))
when _T_1654 :
node _T_1655 = eq(_T_1652, UInt<1>(0h0))
when _T_1655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1652, UInt<1>(0h1), "") : assert_55
node _T_1656 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(_T_1656, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1656, UInt<1>(0h1), "") : assert_56
node _T_1660 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1661 = asUInt(reset)
node _T_1662 = eq(_T_1661, UInt<1>(0h0))
when _T_1662 :
node _T_1663 = eq(_T_1660, UInt<1>(0h0))
when _T_1663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1660, UInt<1>(0h1), "") : assert_57
node _T_1664 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1664 :
node _T_1665 = asUInt(reset)
node _T_1666 = eq(_T_1665, UInt<1>(0h0))
when _T_1666 :
node _T_1667 = eq(source_ok_1, UInt<1>(0h0))
when _T_1667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1668 = asUInt(reset)
node _T_1669 = eq(_T_1668, UInt<1>(0h0))
when _T_1669 :
node _T_1670 = eq(sink_ok, UInt<1>(0h0))
when _T_1670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1671 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1672 = asUInt(reset)
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
when _T_1673 :
node _T_1674 = eq(_T_1671, UInt<1>(0h0))
when _T_1674 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1671, UInt<1>(0h1), "") : assert_60
node _T_1675 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_61
node _T_1679 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1680 = asUInt(reset)
node _T_1681 = eq(_T_1680, UInt<1>(0h0))
when _T_1681 :
node _T_1682 = eq(_T_1679, UInt<1>(0h0))
when _T_1682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1679, UInt<1>(0h1), "") : assert_62
node _T_1683 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1684 = asUInt(reset)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(_T_1683, UInt<1>(0h0))
when _T_1686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1683, UInt<1>(0h1), "") : assert_63
node _T_1687 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1688 = or(UInt<1>(0h1), _T_1687)
node _T_1689 = asUInt(reset)
node _T_1690 = eq(_T_1689, UInt<1>(0h0))
when _T_1690 :
node _T_1691 = eq(_T_1688, UInt<1>(0h0))
when _T_1691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1688, UInt<1>(0h1), "") : assert_64
node _T_1692 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1692 :
node _T_1693 = asUInt(reset)
node _T_1694 = eq(_T_1693, UInt<1>(0h0))
when _T_1694 :
node _T_1695 = eq(source_ok_1, UInt<1>(0h0))
when _T_1695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(sink_ok, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1699 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1700 = asUInt(reset)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
when _T_1701 :
node _T_1702 = eq(_T_1699, UInt<1>(0h0))
when _T_1702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1699, UInt<1>(0h1), "") : assert_67
node _T_1703 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1704 = asUInt(reset)
node _T_1705 = eq(_T_1704, UInt<1>(0h0))
when _T_1705 :
node _T_1706 = eq(_T_1703, UInt<1>(0h0))
when _T_1706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1703, UInt<1>(0h1), "") : assert_68
node _T_1707 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1708 = asUInt(reset)
node _T_1709 = eq(_T_1708, UInt<1>(0h0))
when _T_1709 :
node _T_1710 = eq(_T_1707, UInt<1>(0h0))
when _T_1710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1707, UInt<1>(0h1), "") : assert_69
node _T_1711 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1712 = or(_T_1711, io.in.d.bits.corrupt)
node _T_1713 = asUInt(reset)
node _T_1714 = eq(_T_1713, UInt<1>(0h0))
when _T_1714 :
node _T_1715 = eq(_T_1712, UInt<1>(0h0))
when _T_1715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1712, UInt<1>(0h1), "") : assert_70
node _T_1716 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1717 = or(UInt<1>(0h1), _T_1716)
node _T_1718 = asUInt(reset)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
when _T_1719 :
node _T_1720 = eq(_T_1717, UInt<1>(0h0))
when _T_1720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1717, UInt<1>(0h1), "") : assert_71
node _T_1721 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1721 :
node _T_1722 = asUInt(reset)
node _T_1723 = eq(_T_1722, UInt<1>(0h0))
when _T_1723 :
node _T_1724 = eq(source_ok_1, UInt<1>(0h0))
when _T_1724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1725 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1726 = asUInt(reset)
node _T_1727 = eq(_T_1726, UInt<1>(0h0))
when _T_1727 :
node _T_1728 = eq(_T_1725, UInt<1>(0h0))
when _T_1728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1725, UInt<1>(0h1), "") : assert_73
node _T_1729 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1730 = asUInt(reset)
node _T_1731 = eq(_T_1730, UInt<1>(0h0))
when _T_1731 :
node _T_1732 = eq(_T_1729, UInt<1>(0h0))
when _T_1732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1729, UInt<1>(0h1), "") : assert_74
node _T_1733 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1734 = or(UInt<1>(0h1), _T_1733)
node _T_1735 = asUInt(reset)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
when _T_1736 :
node _T_1737 = eq(_T_1734, UInt<1>(0h0))
when _T_1737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1734, UInt<1>(0h1), "") : assert_75
node _T_1738 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1738 :
node _T_1739 = asUInt(reset)
node _T_1740 = eq(_T_1739, UInt<1>(0h0))
when _T_1740 :
node _T_1741 = eq(source_ok_1, UInt<1>(0h0))
when _T_1741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1742 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1743 = asUInt(reset)
node _T_1744 = eq(_T_1743, UInt<1>(0h0))
when _T_1744 :
node _T_1745 = eq(_T_1742, UInt<1>(0h0))
when _T_1745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1742, UInt<1>(0h1), "") : assert_77
node _T_1746 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1747 = or(_T_1746, io.in.d.bits.corrupt)
node _T_1748 = asUInt(reset)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
when _T_1749 :
node _T_1750 = eq(_T_1747, UInt<1>(0h0))
when _T_1750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1747, UInt<1>(0h1), "") : assert_78
node _T_1751 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1752 = or(UInt<1>(0h1), _T_1751)
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_79
node _T_1756 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1756 :
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(source_ok_1, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1760 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1761 = asUInt(reset)
node _T_1762 = eq(_T_1761, UInt<1>(0h0))
when _T_1762 :
node _T_1763 = eq(_T_1760, UInt<1>(0h0))
when _T_1763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1760, UInt<1>(0h1), "") : assert_81
node _T_1764 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1765 = asUInt(reset)
node _T_1766 = eq(_T_1765, UInt<1>(0h0))
when _T_1766 :
node _T_1767 = eq(_T_1764, UInt<1>(0h0))
when _T_1767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1764, UInt<1>(0h1), "") : assert_82
node _T_1768 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1769 = or(UInt<1>(0h1), _T_1768)
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1773 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1777 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1778 = asUInt(reset)
node _T_1779 = eq(_T_1778, UInt<1>(0h0))
when _T_1779 :
node _T_1780 = eq(_T_1777, UInt<1>(0h0))
when _T_1780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1777, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1781 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(_T_1781, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1781, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1785 = eq(a_first, UInt<1>(0h0))
node _T_1786 = and(io.in.a.valid, _T_1785)
when _T_1786 :
node _T_1787 = eq(io.in.a.bits.opcode, opcode)
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(_T_1787, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1787, UInt<1>(0h1), "") : assert_87
node _T_1791 = eq(io.in.a.bits.param, param)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_88
node _T_1795 = eq(io.in.a.bits.size, size)
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_89
node _T_1799 = eq(io.in.a.bits.source, source)
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_90
node _T_1803 = eq(io.in.a.bits.address, address)
node _T_1804 = asUInt(reset)
node _T_1805 = eq(_T_1804, UInt<1>(0h0))
when _T_1805 :
node _T_1806 = eq(_T_1803, UInt<1>(0h0))
when _T_1806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1803, UInt<1>(0h1), "") : assert_91
node _T_1807 = and(io.in.a.ready, io.in.a.valid)
node _T_1808 = and(_T_1807, a_first)
when _T_1808 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1809 = eq(d_first, UInt<1>(0h0))
node _T_1810 = and(io.in.d.valid, _T_1809)
when _T_1810 :
node _T_1811 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1812 = asUInt(reset)
node _T_1813 = eq(_T_1812, UInt<1>(0h0))
when _T_1813 :
node _T_1814 = eq(_T_1811, UInt<1>(0h0))
when _T_1814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1811, UInt<1>(0h1), "") : assert_92
node _T_1815 = eq(io.in.d.bits.param, param_1)
node _T_1816 = asUInt(reset)
node _T_1817 = eq(_T_1816, UInt<1>(0h0))
when _T_1817 :
node _T_1818 = eq(_T_1815, UInt<1>(0h0))
when _T_1818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1815, UInt<1>(0h1), "") : assert_93
node _T_1819 = eq(io.in.d.bits.size, size_1)
node _T_1820 = asUInt(reset)
node _T_1821 = eq(_T_1820, UInt<1>(0h0))
when _T_1821 :
node _T_1822 = eq(_T_1819, UInt<1>(0h0))
when _T_1822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1819, UInt<1>(0h1), "") : assert_94
node _T_1823 = eq(io.in.d.bits.source, source_1)
node _T_1824 = asUInt(reset)
node _T_1825 = eq(_T_1824, UInt<1>(0h0))
when _T_1825 :
node _T_1826 = eq(_T_1823, UInt<1>(0h0))
when _T_1826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1823, UInt<1>(0h1), "") : assert_95
node _T_1827 = eq(io.in.d.bits.sink, sink)
node _T_1828 = asUInt(reset)
node _T_1829 = eq(_T_1828, UInt<1>(0h0))
when _T_1829 :
node _T_1830 = eq(_T_1827, UInt<1>(0h0))
when _T_1830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1827, UInt<1>(0h1), "") : assert_96
node _T_1831 = eq(io.in.d.bits.denied, denied)
node _T_1832 = asUInt(reset)
node _T_1833 = eq(_T_1832, UInt<1>(0h0))
when _T_1833 :
node _T_1834 = eq(_T_1831, UInt<1>(0h0))
when _T_1834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1831, UInt<1>(0h1), "") : assert_97
node _T_1835 = and(io.in.d.ready, io.in.d.valid)
node _T_1836 = and(_T_1835, d_first)
when _T_1836 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<513>
connect a_set, UInt<513>(0h0)
wire a_set_wo_ready : UInt<513>
connect a_set_wo_ready, UInt<513>(0h0)
wire a_opcodes_set : UInt<2052>
connect a_opcodes_set, UInt<2052>(0h0)
wire a_sizes_set : UInt<2052>
connect a_sizes_set, UInt<2052>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1837 = and(io.in.a.valid, a_first_1)
node _T_1838 = and(_T_1837, UInt<1>(0h1))
when _T_1838 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1839 = and(io.in.a.ready, io.in.a.valid)
node _T_1840 = and(_T_1839, a_first_1)
node _T_1841 = and(_T_1840, UInt<1>(0h1))
when _T_1841 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1842 = dshr(inflight, io.in.a.bits.source)
node _T_1843 = bits(_T_1842, 0, 0)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
node _T_1845 = asUInt(reset)
node _T_1846 = eq(_T_1845, UInt<1>(0h0))
when _T_1846 :
node _T_1847 = eq(_T_1844, UInt<1>(0h0))
when _T_1847 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1844, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<513>
connect d_clr, UInt<513>(0h0)
wire d_clr_wo_ready : UInt<513>
connect d_clr_wo_ready, UInt<513>(0h0)
wire d_opcodes_clr : UInt<2052>
connect d_opcodes_clr, UInt<2052>(0h0)
wire d_sizes_clr : UInt<2052>
connect d_sizes_clr, UInt<2052>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1848 = and(io.in.d.valid, d_first_1)
node _T_1849 = and(_T_1848, UInt<1>(0h1))
node _T_1850 = eq(d_release_ack, UInt<1>(0h0))
node _T_1851 = and(_T_1849, _T_1850)
when _T_1851 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1852 = and(io.in.d.ready, io.in.d.valid)
node _T_1853 = and(_T_1852, d_first_1)
node _T_1854 = and(_T_1853, UInt<1>(0h1))
node _T_1855 = eq(d_release_ack, UInt<1>(0h0))
node _T_1856 = and(_T_1854, _T_1855)
when _T_1856 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1857 = and(io.in.d.valid, d_first_1)
node _T_1858 = and(_T_1857, UInt<1>(0h1))
node _T_1859 = eq(d_release_ack, UInt<1>(0h0))
node _T_1860 = and(_T_1858, _T_1859)
when _T_1860 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1861 = dshr(inflight, io.in.d.bits.source)
node _T_1862 = bits(_T_1861, 0, 0)
node _T_1863 = or(_T_1862, same_cycle_resp)
node _T_1864 = asUInt(reset)
node _T_1865 = eq(_T_1864, UInt<1>(0h0))
when _T_1865 :
node _T_1866 = eq(_T_1863, UInt<1>(0h0))
when _T_1866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1863, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1867 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1868 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1869 = or(_T_1867, _T_1868)
node _T_1870 = asUInt(reset)
node _T_1871 = eq(_T_1870, UInt<1>(0h0))
when _T_1871 :
node _T_1872 = eq(_T_1869, UInt<1>(0h0))
when _T_1872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1869, UInt<1>(0h1), "") : assert_100
node _T_1873 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1874 = asUInt(reset)
node _T_1875 = eq(_T_1874, UInt<1>(0h0))
when _T_1875 :
node _T_1876 = eq(_T_1873, UInt<1>(0h0))
when _T_1876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1873, UInt<1>(0h1), "") : assert_101
else :
node _T_1877 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1878 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1879 = or(_T_1877, _T_1878)
node _T_1880 = asUInt(reset)
node _T_1881 = eq(_T_1880, UInt<1>(0h0))
when _T_1881 :
node _T_1882 = eq(_T_1879, UInt<1>(0h0))
when _T_1882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1879, UInt<1>(0h1), "") : assert_102
node _T_1883 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1884 = asUInt(reset)
node _T_1885 = eq(_T_1884, UInt<1>(0h0))
when _T_1885 :
node _T_1886 = eq(_T_1883, UInt<1>(0h0))
when _T_1886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1883, UInt<1>(0h1), "") : assert_103
node _T_1887 = and(io.in.d.valid, d_first_1)
node _T_1888 = and(_T_1887, a_first_1)
node _T_1889 = and(_T_1888, io.in.a.valid)
node _T_1890 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1891 = and(_T_1889, _T_1890)
node _T_1892 = eq(d_release_ack, UInt<1>(0h0))
node _T_1893 = and(_T_1891, _T_1892)
when _T_1893 :
node _T_1894 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1895 = or(_T_1894, io.in.a.ready)
node _T_1896 = asUInt(reset)
node _T_1897 = eq(_T_1896, UInt<1>(0h0))
when _T_1897 :
node _T_1898 = eq(_T_1895, UInt<1>(0h0))
when _T_1898 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1895, UInt<1>(0h1), "") : assert_104
node _T_1899 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1900 = orr(a_set_wo_ready)
node _T_1901 = eq(_T_1900, UInt<1>(0h0))
node _T_1902 = or(_T_1899, _T_1901)
node _T_1903 = asUInt(reset)
node _T_1904 = eq(_T_1903, UInt<1>(0h0))
when _T_1904 :
node _T_1905 = eq(_T_1902, UInt<1>(0h0))
when _T_1905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1902, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_18
node _T_1906 = orr(inflight)
node _T_1907 = eq(_T_1906, UInt<1>(0h0))
node _T_1908 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1909 = or(_T_1907, _T_1908)
node _T_1910 = lt(watchdog, plusarg_reader.out)
node _T_1911 = or(_T_1909, _T_1910)
node _T_1912 = asUInt(reset)
node _T_1913 = eq(_T_1912, UInt<1>(0h0))
when _T_1913 :
node _T_1914 = eq(_T_1911, UInt<1>(0h0))
when _T_1914 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1911, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1915 = and(io.in.a.ready, io.in.a.valid)
node _T_1916 = and(io.in.d.ready, io.in.d.valid)
node _T_1917 = or(_T_1915, _T_1916)
when _T_1917 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<513>
connect c_set, UInt<513>(0h0)
wire c_set_wo_ready : UInt<513>
connect c_set_wo_ready, UInt<513>(0h0)
wire c_opcodes_set : UInt<2052>
connect c_opcodes_set, UInt<2052>(0h0)
wire c_sizes_set : UInt<2052>
connect c_sizes_set, UInt<2052>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1918 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1919 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1920 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1921 = and(_T_1919, _T_1920)
node _T_1922 = and(_T_1918, _T_1921)
when _T_1922 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1923 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1924 = and(_T_1923, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1925 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1926 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1927 = and(_T_1925, _T_1926)
node _T_1928 = and(_T_1924, _T_1927)
when _T_1928 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1929 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1930 = bits(_T_1929, 0, 0)
node _T_1931 = eq(_T_1930, UInt<1>(0h0))
node _T_1932 = asUInt(reset)
node _T_1933 = eq(_T_1932, UInt<1>(0h0))
when _T_1933 :
node _T_1934 = eq(_T_1931, UInt<1>(0h0))
when _T_1934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1931, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<513>
connect d_clr_1, UInt<513>(0h0)
wire d_clr_wo_ready_1 : UInt<513>
connect d_clr_wo_ready_1, UInt<513>(0h0)
wire d_opcodes_clr_1 : UInt<2052>
connect d_opcodes_clr_1, UInt<2052>(0h0)
wire d_sizes_clr_1 : UInt<2052>
connect d_sizes_clr_1, UInt<2052>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1935 = and(io.in.d.valid, d_first_2)
node _T_1936 = and(_T_1935, UInt<1>(0h1))
node _T_1937 = and(_T_1936, d_release_ack_1)
when _T_1937 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1938 = and(io.in.d.ready, io.in.d.valid)
node _T_1939 = and(_T_1938, d_first_2)
node _T_1940 = and(_T_1939, UInt<1>(0h1))
node _T_1941 = and(_T_1940, d_release_ack_1)
when _T_1941 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1942 = and(io.in.d.valid, d_first_2)
node _T_1943 = and(_T_1942, UInt<1>(0h1))
node _T_1944 = and(_T_1943, d_release_ack_1)
when _T_1944 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1945 = dshr(inflight_1, io.in.d.bits.source)
node _T_1946 = bits(_T_1945, 0, 0)
node _T_1947 = or(_T_1946, same_cycle_resp_1)
node _T_1948 = asUInt(reset)
node _T_1949 = eq(_T_1948, UInt<1>(0h0))
when _T_1949 :
node _T_1950 = eq(_T_1947, UInt<1>(0h0))
when _T_1950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1947, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1951 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1952 = asUInt(reset)
node _T_1953 = eq(_T_1952, UInt<1>(0h0))
when _T_1953 :
node _T_1954 = eq(_T_1951, UInt<1>(0h0))
when _T_1954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1951, UInt<1>(0h1), "") : assert_109
else :
node _T_1955 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1956 = asUInt(reset)
node _T_1957 = eq(_T_1956, UInt<1>(0h0))
when _T_1957 :
node _T_1958 = eq(_T_1955, UInt<1>(0h0))
when _T_1958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1955, UInt<1>(0h1), "") : assert_110
node _T_1959 = and(io.in.d.valid, d_first_2)
node _T_1960 = and(_T_1959, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1961 = and(_T_1960, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1962 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1963 = and(_T_1961, _T_1962)
node _T_1964 = and(_T_1963, d_release_ack_1)
node _T_1965 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1966 = and(_T_1964, _T_1965)
when _T_1966 :
node _T_1967 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1968 = or(_T_1967, _WIRE_27.ready)
node _T_1969 = asUInt(reset)
node _T_1970 = eq(_T_1969, UInt<1>(0h0))
when _T_1970 :
node _T_1971 = eq(_T_1968, UInt<1>(0h0))
when _T_1971 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1968, UInt<1>(0h1), "") : assert_111
node _T_1972 = orr(c_set_wo_ready)
when _T_1972 :
node _T_1973 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1974 = asUInt(reset)
node _T_1975 = eq(_T_1974, UInt<1>(0h0))
when _T_1975 :
node _T_1976 = eq(_T_1973, UInt<1>(0h0))
when _T_1976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1973, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_19
node _T_1977 = orr(inflight_1)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
node _T_1979 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1980 = or(_T_1978, _T_1979)
node _T_1981 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1982 = or(_T_1980, _T_1981)
node _T_1983 = asUInt(reset)
node _T_1984 = eq(_T_1983, UInt<1>(0h0))
when _T_1984 :
node _T_1985 = eq(_T_1982, UInt<1>(0h0))
when _T_1985 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1982, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1986 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1987 = and(io.in.d.ready, io.in.d.valid)
node _T_1988 = or(_T_1986, _T_1987)
when _T_1988 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_9( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [512:0] inflight_1; // @[Monitor.scala:726:35]
reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_4 :
input clock : Clock
input reset : Reset
output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}}
node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31)
node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23)
node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0)
node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23)
node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24)
node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25)
node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26)
node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27)
node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28)
node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29)
node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30)
node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31)
node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32)
node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33)
node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34)
node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35)
node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36)
node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37)
node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38)
node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39)
node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40)
node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41)
node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42)
node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43)
node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist)
node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3)
node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn)
node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T)
connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1
node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn)
connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T
connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero
connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign
node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T)
connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1
node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T)
node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn)
node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2)
connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3
node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6)
node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T)
node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2)
node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3)
node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0)
node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5)
node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0)
node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7)
node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31)
node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23)
node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0)
node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23)
node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24)
node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25)
node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26)
node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27)
node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28)
node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29)
node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30)
node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31)
node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32)
node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33)
node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34)
node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35)
node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36)
node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37)
node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38)
node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39)
node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40)
node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41)
node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42)
node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43)
node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist)
node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3)
node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn)
node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T)
connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1
node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn)
connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T
connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero
connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign
node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T)
connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1
node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T)
node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn)
node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2)
connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3
node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6)
node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T)
node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2)
node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3)
node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0)
node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5)
node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0)
node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7)
node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31)
node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23)
node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0)
node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0)
node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1)
node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2)
node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3)
node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4)
node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5)
node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6)
node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7)
node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8)
node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9)
node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10)
node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11)
node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12)
node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13)
node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14)
node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15)
node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16)
node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17)
node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18)
node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19)
node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20)
node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21)
node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22)
node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23)
node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24)
node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25)
node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26)
node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27)
node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28)
node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29)
node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30)
node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31)
node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32)
node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33)
node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34)
node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35)
node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36)
node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37)
node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38)
node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39)
node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40)
node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41)
node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42)
node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43)
node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist)
node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn)
node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2)
node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3)
node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn)
node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T)
connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1
node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn)
connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T
connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero
connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign
node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T)
connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1
node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T)
node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn)
node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2)
connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3
node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6)
node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T)
node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2)
node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3)
node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0)
node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5)
node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0)
node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7)
inst io_out_d_m1_resizer of RecFNToRecFN_168
connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec
connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_m2_resizer of RecFNToRecFN_169
connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec
connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_muladder of MulAddRecFN_e8_s24_68
connect io_out_d_muladder.io.op, UInt<1>(0h0)
connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0)
connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1)
connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out
connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out
connect io_out_d_muladder.io.c, io_out_d_self_rec
wire io_out_d_out : { bits : UInt<32>}
node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23)
node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6)
node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7)
node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T)
connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1
node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1)
connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2
connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero
node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32)
connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T
node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp)
connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T
node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T)
node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0)
node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2)
connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3
node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0)
node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T)
node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1)
node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1)
node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist)
node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0)
node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0)
node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81))
node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1)
node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2)
node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf)
node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5)
node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0)
node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T)
node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1)
node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut)
node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut)
connect io_out_d_out.bits, _io_out_d_out_bits_T
connect io.out_d, io_out_d_out | module MacUnit_4( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [31:0] io_in_a_bits, // @[PE.scala:16:14]
input [31:0] io_in_b_bits, // @[PE.scala:16:14]
input [31:0] io_in_c_bits, // @[PE.scala:16:14]
output [31:0] io_out_d_bits // @[PE.scala:16:14]
);
wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30]
wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32]
wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32]
wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7]
wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7]
wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7]
wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23]
wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7]
wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7]
wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
RecFNToRecFN_168 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32]
.io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m1_resizer_io_out)
); // @[Arithmetic.scala:362:32]
RecFNToRecFN_169 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32]
.io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m2_resizer_io_out)
); // @[Arithmetic.scala:369:32]
MulAddRecFN_e8_s24_68 io_out_d_muladder ( // @[Arithmetic.scala:376:30]
.io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32]
.io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32]
.io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_muladder_io_out)
); // @[Arithmetic.scala:376:30]
assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_81 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h101c0)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h100001c0)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h101c0)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h100001c0)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_98 = shr(io.in.a.bits.source, 5)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h101c0)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h100001c0)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h101c0)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h100001c0)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_176 = shr(io.in.a.bits.source, 5)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h101c0)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h100001c0)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_229 = shr(io.in.a.bits.source, 5)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h101c0)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h100001c0)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_276 = shr(io.in.a.bits.source, 5)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h101c0)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h100001c0)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_325 = shr(io.in.a.bits.source, 5)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h101c0)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h100001c0)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_369 = shr(io.in.a.bits.source, 5)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h101c0)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h100001c0)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_413 = shr(io.in.a.bits.source, 5)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h101c0)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h100001c0)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_162
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_163
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_81( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_5 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_5( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25]
wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30]
wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68]
wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9]
wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23]
wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30]
wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_30 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_30( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_234 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_490
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_234( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_490 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_1 :
output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0))
node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0))
node ordered = and(_ordered_T, _ordered_T_1)
node bothInfs = and(rawA.isInf, rawB.isInf)
node bothZeros = and(rawA.isZero, rawB.isZero)
node eqExps = eq(rawA.sExp, rawB.sExp)
node _common_ltMags_T = lt(rawA.sExp, rawB.sExp)
node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig)
node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1)
node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2)
node _common_eqMags_T = eq(rawA.sig, rawB.sig)
node common_eqMags = and(eqExps, _common_eqMags_T)
node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0))
node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1)
node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0))
node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0))
node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4)
node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0))
node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6)
node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags)
node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9)
node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10)
node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11)
node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12)
node _ordered_eq_T = eq(rawA.sign, rawB.sign)
node _ordered_eq_T_1 = or(bothInfs, common_eqMags)
node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1)
node ordered_eq = or(bothZeros, _ordered_eq_T_2)
node _invalid_T = bits(rawA.sig, 51, 51)
node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0))
node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1)
node _invalid_T_3 = bits(rawB.sig, 51, 51)
node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0))
node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4)
node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5)
node _invalid_T_7 = eq(ordered, UInt<1>(0h0))
node _invalid_T_8 = and(io.signaling, _invalid_T_7)
node invalid = or(_invalid_T_6, _invalid_T_8)
node _io_lt_T = and(ordered, ordered_lt)
connect io.lt, _io_lt_T
node _io_eq_T = and(ordered, ordered_eq)
connect io.eq, _io_eq_T
node _io_gt_T = eq(ordered_lt, UInt<1>(0h0))
node _io_gt_T_1 = and(ordered, _io_gt_T)
node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0))
node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2)
connect io.gt, _io_gt_T_3
node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T | module CompareRecFN_1( // @[CompareRecFN.scala:42:7]
input [64:0] io_a, // @[CompareRecFN.scala:44:16]
input [64:0] io_b, // @[CompareRecFN.scala:44:16]
input io_signaling, // @[CompareRecFN.scala:44:16]
output io_lt, // @[CompareRecFN.scala:44:16]
output io_eq, // @[CompareRecFN.scala:44:16]
output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16]
);
wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7]
wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7]
wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7]
wire _io_lt_T; // @[CompareRecFN.scala:78:22]
wire _io_eq_T; // @[CompareRecFN.scala:79:22]
wire _io_gt_T_3; // @[CompareRecFN.scala:80:38]
wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34]
wire io_lt_0; // @[CompareRecFN.scala:42:7]
wire io_eq_0; // @[CompareRecFN.scala:42:7]
wire io_gt; // @[CompareRecFN.scala:42:7]
wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}]
wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}]
wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}]
wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}]
wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9]
wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19]
wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38]
wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57]
wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}]
wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}]
wire _ordered_lt_T_10 = _ordered_lt_T_7 | _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41]
wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74]
wire _ordered_lt_T_12 = _ordered_lt_T_2 | _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30]
wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41]
wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_eq_T_1 = bothInfs | common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62]
wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}]
wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}]
wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}]
wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}]
wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_6 = _invalid_T_2 | _invalid_T_5; // @[common.scala:82:46]
wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30]
wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}]
wire invalid = _invalid_T_6 | _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27]
assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22]
assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22]
assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22]
assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22]
wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25]
wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}]
wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41]
assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}]
assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38]
assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34]
assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34]
assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7]
assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLROM :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_50
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire rom : UInt<64>[512]
connect rom[0], UInt<64>(0h405051300000517)
connect rom[1], UInt<64>(0h301022f330551073)
connect rom[2], UInt<64>(0h12f2934122d293)
connect rom[3], UInt<64>(0h3030107300028863)
connect rom[4], UInt<64>(0h3445307322200513)
connect rom[5], UInt<64>(0h3045107300800513)
connect rom[6], UInt<64>(0h1050007330052073)
connect rom[7], UInt<64>(0hffdff06f)
connect rom[8], UInt<64>(0hf1402573020005b7)
connect rom[9], UInt<64>(0h380006f00050463)
connect rom[10], UInt<64>(0h10069300458613)
connect rom[11], UInt<64>(0h46061300d62023)
connect rom[12], UInt<64>(0hfe069ae3ffc62683)
connect rom[13], UInt<64>(0h2c0006f)
connect rom[14], UInt<64>(0h0)
connect rom[15], UInt<64>(0h0)
connect rom[16], UInt<64>(0h5a283f81ff06f)
connect rom[17], UInt<64>(0h251513fe029ee3)
connect rom[18], UInt<64>(0h5a02300b505b3)
connect rom[19], UInt<64>(0h5350300001537)
connect rom[20], UInt<64>(0hf140257334151073)
connect rom[21], UInt<64>(0h185859300000597)
connect rom[22], UInt<64>(0h3006307308000613)
connect rom[23], UInt<64>(0h1330200073)
connect rom[24], UInt<64>(0h100e0000edfe0dd0)
connect rom[25], UInt<64>(0hb00b000038000000)
connect rom[26], UInt<64>(0h1100000028000000)
connect rom[27], UInt<64>(0h10000000)
connect rom[28], UInt<64>(0h780b000060020000)
connect rom[29], UInt<64>(0h0)
connect rom[30], UInt<64>(0h0)
connect rom[31], UInt<64>(0h1000000)
connect rom[32], UInt<64>(0h400000003000000)
connect rom[33], UInt<64>(0h100000000000000)
connect rom[34], UInt<64>(0h400000003000000)
connect rom[35], UInt<64>(0h10000000f000000)
connect rom[36], UInt<64>(0h1500000003000000)
connect rom[37], UInt<64>(0h2d6263751b000000)
connect rom[38], UInt<64>(0h706968632c726162)
connect rom[39], UInt<64>(0h7665642d64726179)
connect rom[40], UInt<64>(0h300000000000000)
connect rom[41], UInt<64>(0h2600000011000000)
connect rom[42], UInt<64>(0h2c7261622d626375)
connect rom[43], UInt<64>(0h6472617970696863)
connect rom[44], UInt<64>(0h100000000000000)
connect rom[45], UInt<64>(0h73657361696c61)
connect rom[46], UInt<64>(0h1500000003000000)
connect rom[47], UInt<64>(0h636f732f2c000000)
connect rom[48], UInt<64>(0h406c61697265732f)
connect rom[49], UInt<64>(0h3030303032303031)
connect rom[50], UInt<64>(0h200000000000000)
connect rom[51], UInt<64>(0h736f686301000000)
connect rom[52], UInt<64>(0h300000000006e65)
connect rom[53], UInt<64>(0h3400000015000000)
connect rom[54], UInt<64>(0h7265732f636f732f)
connect rom[55], UInt<64>(0h32303031406c6169)
connect rom[56], UInt<64>(0h30303030)
connect rom[57], UInt<64>(0h100000002000000)
connect rom[58], UInt<64>(0h73757063)
connect rom[59], UInt<64>(0h400000003000000)
connect rom[60], UInt<64>(0h100000000000000)
connect rom[61], UInt<64>(0h400000003000000)
connect rom[62], UInt<64>(0hf000000)
connect rom[63], UInt<64>(0h400000003000000)
connect rom[64], UInt<64>(0h20a1070040000000)
connect rom[65], UInt<64>(0h4075706301000000)
connect rom[66], UInt<64>(0h300000000000030)
connect rom[67], UInt<64>(0h5300000004000000)
connect rom[68], UInt<64>(0h300000000000000)
connect rom[69], UInt<64>(0h1b00000015000000)
connect rom[70], UInt<64>(0h722c657669666973)
connect rom[71], UInt<64>(0h72003074656b636f)
connect rom[72], UInt<64>(0h76637369)
connect rom[73], UInt<64>(0h400000003000000)
connect rom[74], UInt<64>(0h4000000063000000)
connect rom[75], UInt<64>(0h400000003000000)
connect rom[76], UInt<64>(0h4000000076000000)
connect rom[77], UInt<64>(0h400000003000000)
connect rom[78], UInt<64>(0h80000083000000)
connect rom[79], UInt<64>(0h400000003000000)
connect rom[80], UInt<64>(0h100000090000000)
connect rom[81], UInt<64>(0h400000003000000)
connect rom[82], UInt<64>(0h200000009b000000)
connect rom[83], UInt<64>(0h400000003000000)
connect rom[84], UInt<64>(0h757063a6000000)
connect rom[85], UInt<64>(0h400000003000000)
connect rom[86], UInt<64>(0h1000000b2000000)
connect rom[87], UInt<64>(0h400000003000000)
connect rom[88], UInt<64>(0h40000000d1000000)
connect rom[89], UInt<64>(0h400000003000000)
connect rom[90], UInt<64>(0h40000000e4000000)
connect rom[91], UInt<64>(0h400000003000000)
connect rom[92], UInt<64>(0h800000f1000000)
connect rom[93], UInt<64>(0h400000003000000)
connect rom[94], UInt<64>(0h1000000fe000000)
connect rom[95], UInt<64>(0h400000003000000)
connect rom[96], UInt<64>(0h2000000009010000)
connect rom[97], UInt<64>(0hb00000003000000)
connect rom[98], UInt<64>(0h6373697214010000)
connect rom[99], UInt<64>(0h393376732c76)
connect rom[100], UInt<64>(0h400000003000000)
connect rom[101], UInt<64>(0h10000001d010000)
connect rom[102], UInt<64>(0h400000003000000)
connect rom[103], UInt<64>(0h2e010000)
connect rom[104], UInt<64>(0h3800000003000000)
connect rom[105], UInt<64>(0h3436767232010000)
connect rom[106], UInt<64>(0h7a62636466616d69)
connect rom[107], UInt<64>(0h66697a5f72736369)
connect rom[108], UInt<64>(0h697a5f6965636e65)
connect rom[109], UInt<64>(0h5f68667a5f6d7068)
connect rom[110], UInt<64>(0h5f62627a5f61627a)
connect rom[111], UInt<64>(0h636f72785f73627a)
connect rom[112], UInt<64>(0h30000000074656b)
connect rom[113], UInt<64>(0h3c01000004000000)
connect rom[114], UInt<64>(0h300000004000000)
connect rom[115], UInt<64>(0h5101000004000000)
connect rom[116], UInt<64>(0h300000008000000)
connect rom[117], UInt<64>(0h6201000005000000)
connect rom[118], UInt<64>(0h79616b6f)
connect rom[119], UInt<64>(0h400000003000000)
connect rom[120], UInt<64>(0h20a1070040000000)
connect rom[121], UInt<64>(0h3000000)
connect rom[122], UInt<64>(0h100000069010000)
connect rom[123], UInt<64>(0h7075727265746e69)
connect rom[124], UInt<64>(0h6f72746e6f632d74)
connect rom[125], UInt<64>(0h72656c6c)
connect rom[126], UInt<64>(0h400000003000000)
connect rom[127], UInt<64>(0h100000073010000)
connect rom[128], UInt<64>(0hf00000003000000)
connect rom[129], UInt<64>(0h637369721b000000)
connect rom[130], UInt<64>(0h6e692d7570632c76)
connect rom[131], UInt<64>(0h300000000006374)
connect rom[132], UInt<64>(0h8401000000000000)
connect rom[133], UInt<64>(0h400000003000000)
connect rom[134], UInt<64>(0h400000099010000)
connect rom[135], UInt<64>(0h200000002000000)
connect rom[136], UInt<64>(0h100000002000000)
connect rom[137], UInt<64>(0h66697468)
connect rom[138], UInt<64>(0ha00000003000000)
connect rom[139], UInt<64>(0h2c6263751b000000)
connect rom[140], UInt<64>(0h3066697468)
connect rom[141], UInt<64>(0h100000002000000)
connect rom[142], UInt<64>(0h384079726f6d656d)
connect rom[143], UInt<64>(0h303030303030)
connect rom[144], UInt<64>(0h700000003000000)
connect rom[145], UInt<64>(0h6f6d656da6000000)
connect rom[146], UInt<64>(0h300000000007972)
connect rom[147], UInt<64>(0h2e01000008000000)
connect rom[148], UInt<64>(0h10000000008)
connect rom[149], UInt<64>(0h900000003000000)
connect rom[150], UInt<64>(0h6173696462010000)
connect rom[151], UInt<64>(0h64656c62)
connect rom[152], UInt<64>(0h400000003000000)
connect rom[153], UInt<64>(0h300000099010000)
connect rom[154], UInt<64>(0h100000002000000)
connect rom[155], UInt<64>(0h384079726f6d656d)
connect rom[156], UInt<64>(0h30303030303030)
connect rom[157], UInt<64>(0h700000003000000)
connect rom[158], UInt<64>(0h6f6d656da6000000)
connect rom[159], UInt<64>(0h300000000007972)
connect rom[160], UInt<64>(0h2e01000008000000)
connect rom[161], UInt<64>(0h1000000080)
connect rom[162], UInt<64>(0h400000003000000)
connect rom[163], UInt<64>(0h200000099010000)
connect rom[164], UInt<64>(0h100000002000000)
connect rom[165], UInt<64>(0h300000000636f73)
connect rom[166], UInt<64>(0h4000000)
connect rom[167], UInt<64>(0h300000001000000)
connect rom[168], UInt<64>(0hf00000004000000)
connect rom[169], UInt<64>(0h300000001000000)
connect rom[170], UInt<64>(0h1b00000020000000)
connect rom[171], UInt<64>(0h2c7261622d626375)
connect rom[172], UInt<64>(0h6472617970696863)
connect rom[173], UInt<64>(0h6d697300636f732d)
connect rom[174], UInt<64>(0h7375622d656c70)
connect rom[175], UInt<64>(0h3000000)
connect rom[176], UInt<64>(0h1000000a1010000)
connect rom[177], UInt<64>(0h6464612d746f6f62)
connect rom[178], UInt<64>(0h6765722d73736572)
connect rom[179], UInt<64>(0h3030303140)
connect rom[180], UInt<64>(0h800000003000000)
connect rom[181], UInt<64>(0h1000002e010000)
connect rom[182], UInt<64>(0h300000000100000)
connect rom[183], UInt<64>(0ha801000008000000)
connect rom[184], UInt<64>(0h6c6f72746e6f63)
connect rom[185], UInt<64>(0h100000002000000)
connect rom[186], UInt<64>(0h6f632d6568636163)
connect rom[187], UInt<64>(0h72656c6c6f72746e)
connect rom[188], UInt<64>(0h3030303031303240)
connect rom[189], UInt<64>(0h300000000000000)
connect rom[190], UInt<64>(0h6500000004000000)
connect rom[191], UInt<64>(0h300000040000000)
connect rom[192], UInt<64>(0hb201000004000000)
connect rom[193], UInt<64>(0h300000002000000)
connect rom[194], UInt<64>(0h7800000004000000)
connect rom[195], UInt<64>(0h300000000040000)
connect rom[196], UInt<64>(0h8500000004000000)
connect rom[197], UInt<64>(0h300000000000800)
connect rom[198], UInt<64>(0hbe01000000000000)
connect rom[199], UInt<64>(0h1d00000003000000)
connect rom[200], UInt<64>(0h696669731b000000)
connect rom[201], UInt<64>(0h756c636e692c6576)
connect rom[202], UInt<64>(0h6863616365766973)
connect rom[203], UInt<64>(0h6568636163003065)
connect rom[204], UInt<64>(0h300000000000000)
connect rom[205], UInt<64>(0h1d01000008000000)
connect rom[206], UInt<64>(0h300000002000000)
connect rom[207], UInt<64>(0h800000003000000)
connect rom[208], UInt<64>(0h1022e010000)
connect rom[209], UInt<64>(0h300000000100000)
connect rom[210], UInt<64>(0ha801000008000000)
connect rom[211], UInt<64>(0h6c6f72746e6f63)
connect rom[212], UInt<64>(0h400000003000000)
connect rom[213], UInt<64>(0h7000000cc010000)
connect rom[214], UInt<64>(0h400000003000000)
connect rom[215], UInt<64>(0h100000099010000)
connect rom[216], UInt<64>(0h100000002000000)
connect rom[217], UInt<64>(0h6f6c635f73756263)
connect rom[218], UInt<64>(0h300000000006b63)
connect rom[219], UInt<64>(0hde01000004000000)
connect rom[220], UInt<64>(0h300000000000000)
connect rom[221], UInt<64>(0h5300000004000000)
connect rom[222], UInt<64>(0h30000000065cd1d)
connect rom[223], UInt<64>(0heb0100000b000000)
connect rom[224], UInt<64>(0h6f6c635f73756263)
connect rom[225], UInt<64>(0h300000000006b63)
connect rom[226], UInt<64>(0h1b0000000c000000)
connect rom[227], UInt<64>(0h6c632d6465786966)
connect rom[228], UInt<64>(0h2000000006b636f)
connect rom[229], UInt<64>(0h6e696c6301000000)
connect rom[230], UInt<64>(0h3030303030324074)
connect rom[231], UInt<64>(0h300000000000030)
connect rom[232], UInt<64>(0h1b0000000d000000)
connect rom[233], UInt<64>(0h6c632c7663736972)
connect rom[234], UInt<64>(0h30746e69)
connect rom[235], UInt<64>(0h1000000003000000)
connect rom[236], UInt<64>(0h4000000fe010000)
connect rom[237], UInt<64>(0h400000003000000)
connect rom[238], UInt<64>(0h300000007000000)
connect rom[239], UInt<64>(0h2e01000008000000)
connect rom[240], UInt<64>(0h10000000002)
connect rom[241], UInt<64>(0h800000003000000)
connect rom[242], UInt<64>(0h746e6f63a8010000)
connect rom[243], UInt<64>(0h2000000006c6f72)
connect rom[244], UInt<64>(0h636f6c6301000000)
connect rom[245], UInt<64>(0h4072657461672d6b)
connect rom[246], UInt<64>(0h303030303031)
connect rom[247], UInt<64>(0h800000003000000)
connect rom[248], UInt<64>(0h10002e010000)
connect rom[249], UInt<64>(0h300000000100000)
connect rom[250], UInt<64>(0ha801000008000000)
connect rom[251], UInt<64>(0h6c6f72746e6f63)
connect rom[252], UInt<64>(0h100000002000000)
connect rom[253], UInt<64>(0h6f632d6775626564)
connect rom[254], UInt<64>(0h72656c6c6f72746e)
connect rom[255], UInt<64>(0h300000000003040)
connect rom[256], UInt<64>(0h1b00000021000000)
connect rom[257], UInt<64>(0h642c657669666973)
connect rom[258], UInt<64>(0h3331302d67756265)
connect rom[259], UInt<64>(0h642c766373697200)
connect rom[260], UInt<64>(0h3331302d67756265)
connect rom[261], UInt<64>(0h300000000000000)
connect rom[262], UInt<64>(0h1202000005000000)
connect rom[263], UInt<64>(0h6761746a)
connect rom[264], UInt<64>(0h800000003000000)
connect rom[265], UInt<64>(0h4000000fe010000)
connect rom[266], UInt<64>(0h3000000ffff0000)
connect rom[267], UInt<64>(0h2e01000008000000)
connect rom[268], UInt<64>(0h10000000000000)
connect rom[269], UInt<64>(0h800000003000000)
connect rom[270], UInt<64>(0h746e6f63a8010000)
connect rom[271], UInt<64>(0h2000000006c6f72)
connect rom[272], UInt<64>(0h6f72726501000000)
connect rom[273], UInt<64>(0h6563697665642d72)
connect rom[274], UInt<64>(0h3030303340)
connect rom[275], UInt<64>(0he00000003000000)
connect rom[276], UInt<64>(0h696669731b000000)
connect rom[277], UInt<64>(0h726f7272652c6576)
connect rom[278], UInt<64>(0h300000000000030)
connect rom[279], UInt<64>(0h2e01000008000000)
connect rom[280], UInt<64>(0h10000000300000)
connect rom[281], UInt<64>(0h100000002000000)
connect rom[282], UInt<64>(0h6f6c635f73756266)
connect rom[283], UInt<64>(0h300000000006b63)
connect rom[284], UInt<64>(0hde01000004000000)
connect rom[285], UInt<64>(0h300000000000000)
connect rom[286], UInt<64>(0h5300000004000000)
connect rom[287], UInt<64>(0h30000000065cd1d)
connect rom[288], UInt<64>(0heb0100000b000000)
connect rom[289], UInt<64>(0h6f6c635f73756266)
connect rom[290], UInt<64>(0h300000000006b63)
connect rom[291], UInt<64>(0h1b0000000c000000)
connect rom[292], UInt<64>(0h6c632d6465786966)
connect rom[293], UInt<64>(0h2000000006b636f)
connect rom[294], UInt<64>(0h65746e6901000000)
connect rom[295], UInt<64>(0h6f632d7470757272)
connect rom[296], UInt<64>(0h72656c6c6f72746e)
connect rom[297], UInt<64>(0h3030303030306340)
connect rom[298], UInt<64>(0h300000000000000)
connect rom[299], UInt<64>(0h7301000004000000)
connect rom[300], UInt<64>(0h300000001000000)
connect rom[301], UInt<64>(0h1b0000000c000000)
connect rom[302], UInt<64>(0h6c702c7663736972)
connect rom[303], UInt<64>(0h300000000306369)
connect rom[304], UInt<64>(0h8401000000000000)
connect rom[305], UInt<64>(0h1000000003000000)
connect rom[306], UInt<64>(0h4000000fe010000)
connect rom[307], UInt<64>(0h40000000b000000)
connect rom[308], UInt<64>(0h300000009000000)
connect rom[309], UInt<64>(0h2e01000008000000)
connect rom[310], UInt<64>(0h40000000c)
connect rom[311], UInt<64>(0h800000003000000)
connect rom[312], UInt<64>(0h746e6f63a8010000)
connect rom[313], UInt<64>(0h3000000006c6f72)
connect rom[314], UInt<64>(0h1f02000004000000)
connect rom[315], UInt<64>(0h300000001000000)
connect rom[316], UInt<64>(0h3202000004000000)
connect rom[317], UInt<64>(0h300000001000000)
connect rom[318], UInt<64>(0h9901000004000000)
connect rom[319], UInt<64>(0h200000006000000)
connect rom[320], UInt<64>(0h7375626d01000000)
connect rom[321], UInt<64>(0h6b636f6c635f)
connect rom[322], UInt<64>(0h400000003000000)
connect rom[323], UInt<64>(0hde010000)
connect rom[324], UInt<64>(0h400000003000000)
connect rom[325], UInt<64>(0h65cd1d53000000)
connect rom[326], UInt<64>(0hb00000003000000)
connect rom[327], UInt<64>(0h7375626deb010000)
connect rom[328], UInt<64>(0h6b636f6c635f)
connect rom[329], UInt<64>(0hc00000003000000)
connect rom[330], UInt<64>(0h657869661b000000)
connect rom[331], UInt<64>(0h6b636f6c632d64)
connect rom[332], UInt<64>(0h100000002000000)
connect rom[333], UInt<64>(0h6f6c635f73756270)
connect rom[334], UInt<64>(0h300000000006b63)
connect rom[335], UInt<64>(0hde01000004000000)
connect rom[336], UInt<64>(0h300000000000000)
connect rom[337], UInt<64>(0h5300000004000000)
connect rom[338], UInt<64>(0h30000000065cd1d)
connect rom[339], UInt<64>(0heb0100000b000000)
connect rom[340], UInt<64>(0h6f6c635f73756270)
connect rom[341], UInt<64>(0h300000000006b63)
connect rom[342], UInt<64>(0h1b0000000c000000)
connect rom[343], UInt<64>(0h6c632d6465786966)
connect rom[344], UInt<64>(0h3000000006b636f)
connect rom[345], UInt<64>(0h9901000004000000)
connect rom[346], UInt<64>(0h200000005000000)
connect rom[347], UInt<64>(0h406d6f7201000000)
connect rom[348], UInt<64>(0h3030303031)
connect rom[349], UInt<64>(0hc00000003000000)
connect rom[350], UInt<64>(0h696669731b000000)
connect rom[351], UInt<64>(0h306d6f722c6576)
connect rom[352], UInt<64>(0h800000003000000)
connect rom[353], UInt<64>(0h1002e010000)
connect rom[354], UInt<64>(0h300000000000100)
connect rom[355], UInt<64>(0ha801000004000000)
connect rom[356], UInt<64>(0h2000000006d656d)
connect rom[357], UInt<64>(0h7375627301000000)
connect rom[358], UInt<64>(0h6b636f6c635f)
connect rom[359], UInt<64>(0h400000003000000)
connect rom[360], UInt<64>(0hde010000)
connect rom[361], UInt<64>(0h400000003000000)
connect rom[362], UInt<64>(0h65cd1d53000000)
connect rom[363], UInt<64>(0hb00000003000000)
connect rom[364], UInt<64>(0h73756273eb010000)
connect rom[365], UInt<64>(0h6b636f6c635f)
connect rom[366], UInt<64>(0hc00000003000000)
connect rom[367], UInt<64>(0h657869661b000000)
connect rom[368], UInt<64>(0h6b636f6c632d64)
connect rom[369], UInt<64>(0h100000002000000)
connect rom[370], UInt<64>(0h31406c6169726573)
connect rom[371], UInt<64>(0h30303030323030)
connect rom[372], UInt<64>(0h400000003000000)
connect rom[373], UInt<64>(0h50000003d020000)
connect rom[374], UInt<64>(0hd00000003000000)
connect rom[375], UInt<64>(0h696669731b000000)
connect rom[376], UInt<64>(0h30747261752c6576)
connect rom[377], UInt<64>(0h300000000000000)
connect rom[378], UInt<64>(0h4402000004000000)
connect rom[379], UInt<64>(0h300000006000000)
connect rom[380], UInt<64>(0h5502000004000000)
connect rom[381], UInt<64>(0h300000001000000)
connect rom[382], UInt<64>(0h2e01000008000000)
connect rom[383], UInt<64>(0h10000000000210)
connect rom[384], UInt<64>(0h800000003000000)
connect rom[385], UInt<64>(0h746e6f63a8010000)
connect rom[386], UInt<64>(0h2000000006c6f72)
connect rom[387], UInt<64>(0h656c697401000000)
connect rom[388], UInt<64>(0h732d74657365722d)
connect rom[389], UInt<64>(0h3131407265747465)
connect rom[390], UInt<64>(0h30303030)
connect rom[391], UInt<64>(0h800000003000000)
connect rom[392], UInt<64>(0h11002e010000)
connect rom[393], UInt<64>(0h300000000100000)
connect rom[394], UInt<64>(0ha801000008000000)
connect rom[395], UInt<64>(0h6c6f72746e6f63)
connect rom[396], UInt<64>(0h200000002000000)
connect rom[397], UInt<64>(0h900000002000000)
connect rom[398], UInt<64>(0h7373657264646123)
connect rom[399], UInt<64>(0h2300736c6c65632d)
connect rom[400], UInt<64>(0h6c65632d657a6973)
connect rom[401], UInt<64>(0h61706d6f6300736c)
connect rom[402], UInt<64>(0h6f6d00656c626974)
connect rom[403], UInt<64>(0h69726573006c6564)
connect rom[404], UInt<64>(0h6f64747300306c61)
connect rom[405], UInt<64>(0h687461702d7475)
connect rom[406], UInt<64>(0h65736162656d6974)
connect rom[407], UInt<64>(0h6e6575716572662d)
connect rom[408], UInt<64>(0h6b636f6c63007963)
connect rom[409], UInt<64>(0h6e6575716572662d)
connect rom[410], UInt<64>(0h6361632d64007963)
connect rom[411], UInt<64>(0h6b636f6c622d6568)
connect rom[412], UInt<64>(0h2d6400657a69732d)
connect rom[413], UInt<64>(0h65732d6568636163)
connect rom[414], UInt<64>(0h6361632d64007374)
connect rom[415], UInt<64>(0h657a69732d6568)
connect rom[416], UInt<64>(0h65732d626c742d64)
connect rom[417], UInt<64>(0h626c742d64007374)
connect rom[418], UInt<64>(0h656400657a69732d)
connect rom[419], UInt<64>(0h7079745f65636976)
connect rom[420], UInt<64>(0h6177647261680065)
connect rom[421], UInt<64>(0h2d636578652d6572)
connect rom[422], UInt<64>(0h696f706b61657262)
connect rom[423], UInt<64>(0h746e756f632d746e)
connect rom[424], UInt<64>(0h65686361632d6900)
connect rom[425], UInt<64>(0h732d6b636f6c622d)
connect rom[426], UInt<64>(0h61632d6900657a69)
connect rom[427], UInt<64>(0h737465732d656863)
connect rom[428], UInt<64>(0h65686361632d6900)
connect rom[429], UInt<64>(0h2d6900657a69732d)
connect rom[430], UInt<64>(0h737465732d626c74)
connect rom[431], UInt<64>(0h732d626c742d6900)
connect rom[432], UInt<64>(0h2d756d6d00657a69)
connect rom[433], UInt<64>(0h78656e0065707974)
connect rom[434], UInt<64>(0h2d6c6576656c2d74)
connect rom[435], UInt<64>(0h6572006568636163)
connect rom[436], UInt<64>(0h2c76637369720067)
connect rom[437], UInt<64>(0h6373697200617369)
connect rom[438], UInt<64>(0h617267706d702c76)
connect rom[439], UInt<64>(0h79746972616c756e)
connect rom[440], UInt<64>(0h702c766373697200)
connect rom[441], UInt<64>(0h6e6f69676572706d)
connect rom[442], UInt<64>(0h7375746174730073)
connect rom[443], UInt<64>(0h6c70732d626c7400)
connect rom[444], UInt<64>(0h65746e6923007469)
connect rom[445], UInt<64>(0h65632d7470757272)
connect rom[446], UInt<64>(0h65746e6900736c6c)
connect rom[447], UInt<64>(0h6f632d7470757272)
connect rom[448], UInt<64>(0h72656c6c6f72746e)
connect rom[449], UInt<64>(0h656c646e61687000)
connect rom[450], UInt<64>(0h7365676e617200)
connect rom[451], UInt<64>(0h656d616e2d676572)
connect rom[452], UInt<64>(0h2d65686361630073)
connect rom[453], UInt<64>(0h6163006c6576656c)
connect rom[454], UInt<64>(0h66696e752d656863)
connect rom[455], UInt<64>(0h6966697300646569)
connect rom[456], UInt<64>(0h2d7268736d2c6576)
connect rom[457], UInt<64>(0h632300746e756f63)
connect rom[458], UInt<64>(0h6c65632d6b636f6c)
connect rom[459], UInt<64>(0h6b636f6c6300736c)
connect rom[460], UInt<64>(0h2d74757074756f2d)
connect rom[461], UInt<64>(0h6e690073656d616e)
connect rom[462], UInt<64>(0h7374707572726574)
connect rom[463], UInt<64>(0h65646e657478652d)
connect rom[464], UInt<64>(0h2d67756265640064)
connect rom[465], UInt<64>(0h7200686361747461)
connect rom[466], UInt<64>(0h78616d2c76637369)
connect rom[467], UInt<64>(0h7469726f6972702d)
connect rom[468], UInt<64>(0h2c76637369720079)
connect rom[469], UInt<64>(0h6f6c63007665646e)
connect rom[470], UInt<64>(0h65746e6900736b63)
connect rom[471], UInt<64>(0h61702d7470757272)
connect rom[472], UInt<64>(0h746e6900746e6572)
connect rom[473], UInt<64>(0h73747075727265)
connect rom[474], UInt<64>(0h0)
connect rom[475], UInt<64>(0h0)
connect rom[476], UInt<64>(0h0)
connect rom[477], UInt<64>(0h0)
connect rom[478], UInt<64>(0h0)
connect rom[479], UInt<64>(0h0)
connect rom[480], UInt<64>(0h0)
connect rom[481], UInt<64>(0h0)
connect rom[482], UInt<64>(0h0)
connect rom[483], UInt<64>(0h0)
connect rom[484], UInt<64>(0h0)
connect rom[485], UInt<64>(0h0)
connect rom[486], UInt<64>(0h0)
connect rom[487], UInt<64>(0h0)
connect rom[488], UInt<64>(0h0)
connect rom[489], UInt<64>(0h0)
connect rom[490], UInt<64>(0h0)
connect rom[491], UInt<64>(0h0)
connect rom[492], UInt<64>(0h0)
connect rom[493], UInt<64>(0h0)
connect rom[494], UInt<64>(0h0)
connect rom[495], UInt<64>(0h0)
connect rom[496], UInt<64>(0h0)
connect rom[497], UInt<64>(0h0)
connect rom[498], UInt<64>(0h0)
connect rom[499], UInt<64>(0h0)
connect rom[500], UInt<64>(0h0)
connect rom[501], UInt<64>(0h0)
connect rom[502], UInt<64>(0h0)
connect rom[503], UInt<64>(0h0)
connect rom[504], UInt<64>(0h0)
connect rom[505], UInt<64>(0h0)
connect rom[506], UInt<64>(0h0)
connect rom[507], UInt<64>(0h0)
connect rom[508], UInt<64>(0h0)
connect rom[509], UInt<64>(0h0)
connect rom[510], UInt<64>(0h0)
connect rom[511], UInt<64>(0h0)
connect nodeIn.d.valid, nodeIn.a.valid
connect nodeIn.a.ready, nodeIn.d.ready
node index = bits(nodeIn.a.bits.address, 11, 3)
node high = bits(nodeIn.a.bits.address, 15, 12)
node _nodeIn_d_bits_T = orr(high)
node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index])
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h1)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, nodeIn.a.bits.size
connect nodeIn_d_bits_d.source, nodeIn.a.bits.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h73747075727265,
64'h746E6900746E6572,
64'h61702D7470757272,
64'h65746E6900736B63,
64'h6F6C63007665646E,
64'h2C76637369720079,
64'h7469726F6972702D,
64'h78616D2C76637369,
64'h7200686361747461,
64'h2D67756265640064,
64'h65646E657478652D,
64'h7374707572726574,
64'h6E690073656D616E,
64'h2D74757074756F2D,
64'h6B636F6C6300736C,
64'h6C65632D6B636F6C,
64'h632300746E756F63,
64'h2D7268736D2C6576,
64'h6966697300646569,
64'h66696E752D656863,
64'h6163006C6576656C,
64'h2D65686361630073,
64'h656D616E2D676572,
64'h7365676E617200,
64'h656C646E61687000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6900736C6C,
64'h65632D7470757272,
64'h65746E6923007469,
64'h6C70732D626C7400,
64'h7375746174730073,
64'h6E6F69676572706D,
64'h702C766373697200,
64'h79746972616C756E,
64'h617267706D702C76,
64'h6373697200617369,
64'h2C76637369720067,
64'h6572006568636163,
64'h2D6C6576656C2D74,
64'h78656E0065707974,
64'h2D756D6D00657A69,
64'h732D626C742D6900,
64'h737465732D626C74,
64'h2D6900657A69732D,
64'h65686361632D6900,
64'h737465732D656863,
64'h61632D6900657A69,
64'h732D6B636F6C622D,
64'h65686361632D6900,
64'h746E756F632D746E,
64'h696F706B61657262,
64'h2D636578652D6572,
64'h6177647261680065,
64'h7079745F65636976,
64'h656400657A69732D,
64'h626C742D64007374,
64'h65732D626C742D64,
64'h657A69732D6568,
64'h6361632D64007374,
64'h65732D6568636163,
64'h2D6400657A69732D,
64'h6B636F6C622D6568,
64'h6361632D64007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
64'h200000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h11002E010000,
64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000210,
64'h2E01000008000000,
64'h300000001000000,
64'h5502000004000000,
64'h300000006000000,
64'h4402000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h50000003D020000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756273EB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
64'hA801000004000000,
64'h300000000000100,
64'h1002E010000,
64'h800000003000000,
64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000005000000,
64'h9901000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h7375626DEB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626D01000000,
64'h200000006000000,
64'h9901000004000000,
64'h300000001000000,
64'h3202000004000000,
64'h300000001000000,
64'h1F02000004000000,
64'h3000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h40000000C,
64'h2E01000008000000,
64'h300000009000000,
64'h40000000B000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h8401000000000000,
64'h300000000306369,
64'h6C702C7663736972,
64'h1B0000000C000000,
64'h300000001000000,
64'h7301000004000000,
64'h300000000000000,
64'h3030303030306340,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'h100000002000000,
64'h10000000300000,
64'h2E01000008000000,
64'h300000000000030,
64'h726F7272652C6576,
64'h696669731B000000,
64'hE00000003000000,
64'h3030303340,
64'h6563697665642D72,
64'h6F72726501000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000000,
64'h2E01000008000000,
64'h3000000FFFF0000,
64'h4000000FE010000,
64'h800000003000000,
64'h6761746A,
64'h1202000005000000,
64'h300000000000000,
64'h3331302D67756265,
64'h642C766373697200,
64'h3331302D67756265,
64'h642C657669666973,
64'h1B00000021000000,
64'h300000000003040,
64'h72656C6C6F72746E,
64'h6F632D6775626564,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h10002E010000,
64'h800000003000000,
64'h303030303031,
64'h4072657461672D6B,
64'h636F6C6301000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000002,
64'h2E01000008000000,
64'h300000007000000,
64'h400000003000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h30746E69,
64'h6C632C7663736972,
64'h1B0000000D000000,
64'h300000000000030,
64'h3030303030324074,
64'h6E696C6301000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'h100000002000000,
64'h100000099010000,
64'h400000003000000,
64'h7000000CC010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1022E010000,
64'h800000003000000,
64'h300000002000000,
64'h1D01000008000000,
64'h300000000000000,
64'h6568636163003065,
64'h6863616365766973,
64'h756C636E692C6576,
64'h696669731B000000,
64'h1D00000003000000,
64'hBE01000000000000,
64'h300000000000800,
64'h8500000004000000,
64'h300000000040000,
64'h7800000004000000,
64'h300000002000000,
64'hB201000004000000,
64'h300000040000000,
64'h6500000004000000,
64'h300000000000000,
64'h3030303031303240,
64'h72656C6C6F72746E,
64'h6F632D6568636163,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1000002E010000,
64'h800000003000000,
64'h3030303140,
64'h6765722D73736572,
64'h6464612D746F6F62,
64'h1000000A1010000,
64'h3000000,
64'h7375622D656C70,
64'h6D697300636F732D,
64'h6472617970696863,
64'h2C7261622D626375,
64'h1B00000020000000,
64'h300000001000000,
64'hF00000004000000,
64'h300000001000000,
64'h4000000,
64'h300000000636F73,
64'h100000002000000,
64'h200000099010000,
64'h400000003000000,
64'h1000000080,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h30303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'h400000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h2E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'h780B000060020000,
64'h10000000,
64'h1100000028000000,
64'hB00B000038000000,
64'h100E0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'h100E0000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hB00B000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'h780B000060020000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h4000000063000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h4000000076000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h80000083000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h100000090000000; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h200000009B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'h757063A6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h1000000B2000000; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h40000000D1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h40000000E4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h800000F1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'h1000000FE000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'h2000000009010000; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'h6373697214010000; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h393376732C76; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'h10000001D010000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h2E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h3800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h3436767232010000; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h7A62636466616D69; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h66697A5F72736369; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h636F72785F73627A; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h30000000074656B; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h3C01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h5101000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h6201000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h100000069010000; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h72656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h100000073010000; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'hF00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h300000000006374; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h400000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h66697468; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'hA00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'h2C6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h3066697468; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h10000000008; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'h900000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'h6173696462010000; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h64656C62; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'h300000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h30303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h1000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h200000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h300000000636F73; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'h4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'hF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h1B00000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h6D697300636F732D; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h7375622D656C70; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h1000000A1010000; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'h6765722D73736572; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'h3030303140; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'h1000002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h6F632D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'h3030303031303240; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'h6500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'hB201000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h7800000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'h300000000040000; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'h8500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h300000000000800; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'hBE01000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h1D00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h756C636E692C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'h6863616365766973; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h6568636163003065; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h1D01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'h1022E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h7000000CC010000; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h100000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h6E696C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h3030303030324074; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'h1B0000000D000000; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'h6C632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h30746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h300000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h10000000002; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h636F6C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h4072657461672D6B; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h303030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'h10002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h6F632D6775626564; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h300000000003040; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'h1B00000021000000; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h642C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h642C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'h1202000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h6761746A; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'h10000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h6F72726501000000; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'h6563697665642D72; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'h3030303340; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'hE00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h726F7272652C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h10000000300000; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h3030303030306340; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h7301000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h6C702C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h300000000306369; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'h40000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h300000009000000; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h40000000C; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h3000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h1F02000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'h3202000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'h200000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h7375626D01000000; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'h7375626DEB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h200000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'h1002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'hA801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'h73756273EB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h50000003D020000; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h4402000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h300000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h5502000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'h11002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h6361632D64007963; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h65732D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h6361632D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h657A69732D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h65732D626C742D64; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h626C742D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'h656400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h7079745F65636976; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h6177647261680065; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h2D636578652D6572; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h696F706B61657262; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h746E756F632D746E; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h61632D6900657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h737465732D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h737465732D626C74; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h732D626C742D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h78656E0065707974; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'h6572006568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h2C76637369720067; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h6373697200617369; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h617267706D702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h79746972616C756E; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h702C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h7375746174730073; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h65746E6923007469; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h65632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h656C646E61687000; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h7365676E617200; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h656D616E2D676572; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h2D65686361630073; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h6163006C6576656C; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h66696E752D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h6966697300646569; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h632300746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h6E690073656D616E; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h7374707572726574; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'h65646E657478652D; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h2D67756265640064; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h7200686361747461; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h78616D2C76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h7469726F6972702D; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h2C76637369720079; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h65746E6900736B63; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h61702D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h746E6900746E6572; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h73747075727265; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34]
wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_50 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_178 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], chosen_oh : UInt<4>[1]}
regreset lock_0 : UInt<4>, clock, reset, UInt<4>(0h0)
node unassigned_lo = cat(io.in[1].valid, io.in[0].valid)
node unassigned_hi = cat(io.in[3].valid, io.in[2].valid)
node _unassigned_T = cat(unassigned_hi, unassigned_lo)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire choices : UInt<4>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = bits(_sel_T_2, 4, 4)
node _sel_T_8 = bits(_sel_T_2, 5, 5)
node _sel_T_9 = bits(_sel_T_2, 6, 6)
node _sel_T_10 = bits(_sel_T_2, 7, 7)
node _sel_T_11 = mux(_sel_T_10, UInt<8>(0h80), UInt<8>(0h0))
node _sel_T_12 = mux(_sel_T_9, UInt<8>(0h40), _sel_T_11)
node _sel_T_13 = mux(_sel_T_8, UInt<8>(0h20), _sel_T_12)
node _sel_T_14 = mux(_sel_T_7, UInt<8>(0h10), _sel_T_13)
node _sel_T_15 = mux(_sel_T_6, UInt<8>(0h8), _sel_T_14)
node _sel_T_16 = mux(_sel_T_5, UInt<8>(0h4), _sel_T_15)
node _sel_T_17 = mux(_sel_T_4, UInt<8>(0h2), _sel_T_16)
node sel = mux(_sel_T_3, UInt<8>(0h1), _sel_T_17)
node _choices_0_T = shr(sel, 4)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = bits(_T_1, 2, 2)
node _T_5 = bits(_T_1, 3, 3)
node _T_6 = mux(_T_5, UInt<4>(0h8), UInt<4>(0h0))
node _T_7 = mux(_T_4, UInt<4>(0h4), _T_6)
node _T_8 = mux(_T_3, UInt<4>(0h2), _T_7)
node _T_9 = mux(_T_2, UInt<4>(0h1), _T_8)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
connect io.in[2].ready, UInt<1>(0h0)
connect io.in[3].ready, UInt<1>(0h0)
node in_tails_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail)
node in_tails_hi = cat(io.in[3].bits.tail, io.in[2].bits.tail)
node in_tails = cat(in_tails_hi, in_tails_lo)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4)
node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6)
node in_valids_lo = cat(_in_valids_T_3, _in_valids_T_1)
node in_valids_hi = cat(_in_valids_T_7, _in_valids_T_5)
node in_valids = cat(in_valids_hi, in_valids_lo)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<4>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
node _io_out_0_bits_T_2 = bits(chosen, 2, 2)
node _io_out_0_bits_T_3 = bits(chosen, 3, 3)
wire _io_out_0_bits_WIRE : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}
node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_7 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_8 = or(_io_out_0_bits_T_4, _io_out_0_bits_T_5)
node _io_out_0_bits_T_9 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_6)
node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_9, _io_out_0_bits_T_7)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_10
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[5]
node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_15 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12)
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_15, _io_out_0_bits_T_13)
node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_14)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_17
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_21 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19)
node _io_out_0_bits_T_23 = or(_io_out_0_bits_T_22, _io_out_0_bits_T_20)
node _io_out_0_bits_T_24 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_21)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_24
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_29 = or(_io_out_0_bits_T_25, _io_out_0_bits_T_26)
node _io_out_0_bits_T_30 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_27)
node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_30, _io_out_0_bits_T_28)
wire _io_out_0_bits_WIRE_6 : UInt<1>
connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_31
connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6
node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33)
node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_34)
node _io_out_0_bits_T_38 = or(_io_out_0_bits_T_37, _io_out_0_bits_T_35)
wire _io_out_0_bits_WIRE_7 : UInt<1>
connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_38
connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7
node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_43 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_40)
node _io_out_0_bits_T_44 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_41)
node _io_out_0_bits_T_45 = or(_io_out_0_bits_T_44, _io_out_0_bits_T_42)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_45
connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_9 : UInt<1>[1]
node _io_out_0_bits_T_46 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_47 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_50 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_47)
node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_48)
node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_49)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_52
connect _io_out_0_bits_WIRE_9[0], _io_out_0_bits_WIRE_10
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_9
wire _io_out_0_bits_WIRE_11 : UInt<1>[1]
node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54)
node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_57, _io_out_0_bits_T_55)
node _io_out_0_bits_T_59 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_56)
wire _io_out_0_bits_WIRE_12 : UInt<1>
connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_59
connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_10 = bits(chosen, 0, 0)
node _T_11 = and(_T_10, io.out[0].ready)
when _T_11 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_12 = bits(chosen, 1, 1)
node _T_13 = and(_T_12, io.out[0].ready)
when _T_13 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_14 = bits(chosen, 2, 2)
node _T_15 = and(_T_14, io.out[0].ready)
when _T_15 :
connect io.in[2].ready, UInt<1>(0h1)
node _T_16 = bits(chosen, 3, 3)
node _T_17 = and(_T_16, io.out[0].ready)
when _T_17 :
connect io.in[3].ready, UInt<1>(0h1)
node _T_18 = or(UInt<4>(0h0), chosen)
node _T_19 = and(io.out[0].ready, io.out[0].valid)
when _T_19 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_20 = and(io.out[0].ready, io.out[0].valid)
when _T_20 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = shr(io.chosen_oh[0], 2)
node _mask_T_3 = shr(io.chosen_oh[0], 3)
node _mask_T_4 = or(_mask_T, _mask_T_1)
node _mask_T_5 = or(_mask_T_4, _mask_T_2)
node _mask_T_6 = or(_mask_T_5, _mask_T_3)
connect mask, _mask_T_6
else :
node _mask_T_7 = not(mask)
node _mask_T_8 = eq(_mask_T_7, UInt<1>(0h0))
node _mask_T_9 = shl(mask, 1)
node _mask_T_10 = or(_mask_T_9, UInt<1>(0h1))
node _mask_T_11 = mux(_mask_T_8, UInt<1>(0h0), _mask_T_10)
connect mask, _mask_T_11 | module SwitchArbiter_178( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [3:0] unassigned = {2'h0, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [3:0] mask; // @[SwitchAllocator.scala:27:21]
wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71]
wire [1:0] _GEN = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [3:0] chosen = (|(_GEN & lock_0[1:0])) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70]
wire [1:0] _io_out_0_valid_T = _GEN & chosen[1:0]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [2:0] _GEN_0 = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_1 = _GEN_0[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38]
mask <= 4'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & {2'h3, ~io_in_1_bits_tail, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_io_out_0_valid_T) ? {chosen[3], _GEN_0[2], _GEN_1[1], _GEN_1[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_22 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_22
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_22
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h12))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_9 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_13 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_14 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_15 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_16 :
connect states[7].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_30 = and(io.router_req.ready, io.router_req.valid)
when _T_30 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_32 = or(_T_31, vcalloc_vals[2])
node _T_33 = or(_T_32, vcalloc_vals[3])
node _T_34 = or(_T_33, vcalloc_vals[4])
node _T_35 = or(_T_34, vcalloc_vals[5])
node _T_36 = or(_T_35, vcalloc_vals[6])
node _T_37 = or(_T_36, vcalloc_vals[7])
when _T_37 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_38 = bits(vcalloc_sel, 0, 0)
node _T_39 = and(vcalloc_vals[0], _T_38)
node _T_40 = and(_T_39, io.vcalloc_req.ready)
when _T_40 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_41 = bits(vcalloc_sel, 1, 1)
node _T_42 = and(vcalloc_vals[1], _T_41)
node _T_43 = and(_T_42, io.vcalloc_req.ready)
when _T_43 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_44 = bits(vcalloc_sel, 2, 2)
node _T_45 = and(vcalloc_vals[2], _T_44)
node _T_46 = and(_T_45, io.vcalloc_req.ready)
when _T_46 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_47 = bits(vcalloc_sel, 3, 3)
node _T_48 = and(vcalloc_vals[3], _T_47)
node _T_49 = and(_T_48, io.vcalloc_req.ready)
when _T_49 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_50 = bits(vcalloc_sel, 4, 4)
node _T_51 = and(vcalloc_vals[4], _T_50)
node _T_52 = and(_T_51, io.vcalloc_req.ready)
when _T_52 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_53 = bits(vcalloc_sel, 5, 5)
node _T_54 = and(vcalloc_vals[5], _T_53)
node _T_55 = and(_T_54, io.vcalloc_req.ready)
when _T_55 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_56 = bits(vcalloc_sel, 6, 6)
node _T_57 = and(vcalloc_vals[6], _T_56)
node _T_58 = and(_T_57, io.vcalloc_req.ready)
when _T_58 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_59 = bits(vcalloc_sel, 7, 7)
node _T_60 = and(vcalloc_vals[7], _T_59)
node _T_61 = and(_T_60, io.vcalloc_req.ready)
when _T_61 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_62 :
node _T_63 = bits(vcalloc_sel, 0, 0)
when _T_63 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_64 = eq(states[0].g, UInt<3>(0h2))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _T_68 = bits(vcalloc_sel, 1, 1)
when _T_68 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_69 = eq(states[1].g, UInt<3>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_69, UInt<1>(0h1), "") : assert_4
node _T_73 = bits(vcalloc_sel, 2, 2)
when _T_73 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_74 = eq(states[2].g, UInt<3>(0h2))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = bits(vcalloc_sel, 3, 3)
when _T_78 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_79 = eq(states[3].g, UInt<3>(0h2))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = bits(vcalloc_sel, 4, 4)
when _T_83 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_84 = eq(states[4].g, UInt<3>(0h2))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_84, UInt<1>(0h1), "") : assert_7
node _T_88 = bits(vcalloc_sel, 5, 5)
when _T_88 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_89 = eq(states[5].g, UInt<3>(0h2))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_89, UInt<1>(0h1), "") : assert_8
node _T_93 = bits(vcalloc_sel, 6, 6)
when _T_93 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_94 = eq(states[6].g, UInt<3>(0h2))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = bits(vcalloc_sel, 7, 7)
when _T_98 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_99 = eq(states[7].g, UInt<3>(0h2))
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_76
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail)
when _T_104 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail)
when _T_106 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail)
when _T_108 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail)
when _T_110 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail)
when _T_112 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail)
when _T_114 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail)
when _T_116 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56)
node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56)
node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70)
node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57)
node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57)
node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71)
node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58)
node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58)
node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72)
node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59)
node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59)
node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73)
node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77)
node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79)
node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74)
node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60)
node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60)
node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75)
node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61)
node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61)
node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76)
node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62)
node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62)
node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77)
node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63)
node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63)
node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78)
node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82)
node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84)
node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79)
node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86)
node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail)
when _T_118 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_119 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[0].vc_sel.`0`[4], UInt<1>(0h0)
connect states[0].vc_sel.`0`[5], UInt<1>(0h0)
connect states[0].vc_sel.`0`[6], UInt<1>(0h0)
connect states[0].vc_sel.`0`[7], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[3], UInt<1>(0h0)
connect states[0].vc_sel.`1`[4], UInt<1>(0h0)
connect states[0].vc_sel.`1`[5], UInt<1>(0h0)
connect states[0].vc_sel.`1`[6], UInt<1>(0h0)
connect states[0].vc_sel.`1`[7], UInt<1>(0h0)
connect states[0].vc_sel.`2`[0], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[2], UInt<1>(0h0)
connect states[0].vc_sel.`2`[3], UInt<1>(0h0)
connect states[0].vc_sel.`2`[4], UInt<1>(0h0)
connect states[0].vc_sel.`2`[5], UInt<1>(0h0)
connect states[0].vc_sel.`2`[6], UInt<1>(0h0)
connect states[0].vc_sel.`2`[7], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[2], UInt<1>(0h0)
connect states[0].vc_sel.`3`[3], UInt<1>(0h0)
connect states[0].vc_sel.`3`[4], UInt<1>(0h0)
connect states[0].vc_sel.`3`[5], UInt<1>(0h0)
connect states[0].vc_sel.`3`[6], UInt<1>(0h0)
connect states[0].vc_sel.`3`[7], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[1], UInt<1>(0h0)
connect states[1].vc_sel.`2`[2], UInt<1>(0h0)
connect states[1].vc_sel.`2`[3], UInt<1>(0h0)
connect states[1].vc_sel.`2`[4], UInt<1>(0h0)
connect states[1].vc_sel.`2`[5], UInt<1>(0h0)
connect states[1].vc_sel.`2`[6], UInt<1>(0h0)
connect states[1].vc_sel.`2`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
connect states[2].vc_sel.`2`[2], UInt<1>(0h0)
connect states[2].vc_sel.`2`[3], UInt<1>(0h0)
connect states[2].vc_sel.`2`[4], UInt<1>(0h0)
connect states[2].vc_sel.`2`[5], UInt<1>(0h0)
connect states[2].vc_sel.`2`[6], UInt<1>(0h0)
connect states[2].vc_sel.`2`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`2`[0], UInt<1>(0h0)
connect states[3].vc_sel.`2`[1], UInt<1>(0h0)
connect states[3].vc_sel.`2`[2], UInt<1>(0h0)
connect states[3].vc_sel.`2`[3], UInt<1>(0h0)
connect states[3].vc_sel.`2`[4], UInt<1>(0h0)
connect states[3].vc_sel.`2`[5], UInt<1>(0h0)
connect states[3].vc_sel.`2`[6], UInt<1>(0h0)
connect states[3].vc_sel.`2`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`1`[5], UInt<1>(0h0)
connect states[4].vc_sel.`1`[6], UInt<1>(0h0)
connect states[4].vc_sel.`1`[7], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[1], UInt<1>(0h0)
connect states[4].vc_sel.`2`[2], UInt<1>(0h0)
connect states[4].vc_sel.`2`[3], UInt<1>(0h0)
connect states[4].vc_sel.`2`[5], UInt<1>(0h0)
connect states[4].vc_sel.`2`[6], UInt<1>(0h0)
connect states[4].vc_sel.`2`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`1`[5], UInt<1>(0h0)
connect states[5].vc_sel.`1`[6], UInt<1>(0h0)
connect states[5].vc_sel.`1`[7], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`2`[1], UInt<1>(0h0)
connect states[5].vc_sel.`2`[2], UInt<1>(0h0)
connect states[5].vc_sel.`2`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`1`[5], UInt<1>(0h0)
connect states[6].vc_sel.`1`[6], UInt<1>(0h0)
connect states[6].vc_sel.`1`[7], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`2`[1], UInt<1>(0h0)
connect states[6].vc_sel.`2`[2], UInt<1>(0h0)
connect states[6].vc_sel.`2`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`1`[5], UInt<1>(0h0)
connect states[7].vc_sel.`1`[6], UInt<1>(0h0)
connect states[7].vc_sel.`1`[7], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`2`[1], UInt<1>(0h0)
connect states[7].vc_sel.`2`[2], UInt<1>(0h0)
connect states[7].vc_sel.`2`[3], UInt<1>(0h0)
node _T_120 = asUInt(reset)
when _T_120 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_22( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_34 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_34( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_99 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_112
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_99( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_112 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s2_6 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_T_2 = not(_res_hit_T_1)
node _res_hit_T_3 = or(_res_hit_T_2, UInt<2>(0h3))
node _res_hit_T_4 = not(_res_hit_T_3)
node _res_hit_T_5 = xor(io.addr, _res_hit_T_4)
node _res_hit_T_6 = not(io.pmp[7].mask)
node _res_hit_T_7 = and(_res_hit_T_5, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_T_9 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_10 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_11 = bits(_res_hit_T_10, 1, 0)
node _res_hit_T_12 = not(_res_hit_T_11)
node _res_hit_T_13 = shl(io.pmp[6].addr, 2)
node _res_hit_T_14 = not(_res_hit_T_13)
node _res_hit_T_15 = or(_res_hit_T_14, UInt<2>(0h3))
node _res_hit_T_16 = not(_res_hit_T_15)
node _res_hit_T_17 = lt(io.addr, _res_hit_T_16)
node _res_hit_T_18 = eq(_res_hit_T_17, UInt<1>(0h0))
node _res_hit_T_19 = shl(io.pmp[7].addr, 2)
node _res_hit_T_20 = not(_res_hit_T_19)
node _res_hit_T_21 = or(_res_hit_T_20, UInt<2>(0h3))
node _res_hit_T_22 = not(_res_hit_T_21)
node _res_hit_T_23 = lt(io.addr, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_18, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_9, _res_hit_T_24)
node res_hit = mux(_res_hit_T, _res_hit_T_8, _res_hit_T_25)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, UInt<1>(0h1))
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, UInt<1>(0h1))
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, UInt<1>(0h1))
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, UInt<1>(0h1))
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, UInt<1>(0h1))
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, UInt<1>(0h1))
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(UInt<1>(0h1), _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(UInt<1>(0h1), _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(UInt<1>(0h1), _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_26 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_T_27 = shl(io.pmp[6].addr, 2)
node _res_hit_T_28 = not(_res_hit_T_27)
node _res_hit_T_29 = or(_res_hit_T_28, UInt<2>(0h3))
node _res_hit_T_30 = not(_res_hit_T_29)
node _res_hit_T_31 = xor(io.addr, _res_hit_T_30)
node _res_hit_T_32 = not(io.pmp[6].mask)
node _res_hit_T_33 = and(_res_hit_T_31, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_T_35 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_36 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_37 = bits(_res_hit_T_36, 1, 0)
node _res_hit_T_38 = not(_res_hit_T_37)
node _res_hit_T_39 = shl(io.pmp[5].addr, 2)
node _res_hit_T_40 = not(_res_hit_T_39)
node _res_hit_T_41 = or(_res_hit_T_40, UInt<2>(0h3))
node _res_hit_T_42 = not(_res_hit_T_41)
node _res_hit_T_43 = lt(io.addr, _res_hit_T_42)
node _res_hit_T_44 = eq(_res_hit_T_43, UInt<1>(0h0))
node _res_hit_T_45 = shl(io.pmp[6].addr, 2)
node _res_hit_T_46 = not(_res_hit_T_45)
node _res_hit_T_47 = or(_res_hit_T_46, UInt<2>(0h3))
node _res_hit_T_48 = not(_res_hit_T_47)
node _res_hit_T_49 = lt(io.addr, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_44, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_35, _res_hit_T_50)
node res_hit_1 = mux(_res_hit_T_26, _res_hit_T_34, _res_hit_T_51)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, UInt<1>(0h1))
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, UInt<1>(0h1))
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, UInt<1>(0h1))
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, UInt<1>(0h1))
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, UInt<1>(0h1))
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, UInt<1>(0h1))
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(UInt<1>(0h1), _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(UInt<1>(0h1), _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(UInt<1>(0h1), _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_52 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_T_53 = shl(io.pmp[5].addr, 2)
node _res_hit_T_54 = not(_res_hit_T_53)
node _res_hit_T_55 = or(_res_hit_T_54, UInt<2>(0h3))
node _res_hit_T_56 = not(_res_hit_T_55)
node _res_hit_T_57 = xor(io.addr, _res_hit_T_56)
node _res_hit_T_58 = not(io.pmp[5].mask)
node _res_hit_T_59 = and(_res_hit_T_57, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_T_61 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_62 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_63 = bits(_res_hit_T_62, 1, 0)
node _res_hit_T_64 = not(_res_hit_T_63)
node _res_hit_T_65 = shl(io.pmp[4].addr, 2)
node _res_hit_T_66 = not(_res_hit_T_65)
node _res_hit_T_67 = or(_res_hit_T_66, UInt<2>(0h3))
node _res_hit_T_68 = not(_res_hit_T_67)
node _res_hit_T_69 = lt(io.addr, _res_hit_T_68)
node _res_hit_T_70 = eq(_res_hit_T_69, UInt<1>(0h0))
node _res_hit_T_71 = shl(io.pmp[5].addr, 2)
node _res_hit_T_72 = not(_res_hit_T_71)
node _res_hit_T_73 = or(_res_hit_T_72, UInt<2>(0h3))
node _res_hit_T_74 = not(_res_hit_T_73)
node _res_hit_T_75 = lt(io.addr, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_70, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_61, _res_hit_T_76)
node res_hit_2 = mux(_res_hit_T_52, _res_hit_T_60, _res_hit_T_77)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, UInt<1>(0h1))
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, UInt<1>(0h1))
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, UInt<1>(0h1))
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, UInt<1>(0h1))
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, UInt<1>(0h1))
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, UInt<1>(0h1))
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(UInt<1>(0h1), _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(UInt<1>(0h1), _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(UInt<1>(0h1), _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_78 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_T_79 = shl(io.pmp[4].addr, 2)
node _res_hit_T_80 = not(_res_hit_T_79)
node _res_hit_T_81 = or(_res_hit_T_80, UInt<2>(0h3))
node _res_hit_T_82 = not(_res_hit_T_81)
node _res_hit_T_83 = xor(io.addr, _res_hit_T_82)
node _res_hit_T_84 = not(io.pmp[4].mask)
node _res_hit_T_85 = and(_res_hit_T_83, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_T_87 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_88 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_89 = bits(_res_hit_T_88, 1, 0)
node _res_hit_T_90 = not(_res_hit_T_89)
node _res_hit_T_91 = shl(io.pmp[3].addr, 2)
node _res_hit_T_92 = not(_res_hit_T_91)
node _res_hit_T_93 = or(_res_hit_T_92, UInt<2>(0h3))
node _res_hit_T_94 = not(_res_hit_T_93)
node _res_hit_T_95 = lt(io.addr, _res_hit_T_94)
node _res_hit_T_96 = eq(_res_hit_T_95, UInt<1>(0h0))
node _res_hit_T_97 = shl(io.pmp[4].addr, 2)
node _res_hit_T_98 = not(_res_hit_T_97)
node _res_hit_T_99 = or(_res_hit_T_98, UInt<2>(0h3))
node _res_hit_T_100 = not(_res_hit_T_99)
node _res_hit_T_101 = lt(io.addr, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_96, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_87, _res_hit_T_102)
node res_hit_3 = mux(_res_hit_T_78, _res_hit_T_86, _res_hit_T_103)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, UInt<1>(0h1))
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, UInt<1>(0h1))
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, UInt<1>(0h1))
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, UInt<1>(0h1))
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, UInt<1>(0h1))
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, UInt<1>(0h1))
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(UInt<1>(0h1), _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(UInt<1>(0h1), _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(UInt<1>(0h1), _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_104 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_T_105 = shl(io.pmp[3].addr, 2)
node _res_hit_T_106 = not(_res_hit_T_105)
node _res_hit_T_107 = or(_res_hit_T_106, UInt<2>(0h3))
node _res_hit_T_108 = not(_res_hit_T_107)
node _res_hit_T_109 = xor(io.addr, _res_hit_T_108)
node _res_hit_T_110 = not(io.pmp[3].mask)
node _res_hit_T_111 = and(_res_hit_T_109, _res_hit_T_110)
node _res_hit_T_112 = eq(_res_hit_T_111, UInt<1>(0h0))
node _res_hit_T_113 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_114 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_115 = bits(_res_hit_T_114, 1, 0)
node _res_hit_T_116 = not(_res_hit_T_115)
node _res_hit_T_117 = shl(io.pmp[2].addr, 2)
node _res_hit_T_118 = not(_res_hit_T_117)
node _res_hit_T_119 = or(_res_hit_T_118, UInt<2>(0h3))
node _res_hit_T_120 = not(_res_hit_T_119)
node _res_hit_T_121 = lt(io.addr, _res_hit_T_120)
node _res_hit_T_122 = eq(_res_hit_T_121, UInt<1>(0h0))
node _res_hit_T_123 = shl(io.pmp[3].addr, 2)
node _res_hit_T_124 = not(_res_hit_T_123)
node _res_hit_T_125 = or(_res_hit_T_124, UInt<2>(0h3))
node _res_hit_T_126 = not(_res_hit_T_125)
node _res_hit_T_127 = lt(io.addr, _res_hit_T_126)
node _res_hit_T_128 = and(_res_hit_T_122, _res_hit_T_127)
node _res_hit_T_129 = and(_res_hit_T_113, _res_hit_T_128)
node res_hit_4 = mux(_res_hit_T_104, _res_hit_T_112, _res_hit_T_129)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, UInt<1>(0h1))
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, UInt<1>(0h1))
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, UInt<1>(0h1))
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, UInt<1>(0h1))
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, UInt<1>(0h1))
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, UInt<1>(0h1))
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(UInt<1>(0h1), _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(UInt<1>(0h1), _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(UInt<1>(0h1), _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_130 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_T_131 = shl(io.pmp[2].addr, 2)
node _res_hit_T_132 = not(_res_hit_T_131)
node _res_hit_T_133 = or(_res_hit_T_132, UInt<2>(0h3))
node _res_hit_T_134 = not(_res_hit_T_133)
node _res_hit_T_135 = xor(io.addr, _res_hit_T_134)
node _res_hit_T_136 = not(io.pmp[2].mask)
node _res_hit_T_137 = and(_res_hit_T_135, _res_hit_T_136)
node _res_hit_T_138 = eq(_res_hit_T_137, UInt<1>(0h0))
node _res_hit_T_139 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_140 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_141 = bits(_res_hit_T_140, 1, 0)
node _res_hit_T_142 = not(_res_hit_T_141)
node _res_hit_T_143 = shl(io.pmp[1].addr, 2)
node _res_hit_T_144 = not(_res_hit_T_143)
node _res_hit_T_145 = or(_res_hit_T_144, UInt<2>(0h3))
node _res_hit_T_146 = not(_res_hit_T_145)
node _res_hit_T_147 = lt(io.addr, _res_hit_T_146)
node _res_hit_T_148 = eq(_res_hit_T_147, UInt<1>(0h0))
node _res_hit_T_149 = shl(io.pmp[2].addr, 2)
node _res_hit_T_150 = not(_res_hit_T_149)
node _res_hit_T_151 = or(_res_hit_T_150, UInt<2>(0h3))
node _res_hit_T_152 = not(_res_hit_T_151)
node _res_hit_T_153 = lt(io.addr, _res_hit_T_152)
node _res_hit_T_154 = and(_res_hit_T_148, _res_hit_T_153)
node _res_hit_T_155 = and(_res_hit_T_139, _res_hit_T_154)
node res_hit_5 = mux(_res_hit_T_130, _res_hit_T_138, _res_hit_T_155)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, UInt<1>(0h1))
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, UInt<1>(0h1))
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, UInt<1>(0h1))
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, UInt<1>(0h1))
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, UInt<1>(0h1))
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, UInt<1>(0h1))
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(UInt<1>(0h1), _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(UInt<1>(0h1), _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(UInt<1>(0h1), _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_156 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_T_157 = shl(io.pmp[1].addr, 2)
node _res_hit_T_158 = not(_res_hit_T_157)
node _res_hit_T_159 = or(_res_hit_T_158, UInt<2>(0h3))
node _res_hit_T_160 = not(_res_hit_T_159)
node _res_hit_T_161 = xor(io.addr, _res_hit_T_160)
node _res_hit_T_162 = not(io.pmp[1].mask)
node _res_hit_T_163 = and(_res_hit_T_161, _res_hit_T_162)
node _res_hit_T_164 = eq(_res_hit_T_163, UInt<1>(0h0))
node _res_hit_T_165 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_166 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_167 = bits(_res_hit_T_166, 1, 0)
node _res_hit_T_168 = not(_res_hit_T_167)
node _res_hit_T_169 = shl(io.pmp[0].addr, 2)
node _res_hit_T_170 = not(_res_hit_T_169)
node _res_hit_T_171 = or(_res_hit_T_170, UInt<2>(0h3))
node _res_hit_T_172 = not(_res_hit_T_171)
node _res_hit_T_173 = lt(io.addr, _res_hit_T_172)
node _res_hit_T_174 = eq(_res_hit_T_173, UInt<1>(0h0))
node _res_hit_T_175 = shl(io.pmp[1].addr, 2)
node _res_hit_T_176 = not(_res_hit_T_175)
node _res_hit_T_177 = or(_res_hit_T_176, UInt<2>(0h3))
node _res_hit_T_178 = not(_res_hit_T_177)
node _res_hit_T_179 = lt(io.addr, _res_hit_T_178)
node _res_hit_T_180 = and(_res_hit_T_174, _res_hit_T_179)
node _res_hit_T_181 = and(_res_hit_T_165, _res_hit_T_180)
node res_hit_6 = mux(_res_hit_T_156, _res_hit_T_164, _res_hit_T_181)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, UInt<1>(0h1))
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, UInt<1>(0h1))
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, UInt<1>(0h1))
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, UInt<1>(0h1))
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, UInt<1>(0h1))
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, UInt<1>(0h1))
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(UInt<1>(0h1), _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(UInt<1>(0h1), _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(UInt<1>(0h1), _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_182 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_T_183 = shl(io.pmp[0].addr, 2)
node _res_hit_T_184 = not(_res_hit_T_183)
node _res_hit_T_185 = or(_res_hit_T_184, UInt<2>(0h3))
node _res_hit_T_186 = not(_res_hit_T_185)
node _res_hit_T_187 = xor(io.addr, _res_hit_T_186)
node _res_hit_T_188 = not(io.pmp[0].mask)
node _res_hit_T_189 = and(_res_hit_T_187, _res_hit_T_188)
node _res_hit_T_190 = eq(_res_hit_T_189, UInt<1>(0h0))
node _res_hit_T_191 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_192 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_193 = bits(_res_hit_T_192, 1, 0)
node _res_hit_T_194 = not(_res_hit_T_193)
node _res_hit_T_195 = shl(pmp0.addr, 2)
node _res_hit_T_196 = not(_res_hit_T_195)
node _res_hit_T_197 = or(_res_hit_T_196, UInt<2>(0h3))
node _res_hit_T_198 = not(_res_hit_T_197)
node _res_hit_T_199 = lt(io.addr, _res_hit_T_198)
node _res_hit_T_200 = eq(_res_hit_T_199, UInt<1>(0h0))
node _res_hit_T_201 = shl(io.pmp[0].addr, 2)
node _res_hit_T_202 = not(_res_hit_T_201)
node _res_hit_T_203 = or(_res_hit_T_202, UInt<2>(0h3))
node _res_hit_T_204 = not(_res_hit_T_203)
node _res_hit_T_205 = lt(io.addr, _res_hit_T_204)
node _res_hit_T_206 = and(_res_hit_T_200, _res_hit_T_205)
node _res_hit_T_207 = and(_res_hit_T_191, _res_hit_T_206)
node res_hit_7 = mux(_res_hit_T_182, _res_hit_T_190, _res_hit_T_207)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, UInt<1>(0h1))
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, UInt<1>(0h1))
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, UInt<1>(0h1))
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, UInt<1>(0h1))
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, UInt<1>(0h1))
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, UInt<1>(0h1))
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(UInt<1>(0h1), _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(UInt<1>(0h1), _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(UInt<1>(0h1), _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s2_6( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire [4:0] _res_hit_T_10 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_36 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_62 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_88 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_114 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_140 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_166 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_192 = 5'hC; // @[package.scala:243:71]
wire [1:0] _res_hit_T_12 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_38 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_64 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_90 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_116 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_142 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_168 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_194 = 2'h3; // @[package.scala:243:46]
wire [31:0] _res_hit_T_196 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_197 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_T_195 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_198 = 32'h0; // @[PMP.scala:60:27]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire _res_hit_T_199 = 1'h0; // @[PMP.scala:77:9]
wire _res_hit_T_200 = 1'h1; // @[PMP.scala:88:5]
wire [1:0] io_size = 2'h2; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] _res_hit_T_11 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_37 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_63 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_89 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_115 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_141 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_167 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_193 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_1; // @[PMP.scala:60:36]
assign _res_hit_T_1 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_19; // @[PMP.scala:60:36]
assign _res_hit_T_19 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_3 = {_res_hit_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_5 = io_addr_0 ^ _res_hit_T_4; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_9 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_13; // @[PMP.scala:60:36]
assign _res_hit_T_13 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_27; // @[PMP.scala:60:36]
assign _res_hit_T_27 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_45; // @[PMP.scala:60:36]
assign _res_hit_T_45 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_14 = ~_res_hit_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_15 = {_res_hit_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_16 = ~_res_hit_T_15; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_17 = io_addr_0 < _res_hit_T_16; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_18 = ~_res_hit_T_17; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_20 = ~_res_hit_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_21 = {_res_hit_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_22 = ~_res_hit_T_21; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_23 = io_addr_0 < _res_hit_T_22; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_24 = _res_hit_T_18 & _res_hit_T_23; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_9 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_8 : _res_hit_T_25; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18; // @[PMP.scala:177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22; // @[PMP.scala:178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27; // @[PMP.scala:177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31; // @[PMP.scala:178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36; // @[PMP.scala:177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40; // @[PMP.scala:178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = _res_cur_cfg_r_T; // @[PMP.scala:182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = _res_cur_cfg_w_T; // @[PMP.scala:183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = _res_cur_cfg_x_T; // @[PMP.scala:184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_28 = ~_res_hit_T_27; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_29 = {_res_hit_T_28[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_30 = ~_res_hit_T_29; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_31 = io_addr_0 ^ _res_hit_T_30; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_32 = ~io_pmp_6_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_33 = _res_hit_T_31 & _res_hit_T_32; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_34 = _res_hit_T_33 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_35 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_39; // @[PMP.scala:60:36]
assign _res_hit_T_39 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_53; // @[PMP.scala:60:36]
assign _res_hit_T_53 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_71; // @[PMP.scala:60:36]
assign _res_hit_T_71 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_40 = ~_res_hit_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_41 = {_res_hit_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_43 = io_addr_0 < _res_hit_T_42; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_47 = {_res_hit_T_46[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_48 = ~_res_hit_T_47; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_49 = io_addr_0 < _res_hit_T_48; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_50 = _res_hit_T_44 & _res_hit_T_49; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_35 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_26 ? _res_hit_T_34 : _res_hit_T_51; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63; // @[PMP.scala:177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67; // @[PMP.scala:178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72; // @[PMP.scala:177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76; // @[PMP.scala:178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81; // @[PMP.scala:177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85; // @[PMP.scala:178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = _res_cur_cfg_r_T_2; // @[PMP.scala:182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = _res_cur_cfg_w_T_2; // @[PMP.scala:183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = _res_cur_cfg_x_T_2; // @[PMP.scala:184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_54 = ~_res_hit_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_55 = {_res_hit_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_56 = ~_res_hit_T_55; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_57 = io_addr_0 ^ _res_hit_T_56; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_58 = ~io_pmp_5_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_59 = _res_hit_T_57 & _res_hit_T_58; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_60 = _res_hit_T_59 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_61 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_65; // @[PMP.scala:60:36]
assign _res_hit_T_65 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_79; // @[PMP.scala:60:36]
assign _res_hit_T_79 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_97; // @[PMP.scala:60:36]
assign _res_hit_T_97 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_66 = ~_res_hit_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_67 = {_res_hit_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_68 = ~_res_hit_T_67; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_69 = io_addr_0 < _res_hit_T_68; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_70 = ~_res_hit_T_69; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_72 = ~_res_hit_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_73 = {_res_hit_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_74 = ~_res_hit_T_73; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_75 = io_addr_0 < _res_hit_T_74; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_76 = _res_hit_T_70 & _res_hit_T_75; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_61 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_52 ? _res_hit_T_60 : _res_hit_T_77; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108; // @[PMP.scala:177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112; // @[PMP.scala:178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117; // @[PMP.scala:177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121; // @[PMP.scala:178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126; // @[PMP.scala:177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130; // @[PMP.scala:178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = _res_cur_cfg_r_T_4; // @[PMP.scala:182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = _res_cur_cfg_w_T_4; // @[PMP.scala:183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = _res_cur_cfg_x_T_4; // @[PMP.scala:184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_80 = ~_res_hit_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_81 = {_res_hit_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_82 = ~_res_hit_T_81; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_83 = io_addr_0 ^ _res_hit_T_82; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_84 = ~io_pmp_4_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_85 = _res_hit_T_83 & _res_hit_T_84; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_86 = _res_hit_T_85 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_87 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_91; // @[PMP.scala:60:36]
assign _res_hit_T_91 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_105; // @[PMP.scala:60:36]
assign _res_hit_T_105 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_123; // @[PMP.scala:60:36]
assign _res_hit_T_123 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_92 = ~_res_hit_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_93 = {_res_hit_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_94 = ~_res_hit_T_93; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_95 = io_addr_0 < _res_hit_T_94; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_99 = {_res_hit_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_101 = io_addr_0 < _res_hit_T_100; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_102 = _res_hit_T_96 & _res_hit_T_101; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_103 = _res_hit_T_87 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_78 ? _res_hit_T_86 : _res_hit_T_103; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153; // @[PMP.scala:177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157; // @[PMP.scala:178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162; // @[PMP.scala:177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166; // @[PMP.scala:178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171; // @[PMP.scala:177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175; // @[PMP.scala:178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = _res_cur_cfg_r_T_6; // @[PMP.scala:182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = _res_cur_cfg_w_T_6; // @[PMP.scala:183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = _res_cur_cfg_x_T_6; // @[PMP.scala:184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_104 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_106 = ~_res_hit_T_105; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_107 = {_res_hit_T_106[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_108 = ~_res_hit_T_107; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_109 = io_addr_0 ^ _res_hit_T_108; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_110 = ~io_pmp_3_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_111 = _res_hit_T_109 & _res_hit_T_110; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_112 = _res_hit_T_111 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_113 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_117; // @[PMP.scala:60:36]
assign _res_hit_T_117 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_131; // @[PMP.scala:60:36]
assign _res_hit_T_131 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_149; // @[PMP.scala:60:36]
assign _res_hit_T_149 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_118 = ~_res_hit_T_117; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_119 = {_res_hit_T_118[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_120 = ~_res_hit_T_119; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_121 = io_addr_0 < _res_hit_T_120; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_122 = ~_res_hit_T_121; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_124 = ~_res_hit_T_123; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_125 = {_res_hit_T_124[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_126 = ~_res_hit_T_125; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_127 = io_addr_0 < _res_hit_T_126; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_128 = _res_hit_T_122 & _res_hit_T_127; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_129 = _res_hit_T_113 & _res_hit_T_128; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_104 ? _res_hit_T_112 : _res_hit_T_129; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198; // @[PMP.scala:177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202; // @[PMP.scala:178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207; // @[PMP.scala:177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211; // @[PMP.scala:178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216; // @[PMP.scala:177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220; // @[PMP.scala:178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = _res_cur_cfg_r_T_8; // @[PMP.scala:182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = _res_cur_cfg_w_T_8; // @[PMP.scala:183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = _res_cur_cfg_x_T_8; // @[PMP.scala:184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_130 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_132 = ~_res_hit_T_131; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_133 = {_res_hit_T_132[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_134 = ~_res_hit_T_133; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_135 = io_addr_0 ^ _res_hit_T_134; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_136 = ~io_pmp_2_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_137 = _res_hit_T_135 & _res_hit_T_136; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_138 = _res_hit_T_137 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_139 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_143; // @[PMP.scala:60:36]
assign _res_hit_T_143 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_157; // @[PMP.scala:60:36]
assign _res_hit_T_157 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_175; // @[PMP.scala:60:36]
assign _res_hit_T_175 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_144 = ~_res_hit_T_143; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_145 = {_res_hit_T_144[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_146 = ~_res_hit_T_145; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_147 = io_addr_0 < _res_hit_T_146; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_148 = ~_res_hit_T_147; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_151 = {_res_hit_T_150[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_153 = io_addr_0 < _res_hit_T_152; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_154 = _res_hit_T_148 & _res_hit_T_153; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_155 = _res_hit_T_139 & _res_hit_T_154; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_130 ? _res_hit_T_138 : _res_hit_T_155; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243; // @[PMP.scala:177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247; // @[PMP.scala:178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252; // @[PMP.scala:177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256; // @[PMP.scala:178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261; // @[PMP.scala:177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265; // @[PMP.scala:178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = _res_cur_cfg_r_T_10; // @[PMP.scala:182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = _res_cur_cfg_w_T_10; // @[PMP.scala:183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = _res_cur_cfg_x_T_10; // @[PMP.scala:184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_156 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_158 = ~_res_hit_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_159 = {_res_hit_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_160 = ~_res_hit_T_159; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_161 = io_addr_0 ^ _res_hit_T_160; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_162 = ~io_pmp_1_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_163 = _res_hit_T_161 & _res_hit_T_162; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_164 = _res_hit_T_163 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_165 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_169; // @[PMP.scala:60:36]
assign _res_hit_T_169 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_183; // @[PMP.scala:60:36]
assign _res_hit_T_183 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_201; // @[PMP.scala:60:36]
assign _res_hit_T_201 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_170 = ~_res_hit_T_169; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_171 = {_res_hit_T_170[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_172 = ~_res_hit_T_171; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_173 = io_addr_0 < _res_hit_T_172; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_174 = ~_res_hit_T_173; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_176 = ~_res_hit_T_175; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_177 = {_res_hit_T_176[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_178 = ~_res_hit_T_177; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_179 = io_addr_0 < _res_hit_T_178; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_180 = _res_hit_T_174 & _res_hit_T_179; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_181 = _res_hit_T_165 & _res_hit_T_180; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_156 ? _res_hit_T_164 : _res_hit_T_181; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288; // @[PMP.scala:177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292; // @[PMP.scala:178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297; // @[PMP.scala:177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301; // @[PMP.scala:178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306; // @[PMP.scala:177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310; // @[PMP.scala:178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = _res_cur_cfg_r_T_12; // @[PMP.scala:182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = _res_cur_cfg_w_T_12; // @[PMP.scala:183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = _res_cur_cfg_x_T_12; // @[PMP.scala:184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_182 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_184 = ~_res_hit_T_183; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_185 = {_res_hit_T_184[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_186 = ~_res_hit_T_185; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_187 = io_addr_0 ^ _res_hit_T_186; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_188 = ~io_pmp_0_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_189 = _res_hit_T_187 & _res_hit_T_188; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_190 = _res_hit_T_189 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_191 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _res_hit_T_202 = ~_res_hit_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_203 = {_res_hit_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_204 = ~_res_hit_T_203; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_205 = io_addr_0 < _res_hit_T_204; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_206 = _res_hit_T_205; // @[PMP.scala:77:9, :94:48]
wire _res_hit_T_207 = _res_hit_T_191 & _res_hit_T_206; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_182 ? _res_hit_T_190 : _res_hit_T_207; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333; // @[PMP.scala:177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337; // @[PMP.scala:178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342; // @[PMP.scala:177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346; // @[PMP.scala:178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351; // @[PMP.scala:177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355; // @[PMP.scala:178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = _res_cur_cfg_r_T_14; // @[PMP.scala:182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = _res_cur_cfg_w_T_14; // @[PMP.scala:183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = _res_cur_cfg_x_T_14; // @[PMP.scala:184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_3 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_3
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_3
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _T_12 = and(io.router_req.ready, io.router_req.valid)
when _T_12 :
node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_13, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_19 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_20 = and(io.router_req.ready, io.router_req.valid)
when _T_20 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_22 = or(_T_21, vcalloc_vals[2])
when _T_22 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_23 = bits(vcalloc_sel, 1, 1)
node _T_24 = and(vcalloc_vals[1], _T_23)
node _T_25 = and(_T_24, io.vcalloc_req.ready)
when _T_25 :
connect states[1].g, UInt<3>(0h3)
node _T_26 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_26 :
connect vcalloc_vals[1], UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_27 = bits(vcalloc_sel, 2, 2)
node _T_28 = and(vcalloc_vals[2], _T_27)
node _T_29 = and(_T_28, io.vcalloc_req.ready)
when _T_29 :
connect states[2].g, UInt<3>(0h3)
node _T_30 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_30 :
connect vcalloc_vals[2], UInt<1>(0h1)
connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_31 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_31 :
node _T_32 = bits(vcalloc_sel, 0, 0)
when _T_32 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_33 = bits(vcalloc_sel, 1, 1)
when _T_33 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_34 = bits(vcalloc_sel, 2, 2)
when _T_34 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_9
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[1].vc_sel.`2`[2], states[1].vc_sel.`2`[1])
node _credit_available_T_2 = cat(credit_available_hi_2, states[1].vc_sel.`2`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_3 = cat(states[1].vc_sel.`3`[0], _credit_available_T_2)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo)
node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0])
node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0])
node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4)
node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_35 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_36 = and(_T_35, input_buffer.io.deq[1].bits.tail)
when _T_36 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_hi_8 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1])
node _credit_available_T_9 = cat(credit_available_hi_8, states[2].vc_sel.`0`[0])
node credit_available_hi_9 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1])
node _credit_available_T_10 = cat(credit_available_hi_9, states[2].vc_sel.`1`[0])
node credit_available_hi_10 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1])
node _credit_available_T_11 = cat(credit_available_hi_10, states[2].vc_sel.`2`[0])
node credit_available_lo_2 = cat(_credit_available_T_10, _credit_available_T_9)
node credit_available_hi_11 = cat(states[2].vc_sel.`3`[0], _credit_available_T_11)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_2)
node credit_available_hi_12 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_13 = cat(credit_available_hi_12, io.out_credit_available.`0`[0])
node credit_available_hi_13 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_14 = cat(credit_available_hi_13, io.out_credit_available.`1`[0])
node credit_available_hi_14 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_15 = cat(credit_available_hi_14, io.out_credit_available.`2`[0])
node credit_available_lo_3 = cat(_credit_available_T_14, _credit_available_T_13)
node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], _credit_available_T_15)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_3)
node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16)
node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_37 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_38 = and(_T_37, input_buffer.io.deq[2].bits.tail)
when _T_38 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[3]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_42
connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10
node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_47
connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11
connect vc_sel.`2`, _vc_sel_WIRE_8
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_52
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`3`, _vc_sel_WIRE_12
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1])
node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0])
node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0))
node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16)
node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17)
node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_21
node _T_39 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_39 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
node _T_40 = asUInt(reset)
when _T_40 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_3( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_2_2; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9]
wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _GEN_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_2_1; // @[MixedVec.scala:116:9]
wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_3 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_27 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_27( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node sAdjustedExp = add(io.in.sExp, asSInt(UInt<12>(0h820)))
node _adjustedSig_T = bits(io.in.sig, 53, 41)
node _adjustedSig_T_1 = bits(io.in.sig, 40, 0)
node _adjustedSig_T_2 = orr(_adjustedSig_T_1)
node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2)
wire common_expOut : UInt<6>
wire common_fractOut : UInt<10>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(sAdjustedExp, 5, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _roundMask_T_1)
node _roundMask_T_2 = bits(roundMask_shift, 18, 7)
node _roundMask_T_3 = bits(_roundMask_T_2, 7, 0)
node _roundMask_T_4 = shl(UInt<4>(0hf), 4)
node _roundMask_T_5 = xor(UInt<8>(0hff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 4)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 3, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 4)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 5, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 2)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 2)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 5, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 2)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 6, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 1)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 1)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 6, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 1)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_2, 11, 8)
node _roundMask_T_34 = bits(_roundMask_T_33, 1, 0)
node _roundMask_T_35 = bits(_roundMask_T_34, 0, 0)
node _roundMask_T_36 = bits(_roundMask_T_34, 1, 1)
node _roundMask_T_37 = cat(_roundMask_T_35, _roundMask_T_36)
node _roundMask_T_38 = bits(_roundMask_T_33, 3, 2)
node _roundMask_T_39 = bits(_roundMask_T_38, 0, 0)
node _roundMask_T_40 = bits(_roundMask_T_38, 1, 1)
node _roundMask_T_41 = cat(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = cat(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = cat(_roundMask_T_32, _roundMask_T_42)
node _roundMask_T_44 = or(_roundMask_T_43, UInt<1>(0h0))
node roundMask = cat(_roundMask_T_44, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 11)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 5, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 10, 1)
node _common_fractOut_T_1 = bits(roundedSig, 9, 0)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 4)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<5>(0h8)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 12, 12)
node _roundCarry_T_1 = bits(roundedSig, 11, 11)
node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(sAdjustedExp, 5)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<6>(0h8))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11_1( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [53:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [53:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20]
wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire [13:0] sAdjustedExp = {io_in_sExp_0[12], io_in_sExp_0} - 14'h7E0; // @[RoundAnyRawFNToRecFN.scala:48:5, :110:24]
wire [12:0] _adjustedSig_T = io_in_sig_0[53:41]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [40:0] _adjustedSig_T_1 = io_in_sig_0[40:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [13:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [5:0] _roundMask_T = sAdjustedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:110:24, :156:37]
wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56]
wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20]
wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20]
wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_44 = _roundMask_T_43; // @[primitives.scala:77:20]
wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :159:42, :174:32]
wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {{12{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:110:24, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [10:0] _common_overflow_T = sRoundedExp[14:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 11'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 15'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
wire [8:0] _common_underflow_T = sAdjustedExp[13:5]; // @[RoundAnyRawFNToRecFN.scala:110:24, :220:49]
wire _common_underflow_T_1 = $signed(_common_underflow_T) < 9'sh1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheControl :
input clock : Clock
input reset : Reset
output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip flush_match : UInt<1>, flush_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip flush_resp : UInt<1>}
wire ctrlnodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate ctrlnodeIn.d.bits.corrupt
invalidate ctrlnodeIn.d.bits.data
invalidate ctrlnodeIn.d.bits.denied
invalidate ctrlnodeIn.d.bits.sink
invalidate ctrlnodeIn.d.bits.source
invalidate ctrlnodeIn.d.bits.size
invalidate ctrlnodeIn.d.bits.param
invalidate ctrlnodeIn.d.bits.opcode
invalidate ctrlnodeIn.d.valid
invalidate ctrlnodeIn.d.ready
invalidate ctrlnodeIn.a.bits.corrupt
invalidate ctrlnodeIn.a.bits.data
invalidate ctrlnodeIn.a.bits.mask
invalidate ctrlnodeIn.a.bits.address
invalidate ctrlnodeIn.a.bits.source
invalidate ctrlnodeIn.a.bits.size
invalidate ctrlnodeIn.a.bits.param
invalidate ctrlnodeIn.a.bits.opcode
invalidate ctrlnodeIn.a.valid
invalidate ctrlnodeIn.a.ready
inst monitor of TLMonitor_36
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, ctrlnodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, ctrlnodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, ctrlnodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, ctrlnodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, ctrlnodeIn.d.bits.source
connect monitor.io.in.d.bits.size, ctrlnodeIn.d.bits.size
connect monitor.io.in.d.bits.param, ctrlnodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, ctrlnodeIn.d.bits.opcode
connect monitor.io.in.d.valid, ctrlnodeIn.d.valid
connect monitor.io.in.d.ready, ctrlnodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, ctrlnodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, ctrlnodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, ctrlnodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, ctrlnodeIn.a.bits.address
connect monitor.io.in.a.bits.source, ctrlnodeIn.a.bits.source
connect monitor.io.in.a.bits.size, ctrlnodeIn.a.bits.size
connect monitor.io.in.a.bits.param, ctrlnodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, ctrlnodeIn.a.bits.opcode
connect monitor.io.in.a.valid, ctrlnodeIn.a.valid
connect monitor.io.in.a.ready, ctrlnodeIn.a.ready
connect ctrlnodeIn, auto.ctrl_in
regreset flushInValid : UInt<1>, clock, reset, UInt<1>(0h0)
reg flushInAddress : UInt<64>, clock
regreset flushOutValid : UInt<1>, clock, reset, UInt<1>(0h0)
wire flushOutReady : UInt<1>
connect flushOutReady, UInt<1>(0h0)
when flushOutReady :
connect flushOutValid, UInt<1>(0h0)
when io.flush_resp :
connect flushOutValid, UInt<1>(0h1)
when io.flush_req.ready :
connect flushInValid, UInt<1>(0h0)
connect io.flush_req.valid, flushInValid
connect io.flush_req.bits, flushInAddress
node _T = eq(io.flush_match, UInt<1>(0h0))
node _T_1 = and(_T, flushInValid)
when _T_1 :
connect flushInValid, UInt<1>(0h0)
connect flushOutValid, UInt<1>(0h1)
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<13>, size : UInt<2>}}}}
node _in_bits_read_T = eq(ctrlnodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(ctrlnodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, ctrlnodeIn.a.bits.data
connect in.bits.mask, ctrlnodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, ctrlnodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, ctrlnodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<13>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<13>, size : UInt<2>}}}}
connect out_front.bits, in.bits
inst out_back_front_q of Queue1_RegMapperInput_i9_m8
connect out_back_front_q.clock, clock
connect out_back_front_q.reset, reset
connect out_back_front_q.io.enq, out_front
node out_maskMatch = not(UInt<9>(0h48))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
node _out_T_2 = eq(out_findex, UInt<9>(0h0))
node _out_T_3 = eq(out_bindex, UInt<9>(0h0))
node _out_T_4 = eq(out_findex, UInt<9>(0h0))
node _out_T_5 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[6]
wire out_wivalid : UInt<1>[6]
wire out_roready : UInt<1>[6]
wire out_woready : UInt<1>[6]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 7, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 7, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 7, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 7, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_6 = bits(out_back_front_q.io.deq.bits.data, 7, 0)
node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1))
node _out_T_8 = and(UInt<1>(0h1), out_f_roready)
node _out_T_9 = eq(out_rimask, UInt<1>(0h0))
node _out_T_10 = eq(out_wimask, UInt<1>(0h0))
node _out_T_11 = eq(out_romask, UInt<1>(0h0))
node _out_T_12 = eq(out_womask, UInt<1>(0h0))
node _out_T_13 = or(UInt<1>(0h1), UInt<8>(0h0))
node _out_T_14 = bits(_out_T_13, 7, 0)
node _out_rimask_T_1 = bits(out_frontMask, 15, 8)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 15, 8)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 15, 8)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 15, 8)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_15 = bits(out_back_front_q.io.deq.bits.data, 15, 8)
node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_18 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_19 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_20 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_14, UInt<8>(0h0))
node out_prepend = cat(UInt<4>(0h8), _out_prepend_T)
node _out_T_22 = or(out_prepend, UInt<16>(0h0))
node _out_T_23 = bits(_out_T_22, 15, 0)
node _out_rimask_T_2 = bits(out_frontMask, 23, 16)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 23, 16)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 23, 16)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 23, 16)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_24 = bits(out_back_front_q.io.deq.bits.data, 23, 16)
node _out_T_25 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_26 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_29 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_30 = eq(out_womask_2, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_23, UInt<16>(0h0))
node out_prepend_1 = cat(UInt<4>(0ha), _out_prepend_T_1)
node _out_T_31 = or(out_prepend_1, UInt<24>(0h0))
node _out_T_32 = bits(_out_T_31, 23, 0)
node _out_rimask_T_3 = bits(out_frontMask, 31, 24)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 31, 24)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 31, 24)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 31, 24)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
node _out_T_33 = bits(out_back_front_q.io.deq.bits.data, 31, 24)
node _out_T_34 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_35 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_36 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_37 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_38 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_39 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_32, UInt<24>(0h0))
node out_prepend_2 = cat(UInt<3>(0h6), _out_prepend_T_2)
node _out_T_40 = or(out_prepend_2, UInt<32>(0h0))
node _out_T_41 = bits(_out_T_40, 31, 0)
node _out_rimask_T_4 = bits(out_frontMask, 63, 0)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 63, 0)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 63, 0)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 63, 0)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_42 = bits(out_front.bits.data, 63, 0)
when out_f_woready_4 :
connect flushOutReady, UInt<1>(0h1)
when out_f_wivalid_4 :
connect flushInValid, UInt<1>(0h1)
node _out_T_43 = eq(flushInValid, UInt<1>(0h0))
node _out_T_44 = and(out_f_wivalid_4, _out_T_43)
when _out_T_44 :
connect flushInAddress, _out_T_42
node out_f_wiready = eq(flushInValid, UInt<1>(0h0))
node _out_T_45 = and(out_f_wivalid_4, out_f_wiready)
node _out_T_46 = and(flushOutValid, out_f_woready_4)
node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_49 = or(out_f_wiready, _out_T_48)
node _out_T_50 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_51 = eq(out_womask_4, UInt<1>(0h0))
node _out_T_52 = or(flushOutValid, _out_T_51)
node _out_T_53 = or(UInt<1>(0h0), UInt<64>(0h0))
node _out_T_54 = bits(_out_T_53, 63, 0)
node _out_rimask_T_5 = bits(out_frontMask, 31, 0)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 31, 0)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 31, 0)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 31, 0)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_55 = bits(out_front.bits.data, 31, 0)
when out_f_woready_5 :
connect flushOutReady, UInt<1>(0h1)
when out_f_wivalid_5 :
connect flushInValid, UInt<1>(0h1)
node _out_T_56 = eq(flushInValid, UInt<1>(0h0))
node _out_T_57 = and(out_f_wivalid_5, _out_T_56)
when _out_T_57 :
node _out_flushInAddress_T = shl(_out_T_55, 4)
connect flushInAddress, _out_flushInAddress_T
node out_f_wiready_1 = eq(flushInValid, UInt<1>(0h0))
node _out_T_58 = and(out_f_wivalid_5, out_f_wiready_1)
node _out_T_59 = and(flushOutValid, out_f_woready_5)
node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_62 = or(out_f_wiready_1, _out_T_61)
node _out_T_63 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_64 = eq(out_womask_5, UInt<1>(0h0))
node _out_T_65 = or(flushOutValid, _out_T_64)
node _out_T_66 = or(UInt<1>(0h0), UInt<32>(0h0))
node _out_T_67 = bits(_out_T_66, 31, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_iindex = cat(_out_iindex_T_6, _out_iindex_T_3)
node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8)
node out_oindex = cat(_out_oindex_T_6, _out_oindex_T_3)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[3], _out_rifireMux_T_3
connect out_rivalid[2], _out_rifireMux_T_3
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1))
connect out_rifireMux_out_1, UInt<1>(0h1)
node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[4], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_4)
connect out_rifireMux_out_3, UInt<1>(0h1)
connect out_rivalid[5], _out_rifireMux_T_15
node _out_rifireMux_T_16 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4))
wire _out_rifireMux_WIRE : UInt<1>[4]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[3], _out_wifireMux_T_4
connect out_wivalid[2], _out_wifireMux_T_4
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1))
connect out_wifireMux_out_1, UInt<1>(0h1)
node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2)
node out_wifireMux_all = and(_out_wifireMux_T_12, _out_T_49)
connect out_wifireMux_out_2, _out_T_49
connect out_wivalid[4], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_4)
node out_wifireMux_all_1 = and(_out_wifireMux_T_16, _out_T_62)
connect out_wifireMux_out_3, _out_T_62
connect out_wivalid[5], _out_wifireMux_T_16
node _out_wifireMux_T_17 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4))
wire _out_wifireMux_WIRE : UInt<1>[4]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[3], _out_rofireMux_T_3
connect out_roready[2], _out_rofireMux_T_3
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1))
connect out_rofireMux_out_1, UInt<1>(0h1)
node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[4], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_5)
connect out_rofireMux_out_3, UInt<1>(0h1)
connect out_roready[5], _out_rofireMux_T_15
node _out_rofireMux_T_16 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4))
wire _out_rofireMux_WIRE : UInt<1>[4]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[3], _out_wofireMux_T_4
connect out_woready[2], _out_wofireMux_T_4
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1))
connect out_wofireMux_out_1, UInt<1>(0h1)
node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3)
node out_wofireMux_all = and(_out_wofireMux_T_12, _out_T_52)
connect out_wofireMux_out_2, _out_T_52
connect out_woready[4], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_5)
node out_wofireMux_all_1 = and(_out_wofireMux_T_16, _out_T_65)
connect out_wofireMux_out_3, _out_T_65
connect out_woready[5], _out_wofireMux_T_16
node _out_wofireMux_T_17 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4))
wire _out_wofireMux_WIRE : UInt<1>[4]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_q_io_deq_ready_T = and(out.ready, out_oready)
connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T
node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_back_front_q.io.deq.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE : UInt<1>[4]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], UInt<1>(0h1)
connect _out_out_bits_data_WIRE[2], _out_T_3
connect _out_out_bits_data_WIRE[3], _out_T_5
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE_1 : UInt<64>[4]
connect _out_out_bits_data_WIRE_1[0], _out_T_41
connect _out_out_bits_data_WIRE_1[1], UInt<1>(0h0)
connect _out_out_bits_data_WIRE_1[2], _out_T_54
connect _out_out_bits_data_WIRE_1[3], _out_T_67
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_back_front_q.io.deq.bits.extra
connect in.valid, ctrlnodeIn.a.valid
connect ctrlnodeIn.a.ready, in.ready
connect ctrlnodeIn.d.valid, out.valid
connect out.ready, ctrlnodeIn.d.ready
wire ctrlnodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect ctrlnodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect ctrlnodeIn_d_bits_d.param, UInt<1>(0h0)
connect ctrlnodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect ctrlnodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect ctrlnodeIn_d_bits_d.sink, UInt<1>(0h0)
connect ctrlnodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate ctrlnodeIn_d_bits_d.data
connect ctrlnodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect ctrlnodeIn.d.bits.corrupt, ctrlnodeIn_d_bits_d.corrupt
connect ctrlnodeIn.d.bits.data, ctrlnodeIn_d_bits_d.data
connect ctrlnodeIn.d.bits.denied, ctrlnodeIn_d_bits_d.denied
connect ctrlnodeIn.d.bits.sink, ctrlnodeIn_d_bits_d.sink
connect ctrlnodeIn.d.bits.source, ctrlnodeIn_d_bits_d.source
connect ctrlnodeIn.d.bits.size, ctrlnodeIn_d_bits_d.size
connect ctrlnodeIn.d.bits.param, ctrlnodeIn_d_bits_d.param
connect ctrlnodeIn.d.bits.opcode, ctrlnodeIn_d_bits_d.opcode
connect ctrlnodeIn.d.bits.data, out.bits.data
node _ctrlnodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect ctrlnodeIn.d.bits.opcode, _ctrlnodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<13>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<13>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
extmodule plusarg_reader_74 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_75 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module InclusiveCacheControl( // @[Control.scala:38:9]
input clock, // @[Control.scala:38:9]
input reset, // @[Control.scala:38:9]
output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_flush_match, // @[Control.scala:39:16]
input io_flush_req_ready, // @[Control.scala:39:16]
output io_flush_req_valid, // @[Control.scala:39:16]
output [63:0] io_flush_req_bits, // @[Control.scala:39:16]
input io_flush_resp // @[Control.scala:39:16]
);
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9]
wire [12:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9]
wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9]
wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9]
wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9]
wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9]
wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9]
wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9]
wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9]
wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801};
wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48]
wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9]
wire [12:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9]
wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9]
wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9]
wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9]
wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
wire [12:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
wire io_flush_req_valid_0; // @[Control.scala:38:9]
wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9]
wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [12:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9]
wire [12:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9]
reg flushInValid; // @[Control.scala:45:33]
assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33]
reg [63:0] flushInAddress; // @[Control.scala:46:29]
assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29]
reg flushOutValid; // @[Control.scala:47:33]
wire flushOutReady; // @[Control.scala:48:34]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23]
wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24]
wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8]
wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23]
wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24]
wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24]
wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23]
wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10]
wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10]
wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10]
assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}]
always @(posedge clock) begin // @[Control.scala:38:9]
if (reset) begin // @[Control.scala:38:9]
flushInValid <= 1'h0; // @[Control.scala:45:33]
flushOutValid <= 1'h0; // @[Control.scala:47:33]
end
else begin // @[Control.scala:38:9]
flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24]
flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21]
end
if (_out_T_57) // @[Control.scala:64:20]
flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}]
else if (_out_T_44) // @[Control.scala:71:20]
flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24]
always @(posedge)
TLMonitor_36 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24]
.clock (clock),
.reset (reset),
.io_enq_ready (out_front_ready),
.io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24]
.io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24]
.io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24]
.io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24]
.io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_out_back_front_q_io_deq_valid),
.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
.io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source),
.io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size)
); // @[RegisterRouter.scala:87:24]
assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9]
assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PTW_6 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}}
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
wire l2_refill_wire : UInt<1>
inst arb of Arbiter2_Valid_PTWReq_6
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], io.requestor[0].req
connect arb.io.in[1], io.requestor[1].req
node _arb_io_out_ready_T = eq(state, UInt<3>(0h0))
node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0))
node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1)
connect arb.io.out.ready, _arb_io_out_ready_T_2
wire _resp_valid_WIRE : UInt<1>[2]
connect _resp_valid_WIRE[0], UInt<1>(0h0)
connect _resp_valid_WIRE[1], UInt<1>(0h0)
reg resp_valid : UInt<1>[2], clock
connect resp_valid, _resp_valid_WIRE
node _clock_en_T = neq(state, UInt<3>(0h0))
node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire)
node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid)
node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid)
node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0)
node clock_en = or(_clock_en_T_3, _clock_en_T_4)
node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en)
connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T
reg invalidated : UInt<1>, clock
reg count : UInt<2>, clock
reg resp_ae_ptw : UInt<1>, clock
reg resp_ae_final : UInt<1>, clock
reg resp_pf : UInt<1>, clock
reg resp_gf : UInt<1>, clock
reg resp_hr : UInt<1>, clock
reg resp_hw : UInt<1>, clock
reg resp_hx : UInt<1>, clock
reg resp_fragmented_superpage : UInt<1>, clock
reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock
reg r_req_dest : UInt, clock
reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg aux_count : UInt<2>, clock
reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg gpa_pgoff : UInt<12>, clock
reg stage2 : UInt<1>, clock
reg stage2_final : UInt<1>, clock
node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1)
node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0))
node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1)
node do_both_stages = and(r_req.vstage1, r_req.stage2)
node _max_count_T = lt(count, aux_count)
node max_count = mux(_max_count_T, aux_count, count)
node _vpn_T = and(r_req.vstage1, stage2)
node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr)
reg mem_resp_valid : UInt<1>, clock
connect mem_resp_valid, io.mem.resp.valid
reg mem_resp_data : UInt, clock
connect mem_resp_data, io.mem.resp.bits.data
wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
wire _tmp_WIRE : UInt<64>
connect _tmp_WIRE, mem_resp_data
node _tmp_T = bits(_tmp_WIRE, 0, 0)
connect tmp.v, _tmp_T
node _tmp_T_1 = bits(_tmp_WIRE, 1, 1)
connect tmp.r, _tmp_T_1
node _tmp_T_2 = bits(_tmp_WIRE, 2, 2)
connect tmp.w, _tmp_T_2
node _tmp_T_3 = bits(_tmp_WIRE, 3, 3)
connect tmp.x, _tmp_T_3
node _tmp_T_4 = bits(_tmp_WIRE, 4, 4)
connect tmp.u, _tmp_T_4
node _tmp_T_5 = bits(_tmp_WIRE, 5, 5)
connect tmp.g, _tmp_T_5
node _tmp_T_6 = bits(_tmp_WIRE, 6, 6)
connect tmp.a, _tmp_T_6
node _tmp_T_7 = bits(_tmp_WIRE, 7, 7)
connect tmp.d, _tmp_T_7
node _tmp_T_8 = bits(_tmp_WIRE, 9, 8)
connect tmp.reserved_for_software, _tmp_T_8
node _tmp_T_9 = bits(_tmp_WIRE, 53, 10)
connect tmp.ppn, _tmp_T_9
node _tmp_T_10 = bits(_tmp_WIRE, 63, 54)
connect tmp.reserved_for_future, _tmp_T_10
wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect pte, tmp
node _res_ppn_T = eq(stage2, UInt<1>(0h0))
node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T)
node _res_ppn_T_2 = bits(tmp.ppn, 26, 0)
node _res_ppn_T_3 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3)
connect pte.ppn, _res_ppn_T_4
node _T = or(tmp.r, tmp.w)
node _T_1 = or(_T, tmp.x)
when _T_1 :
node _T_2 = leq(count, UInt<1>(0h0))
node _T_3 = bits(tmp.ppn, 17, 9)
node _T_4 = neq(_T_3, UInt<1>(0h0))
node _T_5 = and(_T_2, _T_4)
when _T_5 :
connect pte.v, UInt<1>(0h0)
node _T_6 = leq(count, UInt<1>(0h1))
node _T_7 = bits(tmp.ppn, 8, 0)
node _T_8 = neq(_T_7, UInt<1>(0h0))
node _T_9 = and(_T_6, _T_8)
when _T_9 :
connect pte.v, UInt<1>(0h0)
node _T_10 = eq(stage2, UInt<1>(0h0))
node _T_11 = and(do_both_stages, _T_10)
node _T_12 = shr(tmp.ppn, 27)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = shr(tmp.ppn, 20)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node invalid_paddr = mux(_T_11, _T_13, _T_15)
node _T_16 = eq(stage2, UInt<1>(0h0))
node _T_17 = and(do_both_stages, _T_16)
node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _count_T_1 = tail(_count_T, 1)
node _count_T_2 = sub(_count_T_1, UInt<1>(0h0))
node count_1 = tail(_count_T_2, 1)
node idxs_0 = shr(tmp.ppn, 29)
wire _WIRE : UInt<15>[1]
connect _WIRE[0], idxs_0
node _T_18 = or(count_1, UInt<0>(0h0))
node _T_19 = neq(_WIRE[0], UInt<1>(0h0))
node invalid_gpa = and(_T_17, _T_19)
node _traverse_T = eq(pte.r, UInt<1>(0h0))
node _traverse_T_1 = and(pte.v, _traverse_T)
node _traverse_T_2 = eq(pte.w, UInt<1>(0h0))
node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2)
node _traverse_T_4 = eq(pte.x, UInt<1>(0h0))
node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4)
node _traverse_T_6 = eq(pte.d, UInt<1>(0h0))
node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6)
node _traverse_T_8 = eq(pte.a, UInt<1>(0h0))
node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8)
node _traverse_T_10 = eq(pte.u, UInt<1>(0h0))
node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10)
node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12)
node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0))
node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14)
node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0))
node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16)
node _traverse_T_18 = lt(count, UInt<2>(0h2))
node traverse = and(_traverse_T_17, _traverse_T_18)
node _pte_addr_vpn_idxs_T = shr(vpn, 18)
node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0)
node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9)
node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0)
node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0)
node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0)
node _pte_addr_mask_T = eq(count, r_hgatp_initial_count)
node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T)
node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff))
node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1))
node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0)
node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2))
node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1)
node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3))
node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3)
node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask)
node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9)
node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx)
node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3)
node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags : UInt<32>[8], clock
reg data : UInt<20>[8], clock
node _can_hit_T = lt(count, UInt<2>(0h2))
node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0))
node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1)
node can_hit = and(_can_hit_T, _can_hit_T_2)
node tag = cat(r_req.vstage1, pte_addr)
node _hits_T = eq(tags[0], tag)
node _hits_T_1 = eq(tags[1], tag)
node _hits_T_2 = eq(tags[2], tag)
node _hits_T_3 = eq(tags[3], tag)
node _hits_T_4 = eq(tags[4], tag)
node _hits_T_5 = eq(tags[5], tag)
node _hits_T_6 = eq(tags[6], tag)
node _hits_T_7 = eq(tags[7], tag)
node hits_lo_lo = cat(_hits_T_1, _hits_T)
node hits_lo_hi = cat(_hits_T_3, _hits_T_2)
node hits_lo = cat(hits_lo_hi, hits_lo_lo)
node hits_hi_lo = cat(_hits_T_5, _hits_T_4)
node hits_hi_hi = cat(_hits_T_7, _hits_T_6)
node hits_hi = cat(hits_hi_hi, hits_hi_lo)
node _hits_T_8 = cat(hits_hi, hits_lo)
node hits = and(_hits_T_8, valid)
node _hit_T = orr(hits)
node pte_cache_hit = and(_hit_T, can_hit)
node _T_20 = and(mem_resp_valid, traverse)
node _T_21 = and(_T_20, can_hit)
node _T_22 = orr(hits)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = and(_T_21, _T_23)
node _T_25 = eq(invalidated, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
when _T_26 :
node _r_T = andr(valid)
node r_left_subtree_older = bits(state_reg, 6, 6)
node r_left_subtree_state = bits(state_reg, 5, 3)
node r_right_subtree_state = bits(state_reg, 2, 0)
node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2)
node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1)
node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0)
node _r_T_1 = bits(r_left_subtree_state_1, 0, 0)
node _r_T_2 = bits(r_right_subtree_state_1, 0, 0)
node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2)
node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3)
node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2)
node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1)
node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0)
node _r_T_5 = bits(r_left_subtree_state_2, 0, 0)
node _r_T_6 = bits(r_right_subtree_state_2, 0, 0)
node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6)
node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7)
node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8)
node _r_T_10 = cat(r_left_subtree_older, _r_T_9)
node _r_T_11 = not(valid)
node _r_T_12 = bits(_r_T_11, 0, 0)
node _r_T_13 = bits(_r_T_11, 1, 1)
node _r_T_14 = bits(_r_T_11, 2, 2)
node _r_T_15 = bits(_r_T_11, 3, 3)
node _r_T_16 = bits(_r_T_11, 4, 4)
node _r_T_17 = bits(_r_T_11, 5, 5)
node _r_T_18 = bits(_r_T_11, 6, 6)
node _r_T_19 = bits(_r_T_11, 7, 7)
node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20)
node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21)
node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22)
node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23)
node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24)
node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25)
node r = mux(_r_T, _r_T_10, _r_T_26)
node _valid_T = dshl(UInt<1>(0h1), r)
node _valid_T_1 = or(valid, _valid_T)
connect valid, _valid_T_1
connect tags[r], tag
connect data[r], pte.ppn
node state_reg_touch_way_sized = bits(r, 2, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 5, 3)
node state_reg_right_subtree_state = bits(state_reg, 2, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0))
node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3)
node _state_reg_T_5 = bits(_state_reg_T, 0, 0)
node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0)
node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0))
node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1)
node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4)
node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8)
node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9)
node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0)
node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0)
node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0))
node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14)
node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0)
node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0))
node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2)
node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15)
node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19)
node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state)
node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10)
node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21)
connect state_reg, _state_reg_T_22
node _T_27 = eq(state, UInt<3>(0h1))
node _T_28 = and(pte_cache_hit, _T_27)
when _T_28 :
node hi = bits(hits, 7, 4)
node lo = bits(hits, 3, 0)
node _T_29 = orr(hi)
node _T_30 = or(hi, lo)
node hi_1 = bits(_T_30, 3, 2)
node lo_1 = bits(_T_30, 1, 0)
node _T_31 = orr(hi_1)
node _T_32 = or(hi_1, lo_1)
node _T_33 = bits(_T_32, 1, 1)
node _T_34 = cat(_T_31, _T_33)
node _T_35 = cat(_T_29, _T_34)
node state_reg_touch_way_sized_1 = bits(_T_35, 2, 0)
node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3)
node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0)
node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1)
node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0))
node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0)
node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0))
node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26)
node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0)
node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0))
node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4)
node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27)
node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31)
node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32)
node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1)
node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0))
node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0)
node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0)
node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0))
node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37)
node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0)
node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0))
node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5)
node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38)
node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42)
node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3)
node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33)
node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44)
connect state_reg, _state_reg_T_45
node _T_36 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_37 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_38 = or(_T_36, _T_37)
node _T_39 = and(io.dpath.sfence.valid, _T_38)
when _T_39 :
connect valid, UInt<1>(0h0)
node _T_40 = eq(state, UInt<3>(0h1))
node _T_41 = and(pte_cache_hit, _T_40)
node _T_42 = eq(count, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(state, UInt<3>(0h1))
node _T_45 = and(pte_cache_hit, _T_44)
node _T_46 = eq(count, UInt<1>(0h1))
node _T_47 = and(_T_45, _T_46)
node _T_48 = bits(hits, 0, 0)
node _T_49 = bits(hits, 1, 1)
node _T_50 = bits(hits, 2, 2)
node _T_51 = bits(hits, 3, 3)
node _T_52 = bits(hits, 4, 4)
node _T_53 = bits(hits, 5, 5)
node _T_54 = bits(hits, 6, 6)
node _T_55 = bits(hits, 7, 7)
node _T_56 = mux(_T_48, data[0], UInt<1>(0h0))
node _T_57 = mux(_T_49, data[1], UInt<1>(0h0))
node _T_58 = mux(_T_50, data[2], UInt<1>(0h0))
node _T_59 = mux(_T_51, data[3], UInt<1>(0h0))
node _T_60 = mux(_T_52, data[4], UInt<1>(0h0))
node _T_61 = mux(_T_53, data[5], UInt<1>(0h0))
node _T_62 = mux(_T_54, data[6], UInt<1>(0h0))
node _T_63 = mux(_T_55, data[7], UInt<1>(0h0))
node _T_64 = or(_T_56, _T_57)
node _T_65 = or(_T_64, _T_58)
node _T_66 = or(_T_65, _T_59)
node _T_67 = or(_T_66, _T_60)
node _T_68 = or(_T_67, _T_61)
node _T_69 = or(_T_68, _T_62)
node _T_70 = or(_T_69, _T_63)
wire pte_cache_data : UInt<20>
connect pte_cache_data, _T_70
regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags_1 : UInt<32>[8], clock
reg data_1 : UInt<20>[8], clock
node _can_hit_T_3 = eq(count, r_hgatp_initial_count)
node _can_hit_T_4 = lt(aux_count, UInt<2>(0h2))
node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4)
node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1)
node _can_hit_T_7 = and(_can_hit_T_6, stage2)
node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0))
node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8)
node _can_refill_T = eq(stage2, UInt<1>(0h0))
node _can_refill_T_1 = and(do_both_stages, _can_refill_T)
node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0))
node can_refill = and(_can_refill_T_1, _can_refill_T_2)
node _tag_T = cat(UInt<38>(0h0), UInt<1>(0h0))
node tag_1 = cat(UInt<1>(0h1), _tag_T)
node _hits_T_9 = eq(tags_1[0], tag_1)
node _hits_T_10 = eq(tags_1[1], tag_1)
node _hits_T_11 = eq(tags_1[2], tag_1)
node _hits_T_12 = eq(tags_1[3], tag_1)
node _hits_T_13 = eq(tags_1[4], tag_1)
node _hits_T_14 = eq(tags_1[5], tag_1)
node _hits_T_15 = eq(tags_1[6], tag_1)
node _hits_T_16 = eq(tags_1[7], tag_1)
node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9)
node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11)
node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1)
node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13)
node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15)
node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1)
node _hits_T_17 = cat(hits_hi_1, hits_lo_1)
node hits_1 = and(_hits_T_17, valid_1)
node _hit_T_1 = orr(hits_1)
node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1)
node _T_71 = and(mem_resp_valid, traverse)
node _T_72 = and(_T_71, can_refill)
node _T_73 = orr(hits_1)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = and(_T_72, _T_74)
node _T_76 = eq(invalidated, UInt<1>(0h0))
node _T_77 = and(_T_75, _T_76)
when _T_77 :
node _r_T_27 = andr(valid_1)
node r_left_subtree_older_3 = bits(state_reg_1, 6, 6)
node r_left_subtree_state_3 = bits(state_reg_1, 5, 3)
node r_right_subtree_state_3 = bits(state_reg_1, 2, 0)
node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2)
node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1)
node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0)
node _r_T_28 = bits(r_left_subtree_state_4, 0, 0)
node _r_T_29 = bits(r_right_subtree_state_4, 0, 0)
node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29)
node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30)
node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2)
node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1)
node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0)
node _r_T_32 = bits(r_left_subtree_state_5, 0, 0)
node _r_T_33 = bits(r_right_subtree_state_5, 0, 0)
node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33)
node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34)
node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35)
node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36)
node _r_T_38 = not(valid_1)
node _r_T_39 = bits(_r_T_38, 0, 0)
node _r_T_40 = bits(_r_T_38, 1, 1)
node _r_T_41 = bits(_r_T_38, 2, 2)
node _r_T_42 = bits(_r_T_38, 3, 3)
node _r_T_43 = bits(_r_T_38, 4, 4)
node _r_T_44 = bits(_r_T_38, 5, 5)
node _r_T_45 = bits(_r_T_38, 6, 6)
node _r_T_46 = bits(_r_T_38, 7, 7)
node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47)
node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48)
node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49)
node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50)
node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51)
node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52)
node r_1 = mux(_r_T_27, _r_T_37, _r_T_53)
node _valid_T_2 = dshl(UInt<1>(0h1), r_1)
node _valid_T_3 = or(valid_1, _valid_T_2)
connect valid_1, _valid_T_3
connect tags_1[r_1], tag_1
connect data_1[r_1], pte.ppn
node state_reg_touch_way_sized_2 = bits(r_1, 2, 0)
node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2)
node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0))
node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0)
node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1)
node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0))
node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0)
node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0)
node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0))
node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49)
node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0)
node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0))
node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7)
node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50)
node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54)
node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55)
node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1)
node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0))
node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0)
node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0)
node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0))
node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60)
node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0)
node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0))
node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8)
node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61)
node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65)
node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6)
node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56)
node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67)
connect state_reg_1, _state_reg_T_68
node _T_78 = eq(state, UInt<3>(0h1))
node _T_79 = and(stage2_pte_cache_hit, _T_78)
when _T_79 :
node hi_2 = bits(hits_1, 7, 4)
node lo_2 = bits(hits_1, 3, 0)
node _T_80 = orr(hi_2)
node _T_81 = or(hi_2, lo_2)
node hi_3 = bits(_T_81, 3, 2)
node lo_3 = bits(_T_81, 1, 0)
node _T_82 = orr(hi_3)
node _T_83 = or(hi_3, lo_3)
node _T_84 = bits(_T_83, 1, 1)
node _T_85 = cat(_T_82, _T_84)
node _T_86 = cat(_T_80, _T_85)
node state_reg_touch_way_sized_3 = bits(_T_86, 2, 0)
node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2)
node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0))
node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0)
node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1)
node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0))
node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0)
node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0)
node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0))
node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72)
node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0)
node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0))
node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10)
node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73)
node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77)
node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78)
node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1)
node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0))
node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0)
node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0)
node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0))
node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83)
node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0)
node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0))
node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11)
node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84)
node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88)
node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9)
node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79)
node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90)
connect state_reg_1, _state_reg_T_91
node _T_87 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_88 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_89 = or(_T_87, _T_88)
node _T_90 = and(io.dpath.sfence.valid, _T_89)
when _T_90 :
connect valid_1, UInt<1>(0h0)
node _T_91 = eq(state, UInt<3>(0h1))
node _T_92 = and(stage2_pte_cache_hit, _T_91)
node _T_93 = eq(aux_count, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(state, UInt<3>(0h1))
node _T_96 = and(stage2_pte_cache_hit, _T_95)
node _T_97 = eq(aux_count, UInt<1>(0h1))
node _T_98 = and(_T_96, _T_97)
node _T_99 = bits(hits_1, 0, 0)
node _T_100 = bits(hits_1, 1, 1)
node _T_101 = bits(hits_1, 2, 2)
node _T_102 = bits(hits_1, 3, 3)
node _T_103 = bits(hits_1, 4, 4)
node _T_104 = bits(hits_1, 5, 5)
node _T_105 = bits(hits_1, 6, 6)
node _T_106 = bits(hits_1, 7, 7)
node _T_107 = mux(_T_99, data_1[0], UInt<1>(0h0))
node _T_108 = mux(_T_100, data_1[1], UInt<1>(0h0))
node _T_109 = mux(_T_101, data_1[2], UInt<1>(0h0))
node _T_110 = mux(_T_102, data_1[3], UInt<1>(0h0))
node _T_111 = mux(_T_103, data_1[4], UInt<1>(0h0))
node _T_112 = mux(_T_104, data_1[5], UInt<1>(0h0))
node _T_113 = mux(_T_105, data_1[6], UInt<1>(0h0))
node _T_114 = mux(_T_106, data_1[7], UInt<1>(0h0))
node _T_115 = or(_T_107, _T_108)
node _T_116 = or(_T_115, _T_109)
node _T_117 = or(_T_116, _T_110)
node _T_118 = or(_T_117, _T_111)
node _T_119 = or(_T_118, _T_112)
node _T_120 = or(_T_119, _T_113)
node _T_121 = or(_T_120, _T_114)
wire stage2_pte_cache_data : UInt<20>
connect stage2_pte_cache_data, _T_121
reg pte_hit : UInt<1>, clock
connect pte_hit, UInt<1>(0h0)
connect io.dpath.perf.pte_miss, UInt<1>(0h0)
node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1))
node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T)
node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0))
node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2)
connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3
node _T_122 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit)
node _T_123 = and(io.dpath.perf.l2hit, _T_122)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf
assert(clock, _T_124, UInt<1>(0h1), "") : assert
reg l2_refill : UInt<1>, clock
connect l2_refill, UInt<1>(0h0)
connect l2_refill_wire, l2_refill
connect io.dpath.perf.l2miss, UInt<1>(0h0)
connect io.dpath.perf.l2hit, UInt<1>(0h0)
wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect _WIRE_1.v, UInt<1>(0h0)
connect _WIRE_1.r, UInt<1>(0h0)
connect _WIRE_1.w, UInt<1>(0h0)
connect _WIRE_1.x, UInt<1>(0h0)
connect _WIRE_1.u, UInt<1>(0h0)
connect _WIRE_1.g, UInt<1>(0h0)
connect _WIRE_1.a, UInt<1>(0h0)
connect _WIRE_1.d, UInt<1>(0h0)
connect _WIRE_1.reserved_for_software, UInt<2>(0h0)
connect _WIRE_1.ppn, UInt<44>(0h0)
connect _WIRE_1.reserved_for_future, UInt<10>(0h0)
wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect l2_pte, _WIRE_1
node _invalidated_T = neq(state, UInt<3>(0h0))
node _invalidated_T_1 = and(invalidated, _invalidated_T)
node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1)
connect invalidated, _invalidated_T_2
connect io.mem.keep_clock_enabled, UInt<1>(0h0)
node _io_mem_req_valid_T = eq(state, UInt<3>(0h1))
node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3))
node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1)
connect io.mem.req.valid, _io_mem_req_valid_T_2
connect io.mem.req.bits.phys, UInt<1>(0h1)
connect io.mem.req.bits.cmd, UInt<1>(0h0)
connect io.mem.req.bits.size, UInt<2>(0h3)
connect io.mem.req.bits.signed, UInt<1>(0h0)
connect io.mem.req.bits.addr, pte_addr
connect io.mem.req.bits.dprv, UInt<1>(0h1)
node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0))
node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T)
connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1
invalidate io.mem.req.bits.tag
connect io.mem.req.bits.no_resp, UInt<1>(0h0)
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.mask
node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2))
node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T)
node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf)
connect io.mem.s1_kill, _io_mem_s1_kill_T_2
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
connect io.mem.s2_kill, UInt<1>(0h0)
node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8)
node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10)
node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13)
node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15)
node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12)
node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17)
node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21)
node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23)
node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25)
node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28)
node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30)
node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32)
node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38)
node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000)))
node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40)
node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43)
node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45)
node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48)
node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50)
node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000))
node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53)
node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000)))
node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55)
node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000))
node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58)
node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60)
node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000))
node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63)
node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65)
node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68)
node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70)
node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73)
node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75)
node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000))
node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78)
node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80)
node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83)
node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85)
node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42)
node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47)
node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52)
node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57)
node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62)
node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67)
node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72)
node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77)
node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82)
node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87)
node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98)
node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100)
node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102)
node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105)
node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107)
node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110)
node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112)
node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115)
node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117)
node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120)
node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122)
node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125)
node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000)))
node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127)
node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109)
node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114)
node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119)
node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124)
node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129)
node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135)
node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000)))
node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137)
node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140)
node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142)
node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139)
node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144)
node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147)
node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149)
node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151)
node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154)
node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156)
node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158)
node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0))
node _pmaHomogeneous_T = eq(count, UInt<1>(0h1))
node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0))
node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2))
node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1)
node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3))
node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3)
node _pmpHomogeneous_T = shl(r_pte.ppn, 12)
wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0)
connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0)
connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0)
node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T)
node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4)
node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6)
node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2)
node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3))
node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4)
node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5)
node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30)
node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0))
node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9)
node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3))
node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11)
node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12)
node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21)
node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0))
node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16)
node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3))
node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18)
node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19)
node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12)
node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0))
node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8)
node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24)
node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26)
node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28)
node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0)
node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T)
node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2)
node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3)
node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T)
node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2)
node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3)
node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1)
node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3)
node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1)
node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3)
node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5)
node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1)
node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3)
node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5)
node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper)
node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper)
node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33)
node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34)
node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35)
node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36)
node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8)
node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12)
node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14)
node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39)
node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3))
node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41)
node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42)
node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30)
node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0))
node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46)
node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3))
node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48)
node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49)
node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21)
node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0))
node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53)
node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3))
node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55)
node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56)
node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12)
node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0))
node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45)
node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61)
node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63)
node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65)
node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0)
node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5)
node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7)
node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8)
node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5)
node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7)
node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8)
node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6)
node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8)
node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7)
node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9)
node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11)
node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7)
node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9)
node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11)
node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1)
node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1)
node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70)
node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71)
node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72)
node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73)
node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16)
node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20)
node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22)
node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76)
node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3))
node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78)
node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79)
node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30)
node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0))
node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83)
node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3))
node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85)
node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86)
node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21)
node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0))
node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90)
node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3))
node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92)
node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93)
node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12)
node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0))
node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82)
node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98)
node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100)
node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102)
node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0)
node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10)
node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12)
node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13)
node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10)
node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12)
node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13)
node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11)
node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13)
node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13)
node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15)
node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17)
node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13)
node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15)
node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17)
node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2)
node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2)
node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107)
node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108)
node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109)
node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110)
node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24)
node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28)
node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30)
node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113)
node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3))
node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115)
node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116)
node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30)
node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0))
node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120)
node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3))
node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122)
node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123)
node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21)
node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0))
node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127)
node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3))
node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129)
node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130)
node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12)
node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0))
node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119)
node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135)
node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137)
node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139)
node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0)
node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15)
node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17)
node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18)
node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15)
node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17)
node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18)
node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16)
node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18)
node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19)
node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21)
node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23)
node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19)
node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21)
node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23)
node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3)
node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3)
node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144)
node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145)
node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146)
node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147)
node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32)
node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36)
node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38)
node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150)
node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3))
node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152)
node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153)
node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30)
node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0))
node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157)
node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3))
node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159)
node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160)
node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21)
node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0))
node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164)
node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3))
node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166)
node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167)
node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12)
node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0))
node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156)
node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172)
node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174)
node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176)
node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0)
node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20)
node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22)
node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23)
node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20)
node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22)
node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23)
node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21)
node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23)
node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25)
node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27)
node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29)
node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25)
node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27)
node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29)
node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4)
node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4)
node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181)
node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182)
node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183)
node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184)
node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40)
node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44)
node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46)
node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187)
node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3))
node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189)
node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190)
node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30)
node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0))
node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194)
node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3))
node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196)
node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197)
node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21)
node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0))
node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201)
node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3))
node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203)
node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204)
node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12)
node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0))
node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193)
node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209)
node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211)
node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213)
node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0)
node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25)
node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27)
node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28)
node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25)
node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27)
node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28)
node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26)
node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28)
node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31)
node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33)
node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35)
node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31)
node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33)
node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35)
node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5)
node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5)
node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218)
node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219)
node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220)
node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221)
node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48)
node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52)
node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54)
node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224)
node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3))
node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226)
node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227)
node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30)
node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0))
node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231)
node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3))
node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233)
node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234)
node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21)
node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0))
node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238)
node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3))
node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240)
node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241)
node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12)
node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0))
node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230)
node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246)
node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248)
node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250)
node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0)
node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30)
node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32)
node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33)
node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30)
node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32)
node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33)
node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31)
node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33)
node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37)
node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39)
node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41)
node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37)
node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39)
node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41)
node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6)
node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6)
node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255)
node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256)
node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257)
node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258)
node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56)
node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60)
node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62)
node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261)
node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3))
node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263)
node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264)
node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30)
node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0))
node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268)
node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3))
node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270)
node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271)
node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21)
node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0))
node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275)
node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3))
node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277)
node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278)
node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12)
node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0))
node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267)
node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283)
node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285)
node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287)
node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0)
node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35)
node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37)
node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38)
node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35)
node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37)
node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38)
node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36)
node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38)
node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43)
node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45)
node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47)
node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43)
node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45)
node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47)
node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7)
node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7)
node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292)
node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293)
node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294)
node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295)
node homogeneous = and(pmaHomogeneous, pmpHomogeneous)
connect io.requestor[0].resp.valid, resp_valid[0]
connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[0].resp.bits.ae_final, resp_ae_final
connect io.requestor[0].resp.bits.pf, resp_pf
connect io.requestor[0].resp.bits.gf, resp_gf
connect io.requestor[0].resp.bits.hr, resp_hr
connect io.requestor[0].resp.bits.hw, resp_hw
connect io.requestor[0].resp.bits.hx, resp_hx
connect io.requestor[0].resp.bits.pte, r_pte
connect io.requestor[0].resp.bits.level, max_count
node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T
node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T
connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1)
node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3)
node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6)
node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9)
node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7)
node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12)
node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14
node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T
connect io.requestor[0].ptbr, io.dpath.ptbr
connect io.requestor[0].hgatp, io.dpath.hgatp
connect io.requestor[0].vsatp, io.dpath.vsatp
connect io.requestor[0].customCSRs, io.dpath.customCSRs
connect io.requestor[0].status, io.dpath.status
connect io.requestor[0].hstatus, io.dpath.hstatus
connect io.requestor[0].gstatus, io.dpath.gstatus
connect io.requestor[0].pmp, io.dpath.pmp
connect io.requestor[1].resp.valid, resp_valid[1]
connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[1].resp.bits.ae_final, resp_ae_final
connect io.requestor[1].resp.bits.pf, resp_pf
connect io.requestor[1].resp.bits.gf, resp_gf
connect io.requestor[1].resp.bits.hr, resp_hr
connect io.requestor[1].resp.bits.hw, resp_hw
connect io.requestor[1].resp.bits.hx, resp_hx
connect io.requestor[1].resp.bits.pte, r_pte
connect io.requestor[1].resp.bits.level, max_count
node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T
node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T
connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1)
node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3)
node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6)
node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9)
node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7)
node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12)
node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14
node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T
connect io.requestor[1].ptbr, io.dpath.ptbr
connect io.requestor[1].hgatp, io.dpath.hgatp
connect io.requestor[1].vsatp, io.dpath.vsatp
connect io.requestor[1].customCSRs, io.dpath.customCSRs
connect io.requestor[1].status, io.dpath.status
connect io.requestor[1].hstatus, io.dpath.hstatus
connect io.requestor[1].gstatus, io.dpath.gstatus
connect io.requestor[1].pmp, io.dpath.pmp
wire next_state : UInt
connect next_state, state
inst state_barrier of OptimizationBarrier_UInt_6
connect state_barrier.clock, clock
connect state_barrier.reset, reset
connect state_barrier.io.x, next_state
connect state, state_barrier.io.y
wire do_switch : UInt<1>
connect do_switch, UInt<1>(0h0)
node _T_128 = eq(UInt<3>(0h0), state)
when _T_128 :
node _T_129 = and(arb.io.out.ready, arb.io.out.valid)
when _T_129 :
node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1)
node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0))
node satp_initial_count = tail(_satp_initial_count_T_2, 1)
node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1)
node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0))
node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1)
node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1)
node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0))
node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1)
node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
connect r_req, arb.io.out.bits.bits
connect r_req_dest, arb.io.chosen
node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0))
connect next_state, _next_state_T
connect stage2, arb.io.out.bits.bits.stage2
node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0))
node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T)
connect stage2_final, _stage2_final_T_1
node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
connect count, _count_T_3
node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0))
connect aux_count, _aux_count_T
connect aux_pte.ppn, aux_ppn
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect resp_ae_ptw, UInt<1>(0h0)
connect resp_ae_final, UInt<1>(0h0)
connect resp_pf, UInt<1>(0h0)
node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1)
node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0))
node resp_gf_count = tail(_resp_gf_count_T_2, 1)
node resp_gf_idxs_0 = shr(aux_ppn, 29)
wire _resp_gf_WIRE : UInt<15>[1]
connect _resp_gf_WIRE[0], resp_gf_idxs_0
node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0))
node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0))
node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2)
connect resp_gf, _resp_gf_T_2
connect resp_hr, UInt<1>(0h1)
connect resp_hw, UInt<1>(0h1)
connect resp_hx, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h0)
connect r_hgatp, io.dpath.hgatp
node _T_130 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0))
node _T_131 = or(_T_130, arb.io.out.bits.bits.stage2)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
else :
node _T_135 = eq(UInt<3>(0h1), state)
when _T_135 :
node _T_136 = eq(count, r_hgatp_initial_count)
node _T_137 = and(stage2, _T_136)
when _T_137 :
node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2))
node _gpa_pgoff_T_1 = shl(r_req.addr, 3)
node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0))
connect gpa_pgoff, _gpa_pgoff_T_2
when stage2_pte_cache_hit :
node _aux_count_T_1 = add(aux_count, UInt<1>(0h1))
node _aux_count_T_2 = tail(_aux_count_T_1, 1)
connect aux_count, _aux_count_T_2
connect aux_pte.ppn, stage2_pte_cache_data
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect pte_hit, UInt<1>(0h1)
else :
when pte_cache_hit :
node _count_T_4 = add(count, UInt<1>(0h1))
node _count_T_5 = tail(_count_T_4, 1)
connect count, _count_T_5
connect pte_hit, UInt<1>(0h1)
else :
node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1))
connect next_state, _next_state_T_1
when resp_gf :
connect next_state, UInt<3>(0h0)
node _T_138 = or(r_req_dest, UInt<1>(0h0))
node _T_139 = bits(_T_138, 0, 0)
connect resp_valid[_T_139], UInt<1>(0h1)
else :
node _T_140 = eq(UInt<3>(0h2), state)
when _T_140 :
node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4))
connect next_state, _next_state_T_2
else :
node _T_141 = eq(UInt<3>(0h4), state)
when _T_141 :
connect next_state, UInt<3>(0h5)
node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2))
connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T
when io.mem.s2_xcpt.ae.ld :
connect resp_ae_ptw, UInt<1>(0h1)
connect next_state, UInt<3>(0h0)
node _T_142 = or(r_req_dest, UInt<1>(0h0))
node _T_143 = bits(_T_142, 0, 0)
connect resp_valid[_T_143], UInt<1>(0h1)
else :
node _T_144 = eq(UInt<3>(0h7), state)
when _T_144 :
connect next_state, UInt<3>(0h0)
node _T_145 = or(r_req_dest, UInt<1>(0h0))
node _T_146 = bits(_T_145, 0, 0)
connect resp_valid[_T_146], UInt<1>(0h1)
node _T_147 = eq(homogeneous, UInt<1>(0h0))
when _T_147 :
connect count, UInt<2>(0h2)
connect resp_fragmented_superpage, UInt<1>(0h1)
when do_both_stages :
connect resp_fragmented_superpage, UInt<1>(0h1)
node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1))
node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000))
node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2)
node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3))
node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4)
node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18)
node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0)
node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1)
node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0)
node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3)
node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1))
node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0)
node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2))
node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1)
node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3))
node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3)
node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask)
wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect merged_pte, aux_pte
connect merged_pte.ppn, _merged_pte_T
node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T)
node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0))
node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2)
node _r_pte_T_4 = eq(state, UInt<3>(0h1))
node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit)
node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_1 = tail(_r_pte_count_T, 1)
node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0))
node r_pte_count = tail(_r_pte_count_T_2, 1)
node r_pte_idxs_0 = shr(stage2_pte_cache_data, 27)
wire r_pte_lsbs : UInt<2>
connect r_pte_lsbs, r_pte_idxs_0
wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte, l2_pte
node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs)
connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1
node _r_pte_T_6 = eq(state, UInt<3>(0h1))
node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit)
wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_1, l2_pte
connect r_pte_pte_1.ppn, pte_cache_data
node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1)
node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0))
node r_pte_count_1 = tail(_r_pte_count_T_5, 1)
node r_pte_idxs_0_1 = shr(pte.ppn, 27)
wire r_pte_lsbs_1 : UInt<2>
connect r_pte_lsbs_1, r_pte_idxs_0_1
wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_2, r_pte
node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1)
connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3
node _r_pte_T_8 = eq(traverse, UInt<1>(0h0))
node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1)
node _r_pte_T_10 = and(_r_pte_T_9, stage2)
node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte)
node _r_pte_T_12 = eq(state, UInt<3>(0h7))
node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0))
node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13)
node _r_pte_T_15 = neq(count, UInt<2>(0h2))
node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15)
node _r_pte_T_17 = shr(r_pte.ppn, 18)
node _r_pte_T_18 = bits(r_req.addr, 17, 0)
node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18)
node _r_pte_T_20 = shr(r_pte.ppn, 9)
node _r_pte_T_21 = bits(r_req.addr, 8, 0)
node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21)
node _r_pte_truncIdx_T = or(count, UInt<1>(0h0))
node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0)
node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1))
node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19)
wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_3, r_pte
connect r_pte_pte_3.ppn, _r_pte_T_24
node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid)
node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1)
node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0))
node r_pte_count_2 = tail(_r_pte_count_T_8, 1)
node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27)
wire r_pte_lsbs_2 : UInt<2>
connect r_pte_lsbs_2, r_pte_idxs_0_2
wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_4, r_pte
node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2)
node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2)
connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5
wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_5, r_pte
connect r_pte_pte_5.ppn, satp.ppn
node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5)
node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte)
node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27)
node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28)
node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29)
node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30)
node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31)
node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32)
inst r_pte_barrier of OptimizationBarrier_PTE_6
connect r_pte_barrier.clock, clock
connect r_pte_barrier.reset, reset
connect r_pte_barrier.io.x.v, _r_pte_T_33.v
connect r_pte_barrier.io.x.r, _r_pte_T_33.r
connect r_pte_barrier.io.x.w, _r_pte_T_33.w
connect r_pte_barrier.io.x.x, _r_pte_T_33.x
connect r_pte_barrier.io.x.u, _r_pte_T_33.u
connect r_pte_barrier.io.x.g, _r_pte_T_33.g
connect r_pte_barrier.io.x.a, _r_pte_T_33.a
connect r_pte_barrier.io.x.d, _r_pte_T_33.d
connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software
connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn
connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future
connect r_pte, r_pte_barrier.io.y
node _T_148 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_149 = and(UInt<1>(0h0), _T_148)
node _T_150 = eq(resp_gf, UInt<1>(0h0))
node _T_151 = and(_T_149, _T_150)
when _T_151 :
node _T_152 = eq(state, UInt<3>(0h1))
node _T_153 = eq(state, UInt<3>(0h2))
node _T_154 = or(_T_152, _T_153)
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_T_154, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2
assert(clock, _T_154, UInt<1>(0h1), "") : assert_2
connect next_state, UInt<3>(0h0)
node _T_158 = or(r_req_dest, UInt<1>(0h0))
node _T_159 = bits(_T_158, 0, 0)
connect resp_valid[_T_159], UInt<1>(0h1)
connect count, UInt<2>(0h2)
when mem_resp_valid :
node _T_160 = eq(state, UInt<3>(0h5))
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3
assert(clock, _T_160, UInt<1>(0h1), "") : assert_3
connect next_state, UInt<3>(0h1)
when traverse :
node _T_164 = eq(stage2, UInt<1>(0h0))
node _T_165 = and(do_both_stages, _T_164)
when _T_165 :
connect do_switch, UInt<1>(0h1)
node _count_T_6 = add(count, UInt<1>(0h1))
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
else :
node _gf_T = eq(stage2_final, UInt<1>(0h0))
node _gf_T_1 = and(stage2, _gf_T)
node _gf_T_2 = eq(pte.w, UInt<1>(0h0))
node _gf_T_3 = and(pte.x, _gf_T_2)
node _gf_T_4 = or(pte.r, _gf_T_3)
node _gf_T_5 = and(pte.v, _gf_T_4)
node _gf_T_6 = and(_gf_T_5, pte.a)
node _gf_T_7 = and(_gf_T_6, pte.r)
node _gf_T_8 = and(_gf_T_7, pte.u)
node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0))
node _gf_T_10 = and(_gf_T_1, _gf_T_9)
node _gf_T_11 = eq(pte.w, UInt<1>(0h0))
node _gf_T_12 = and(pte.x, _gf_T_11)
node _gf_T_13 = or(pte.r, _gf_T_12)
node _gf_T_14 = and(pte.v, _gf_T_13)
node _gf_T_15 = and(_gf_T_14, pte.a)
node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _gf_T_17 = and(_gf_T_15, _gf_T_16)
node _gf_T_18 = and(_gf_T_17, invalid_gpa)
node gf = or(_gf_T_10, _gf_T_18)
node ae = and(pte.v, invalid_paddr)
node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0))
node pf = and(pte.v, _pf_T)
node _success_T = eq(ae, UInt<1>(0h0))
node _success_T_1 = and(pte.v, _success_T)
node _success_T_2 = eq(pf, UInt<1>(0h0))
node _success_T_3 = and(_success_T_1, _success_T_2)
node _success_T_4 = eq(gf, UInt<1>(0h0))
node success = and(_success_T_3, _success_T_4)
node _T_166 = eq(stage2_final, UInt<1>(0h0))
node _T_167 = and(do_both_stages, _T_166)
node _T_168 = and(_T_167, success)
when _T_168 :
when stage2 :
connect stage2, UInt<1>(0h0)
connect count, aux_count
else :
connect stage2_final, UInt<1>(0h1)
connect do_switch, UInt<1>(0h1)
else :
node _l2_refill_T = eq(count, UInt<2>(0h2))
node _l2_refill_T_1 = and(success, _l2_refill_T)
node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0))
node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2)
node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0))
node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0))
node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5)
node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2))
node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7)
node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9)
node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10)
node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11)
node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a)
node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w)
node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d)
node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u)
node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17)
node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18)
node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19)
node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a)
node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x)
node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u)
node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23)
node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24)
node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25)
node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26)
connect l2_refill, _l2_refill_T_27
connect count, max_count
node _T_169 = eq(count, UInt<2>(0h2))
node _T_170 = eq(do_both_stages, UInt<1>(0h0))
node _T_171 = eq(aux_count, UInt<2>(0h2))
node _T_172 = or(_T_170, _T_171)
node _T_173 = and(_T_169, _T_172)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = and(UInt<1>(0h0), _T_174)
when _T_175 :
connect next_state, UInt<3>(0h7)
else :
connect next_state, UInt<3>(0h0)
node _T_176 = or(r_req_dest, UInt<1>(0h0))
node _T_177 = bits(_T_176, 0, 0)
connect resp_valid[_T_177], UInt<1>(0h1)
node _resp_ae_ptw_T = lt(count, UInt<2>(0h2))
node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T)
node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0))
node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2)
node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4)
node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0))
node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6)
node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0))
node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8)
node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0))
node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10)
node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0))
node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12)
node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14)
node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15)
connect resp_ae_ptw, _resp_ae_ptw_T_16
node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0))
node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T)
node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1)
node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2)
node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a)
node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4)
connect resp_ae_final, _resp_ae_final_T_5
node _resp_pf_T = eq(stage2, UInt<1>(0h0))
node _resp_pf_T_1 = and(pf, _resp_pf_T)
connect resp_pf, _resp_pf_T_1
node _resp_gf_T_3 = and(pf, stage2)
node _resp_gf_T_4 = or(gf, _resp_gf_T_3)
connect resp_gf, _resp_gf_T_4
node _resp_hr_T = eq(stage2, UInt<1>(0h0))
node _resp_hr_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hr_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2)
node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4)
node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5)
node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6)
node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a)
node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r)
node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u)
node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10)
node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11)
connect resp_hr, _resp_hr_T_12
node _resp_hw_T = eq(stage2, UInt<1>(0h0))
node _resp_hw_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hw_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2)
node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4)
node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5)
node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6)
node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a)
node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w)
node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d)
node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u)
node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11)
node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12)
connect resp_hw, _resp_hw_T_13
node _resp_hx_T = eq(stage2, UInt<1>(0h0))
node _resp_hx_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hx_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2)
node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4)
node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5)
node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6)
node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a)
node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x)
node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u)
node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10)
node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11)
connect resp_hx, _resp_hx_T_12
when io.mem.s2_nack :
node _T_178 = eq(state, UInt<3>(0h4))
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4
assert(clock, _T_178, UInt<1>(0h1), "") : assert_4
connect next_state, UInt<3>(0h1)
when do_switch :
node _aux_count_T_3 = add(count, UInt<1>(0h1))
node _aux_count_T_4 = tail(_aux_count_T_3, 1)
node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count)
connect aux_count, _aux_count_T_5
connect count, r_hgatp_initial_count
node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18)
node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0)
node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1)
node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0)
node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3)
node _aux_pte_T = eq(count, UInt<1>(0h1))
node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0)
node _aux_pte_T_2 = eq(count, UInt<2>(0h2))
node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1)
node _aux_pte_T_4 = eq(count, UInt<2>(0h3))
node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3)
wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect aux_pte_pte, pte
connect aux_pte_pte.ppn, _aux_pte_T_5
node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte)
connect aux_pte, _aux_pte_T_6
connect stage2, UInt<1>(0h1)
node _leaf_T = eq(traverse, UInt<1>(0h0))
node _leaf_T_1 = and(mem_resp_valid, _leaf_T)
node _leaf_T_2 = eq(count, UInt<1>(0h0))
node leaf = and(_leaf_T_1, _leaf_T_2)
node _T_182 = and(leaf, pte.v)
node _T_183 = eq(invalid_paddr, UInt<1>(0h0))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(invalid_gpa, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = and(leaf, pte.v)
node _T_190 = and(_T_189, invalid_paddr)
node _T_191 = and(leaf, pte.v)
node _T_192 = and(_T_191, invalid_gpa)
node _T_193 = and(leaf, pte.v)
node _T_194 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = bits(mem_resp_data, 0, 0)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = and(leaf, _T_197)
node _T_199 = eq(pte.v, UInt<1>(0h0))
node _T_200 = and(leaf, _T_199)
node _T_201 = bits(mem_resp_data, 0, 0)
node _T_202 = and(_T_200, _T_201)
node _leaf_T_3 = eq(traverse, UInt<1>(0h0))
node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3)
node _leaf_T_5 = eq(count, UInt<1>(0h1))
node leaf_1 = and(_leaf_T_4, _leaf_T_5)
node _T_203 = and(leaf_1, pte.v)
node _T_204 = eq(invalid_paddr, UInt<1>(0h0))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(invalid_gpa, UInt<1>(0h0))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_209 = and(_T_207, _T_208)
node _T_210 = and(leaf_1, pte.v)
node _T_211 = and(_T_210, invalid_paddr)
node _T_212 = and(leaf_1, pte.v)
node _T_213 = and(_T_212, invalid_gpa)
node _T_214 = and(leaf_1, pte.v)
node _T_215 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_216 = and(_T_214, _T_215)
node _T_217 = bits(mem_resp_data, 0, 0)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = and(leaf_1, _T_218)
node _T_220 = eq(pte.v, UInt<1>(0h0))
node _T_221 = and(leaf_1, _T_220)
node _T_222 = bits(mem_resp_data, 0, 0)
node _T_223 = and(_T_221, _T_222)
node _leaf_T_6 = eq(traverse, UInt<1>(0h0))
node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6)
node _leaf_T_8 = eq(count, UInt<2>(0h2))
node leaf_2 = and(_leaf_T_7, _leaf_T_8)
node _T_224 = and(leaf_2, pte.v)
node _T_225 = eq(invalid_paddr, UInt<1>(0h0))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(invalid_gpa, UInt<1>(0h0))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_230 = and(_T_228, _T_229)
node _T_231 = and(leaf_2, pte.v)
node _T_232 = and(_T_231, invalid_paddr)
node _T_233 = and(leaf_2, pte.v)
node _T_234 = and(_T_233, invalid_gpa)
node _T_235 = and(leaf_2, pte.v)
node _T_236 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_237 = and(_T_235, _T_236)
node _T_238 = bits(mem_resp_data, 0, 0)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = and(leaf_2, _T_239)
node _T_241 = eq(count, UInt<2>(0h2))
node _T_242 = and(mem_resp_valid, _T_241)
node _T_243 = eq(pte.r, UInt<1>(0h0))
node _T_244 = and(pte.v, _T_243)
node _T_245 = eq(pte.w, UInt<1>(0h0))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(pte.x, UInt<1>(0h0))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(pte.d, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(pte.a, UInt<1>(0h0))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(pte.u, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_256 = and(_T_254, _T_255)
node _T_257 = and(_T_242, _T_256)
node _T_258 = eq(state, UInt<3>(0h4))
node _T_259 = and(_T_258, io.mem.s2_xcpt.ae.ld) | module PTW_6( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input io_requestor_0_req_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_sd, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output io_requestor_0_status_tsr, // @[PTW.scala:220:14]
output io_requestor_0_status_tw, // @[PTW.scala:220:14]
output io_requestor_0_status_tvm, // @[PTW.scala:220:14]
output io_requestor_0_status_mxr, // @[PTW.scala:220:14]
output io_requestor_0_status_sum, // @[PTW.scala:220:14]
output io_requestor_0_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output io_requestor_0_status_spp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_spie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_status_sie, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_requestor_1_req_ready, // @[PTW.scala:220:14]
input io_requestor_1_req_valid, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_1_resp_valid, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_1_status_debug, // @[PTW.scala:220:14]
output io_requestor_1_status_cease, // @[PTW.scala:220:14]
output io_requestor_1_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14]
output io_requestor_1_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14]
output io_requestor_1_status_v, // @[PTW.scala:220:14]
output io_requestor_1_status_sd, // @[PTW.scala:220:14]
output io_requestor_1_status_mpv, // @[PTW.scala:220:14]
output io_requestor_1_status_gva, // @[PTW.scala:220:14]
output io_requestor_1_status_tsr, // @[PTW.scala:220:14]
output io_requestor_1_status_tw, // @[PTW.scala:220:14]
output io_requestor_1_status_tvm, // @[PTW.scala:220:14]
output io_requestor_1_status_mxr, // @[PTW.scala:220:14]
output io_requestor_1_status_sum, // @[PTW.scala:220:14]
output io_requestor_1_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14]
output io_requestor_1_status_spp, // @[PTW.scala:220:14]
output io_requestor_1_status_mpie, // @[PTW.scala:220:14]
output io_requestor_1_status_spie, // @[PTW.scala:220:14]
output io_requestor_1_status_mie, // @[PTW.scala:220:14]
output io_requestor_1_status_sie, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
input io_mem_req_ready, // @[PTW.scala:220:14]
output io_mem_req_valid, // @[PTW.scala:220:14]
output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14]
output io_mem_req_bits_dv, // @[PTW.scala:220:14]
output io_mem_s1_kill, // @[PTW.scala:220:14]
input io_mem_s2_nack, // @[PTW.scala:220:14]
input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14]
input io_mem_s2_uncached, // @[PTW.scala:220:14]
input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14]
input io_mem_resp_valid, // @[PTW.scala:220:14]
input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14]
input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14]
input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14]
input io_mem_resp_bits_signed, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14]
input io_mem_resp_bits_dv, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14]
input io_mem_resp_bits_replay, // @[PTW.scala:220:14]
input io_mem_resp_bits_has_data, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14]
input io_mem_replay_next, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14]
input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14]
input io_mem_ordered, // @[PTW.scala:220:14]
input io_mem_store_pending, // @[PTW.scala:220:14]
input io_mem_perf_acquire, // @[PTW.scala:220:14]
input io_mem_perf_release, // @[PTW.scala:220:14]
input io_mem_perf_grant, // @[PTW.scala:220:14]
input io_mem_perf_tlbMiss, // @[PTW.scala:220:14]
input io_mem_perf_blocked, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14]
input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14]
input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14]
input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_sd, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input io_dpath_status_tsr, // @[PTW.scala:220:14]
input io_dpath_status_tw, // @[PTW.scala:220:14]
input io_dpath_status_tvm, // @[PTW.scala:220:14]
input io_dpath_status_mxr, // @[PTW.scala:220:14]
input io_dpath_status_sum, // @[PTW.scala:220:14]
input io_dpath_status_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input io_dpath_status_spp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_spie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_status_sie, // @[PTW.scala:220:14]
input io_dpath_hstatus_spvp, // @[PTW.scala:220:14]
input io_dpath_hstatus_spv, // @[PTW.scala:220:14]
input io_dpath_hstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_debug, // @[PTW.scala:220:14]
input io_dpath_gstatus_cease, // @[PTW.scala:220:14]
input io_dpath_gstatus_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14]
input io_dpath_gstatus_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14]
input io_dpath_gstatus_v, // @[PTW.scala:220:14]
input io_dpath_gstatus_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpv, // @[PTW.scala:220:14]
input io_dpath_gstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_mbe, // @[PTW.scala:220:14]
input io_dpath_gstatus_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14]
input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14]
input io_dpath_gstatus_tsr, // @[PTW.scala:220:14]
input io_dpath_gstatus_tw, // @[PTW.scala:220:14]
input io_dpath_gstatus_tvm, // @[PTW.scala:220:14]
input io_dpath_gstatus_mxr, // @[PTW.scala:220:14]
input io_dpath_gstatus_sum, // @[PTW.scala:220:14]
input io_dpath_gstatus_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14]
input io_dpath_gstatus_spp, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpie, // @[PTW.scala:220:14]
input io_dpath_gstatus_ube, // @[PTW.scala:220:14]
input io_dpath_gstatus_spie, // @[PTW.scala:220:14]
input io_dpath_gstatus_upie, // @[PTW.scala:220:14]
input io_dpath_gstatus_mie, // @[PTW.scala:220:14]
input io_dpath_gstatus_hie, // @[PTW.scala:220:14]
input io_dpath_gstatus_sie, // @[PTW.scala:220:14]
input io_dpath_gstatus_uie, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_perf_pte_hit, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_dpath_clock_enabled // @[PTW.scala:220:14]
);
wire tmp_r; // @[PTW.scala:304:37]
wire tmp_w; // @[PTW.scala:304:37]
wire tmp_x; // @[PTW.scala:304:37]
wire tmp_u; // @[PTW.scala:304:37]
wire tmp_g; // @[PTW.scala:304:37]
wire tmp_a; // @[PTW.scala:304:37]
wire tmp_d; // @[PTW.scala:304:37]
wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37]
wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37]
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_valid; // @[PTW.scala:236:19]
wire _arb_io_out_bits_valid; // @[PTW.scala:236:19]
wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19]
wire _arb_io_chosen; // @[PTW.scala:236:19]
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7]
wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7]
wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7]
wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7]
wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7]
wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7]
wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7]
wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7]
wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7]
wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35]
wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27]
wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20]
wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24]
wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32]
wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17]
wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18]
wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19]
wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27]
wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43]
wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13]
wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7]
wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33]
wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16]
wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28]
wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30]
wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58]
wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18]
wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23]
wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15]
wire [1:0] max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17]
wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57]
wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7]
wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7]
wire io_mem_req_valid_0; // @[PTW.scala:219:7]
wire io_mem_s1_kill_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
reg resp_valid_1; // @[PTW.scala:242:27]
assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61]
wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61]
assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39]
assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39]
reg invalidated; // @[PTW.scala:251:24]
reg [1:0] count; // @[PTW.scala:259:18]
wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [26:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
reg r_req_stage2; // @[PTW.scala:270:18]
reg r_req_dest; // @[PTW.scala:272:23]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20]
reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20]
reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20]
reg [1:0] aux_count; // @[PTW.scala:278:22]
wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12]
reg mem_resp_valid; // @[PTW.scala:292:31]
reg [63:0] mem_resp_data; // @[PTW.scala:293:30]
wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37]
wire [9:0] _tmp_T_10; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26]
wire [1:0] _tmp_T_8; // @[PTW.scala:304:37]
wire _tmp_T_7; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_6; // @[PTW.scala:304:37]
wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_5; // @[PTW.scala:304:37]
wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_4; // @[PTW.scala:304:37]
wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_3; // @[PTW.scala:304:37]
wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_2; // @[PTW.scala:304:37]
wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_1; // @[PTW.scala:304:37]
wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26]
wire _tmp_T; // @[PTW.scala:304:37]
wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26]
wire [43:0] tmp_ppn; // @[PTW.scala:304:37]
wire tmp_v; // @[PTW.scala:304:37]
assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37]
assign tmp_v = _tmp_T; // @[PTW.scala:304:37]
assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37]
assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37]
assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37]
assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37]
assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37]
assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37]
assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37]
assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37]
assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37]
assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37]
assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37]
assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37]
assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37]
assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37]
assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37]
assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37]
assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37]
assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37]
assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37]
assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37]
wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26]
wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26]
wire [43:0] pte_ppn; // @[PTW.scala:305:26]
wire pte_v; // @[PTW.scala:305:26]
wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54]
wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99]
wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}]
assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}]
assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}]
wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}]
wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58]
wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25]
wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26]
wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}]
wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}]
wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}]
wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}]
wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}]
wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}]
wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33]
wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}]
wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51]
wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}]
wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73]
wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}]
wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}]
wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}]
wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}]
wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40]
wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}]
wire _T_46 = count == 2'h1; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86]
wire _pmaHomogeneous_T; // @[package.scala:39:86]
assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_23; // @[package.scala:39:86]
assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_60; // @[package.scala:39:86]
assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_97; // @[package.scala:39:86]
assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_134; // @[package.scala:39:86]
assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_171; // @[package.scala:39:86]
assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_208; // @[package.scala:39:86]
assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_245; // @[package.scala:39:86]
assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_282; // @[package.scala:39:86]
assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86]
wire _aux_pte_T; // @[package.scala:39:86]
assign _aux_pte_T = _T_46; // @[package.scala:39:86]
wire _leaf_T_5; // @[PTW.scala:751:53]
assign _leaf_T_5 = _T_46; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}]
wire _T_241 = count == 2'h2; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T_2 = _T_241; // @[package.scala:39:86]
wire _pmaHomogeneous_T_2; // @[package.scala:39:86]
assign _pmaHomogeneous_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_T_25 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_62; // @[package.scala:39:86]
assign _pmpHomogeneous_T_62 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_7 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_99; // @[package.scala:39:86]
assign _pmpHomogeneous_T_99 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_12 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_136; // @[package.scala:39:86]
assign _pmpHomogeneous_T_136 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_17 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_173; // @[package.scala:39:86]
assign _pmpHomogeneous_T_173 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_22 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_210; // @[package.scala:39:86]
assign _pmpHomogeneous_T_210 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_27 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_247; // @[package.scala:39:86]
assign _pmpHomogeneous_T_247 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_32 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_284; // @[package.scala:39:86]
assign _pmpHomogeneous_T_284 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_37 = _T_241; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T_2 = _T_241; // @[package.scala:39:86]
wire _l2_refill_T; // @[PTW.scala:713:39]
assign _l2_refill_T = _T_241; // @[package.scala:39:86]
wire _aux_pte_T_2; // @[package.scala:39:86]
assign _aux_pte_T_2 = _T_241; // @[package.scala:39:86]
wire _leaf_T_8; // @[PTW.scala:751:53]
assign _leaf_T_8 = _T_241; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}]
wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}]
wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76]
wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36]
wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}]
wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}]
wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23]
reg [6:0] state_reg; // @[Replacement.scala:168:70]
reg [7:0] valid; // @[PTW.scala:352:24]
reg [31:0] tags_0; // @[PTW.scala:353:19]
reg [31:0] tags_1; // @[PTW.scala:353:19]
reg [31:0] tags_2; // @[PTW.scala:353:19]
reg [31:0] tags_3; // @[PTW.scala:353:19]
reg [31:0] tags_4; // @[PTW.scala:353:19]
reg [31:0] tags_5; // @[PTW.scala:353:19]
reg [31:0] tags_6; // @[PTW.scala:353:19]
reg [31:0] tags_7; // @[PTW.scala:353:19]
reg [19:0] data_0; // @[PTW.scala:355:19]
reg [19:0] data_1; // @[PTW.scala:355:19]
reg [19:0] data_2; // @[PTW.scala:355:19]
reg [19:0] data_3; // @[PTW.scala:355:19]
reg [19:0] data_4; // @[PTW.scala:355:19]
reg [19:0] data_5; // @[PTW.scala:355:19]
reg [19:0] data_6; // @[PTW.scala:355:19]
reg [19:0] data_7; // @[PTW.scala:355:19]
wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18]
wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65]
wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}]
wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}]
wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15]
wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27]
wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27]
wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27]
wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27]
wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27]
wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27]
wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27]
wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20]
wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}]
wire _r_T = &valid; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13]
wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13]
wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13]
wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57]
wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45]
wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45]
wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45]
wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45]
wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45]
wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45]
wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45]
wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45]
wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13]
wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire _T_152 = state == 3'h1; // @[PTW.scala:233:22, :377:24]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_152; // @[PTW.scala:377:24, :394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_152; // @[PTW.scala:377:24, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_152; // @[PTW.scala:377:24, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_152; // @[PTW.scala:377:24, :674:15]
wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18]
wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18]
wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13]
wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13]
wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13]
wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13]
wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16]
wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53]
wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36]
reg [6:0] state_reg_1; // @[Replacement.scala:168:70]
reg [7:0] valid_1; // @[PTW.scala:352:24]
reg [19:0] data_1_0; // @[PTW.scala:355:19]
reg [19:0] data_1_1; // @[PTW.scala:355:19]
reg [19:0] data_1_2; // @[PTW.scala:355:19]
reg [19:0] data_1_3; // @[PTW.scala:355:19]
reg [19:0] data_1_4; // @[PTW.scala:355:19]
reg [19:0] data_1_5; // @[PTW.scala:355:19]
reg [19:0] data_1_6; // @[PTW.scala:355:19]
reg [19:0] data_1_7; // @[PTW.scala:355:19]
wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21]
wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60]
wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}]
wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}]
wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}]
wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107]
wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}]
wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33]
wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}]
wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44]
wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}]
wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13]
wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13]
wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12]
wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13]
wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38]
wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12]
wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57]
wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45]
wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45]
wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45]
wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45]
wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45]
wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45]
wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45]
wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45]
wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45]
wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45]
wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45]
wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45]
wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45]
wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13]
wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13]
wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13]
wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13]
wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13]
wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13]
wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13]
wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13]
wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13]
wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12]
wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13]
wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38]
wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12]
wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16]
wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16]
wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16]
reg pte_hit; // @[PTW.scala:392:24]
wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}]
assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}]
assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_7 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_37 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}]
wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_43 = _GEN_0; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_110 = _GEN_0; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_48 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_98 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_115 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_147 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_154 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_68 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_120 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_135 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_83 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_125 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_140 = _GEN_3; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}]
wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86]
wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_4 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_2 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_9 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_16 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76]
wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}]
wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21]
wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_5 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T = _GEN_5; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_5; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62]
wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_6 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_39 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_46 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_53 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76]
wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_7; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_7; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_8 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_76 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_83 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_90 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76]
wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_9; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_9; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_10 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_113 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_120 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_127 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76]
wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_11; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_11; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_12 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_150 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_157 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_164 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76]
wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_13; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_13; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_14 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_187 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_194 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_201 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76]
wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_15; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_15; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_16 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_224 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_231 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_238 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76]
wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_17; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_17; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_18 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_261 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_268 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_275 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76]
wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_19; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_19; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10]
wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _T_171 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _gpa_pgoff_T; // @[PTW.scala:615:36]
assign _gpa_pgoff_T = _T_171; // @[PTW.scala:566:60, :615:36]
wire _l2_refill_T_7; // @[PTW.scala:715:40]
assign _l2_refill_T_7 = _T_171; // @[PTW.scala:566:60, :715:40]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire do_switch; // @[PTW.scala:581:30]
wire _T_129 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire _GEN_20 = ~(|state) & _T_129; // @[Decoupled.scala:51:35]
wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26]
wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58]
wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40]
wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40]
wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67]
wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}]
wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32]
wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32]
wire [2:0] _GEN_21 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24]
wire [2:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_21; // @[PTW.scala:624:24]
wire [2:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_21; // @[PTW.scala:624:24, :696:22]
wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_21; // @[PTW.scala:624:24, :741:38]
wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24]
wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26]
wire _T_140 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_141 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39]
wire _GEN_22 = _T_152 | _T_140; // @[PTW.scala:377:24, :393:26, :583:18]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_22) & _T_141 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}]
wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}]
wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64]
wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}]
wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64]
wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}]
wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}]
wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26]
wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}]
assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}]
wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26]
assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73]
wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58]
wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27]
assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27]
wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}]
assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29]
wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}]
wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76]
wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26]
wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8]
wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26]
wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_d = ~_r_pte_T_7 & _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_a = ~_r_pte_T_7 & _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_g = ~_r_pte_T_7 & _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_u = ~_r_pte_T_7 & _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_x = ~_r_pte_T_7 & _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_w = ~_r_pte_T_7 & _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_r = ~_r_pte_T_7 & _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_v = ~_r_pte_T_7 & _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8]
wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44]
wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}]
wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97]
wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}]
wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}]
wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}]
wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22]
wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49]
wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}]
wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30]
wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}]
wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37]
wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}]
wire _T_168 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}]
assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_168 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21]
wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41]
wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}]
wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59]
wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44]
wire _GEN_23 = traverse | _T_168; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19]
wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36]
wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}]
wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26]
wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}]
wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}]
wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}]
wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}]
wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}]
wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}]
wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}]
wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}]
wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30]
wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}]
wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}]
wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}]
wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}]
wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}]
wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}]
wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_120 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_120( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LatencyInjectionQueue_11 :
input clock : Clock
input reset : Reset
output io : { flip latency_cycles : UInt<64>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0)
node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1))
node _cur_cycle_T_1 = tail(_cur_cycle_T, 1)
connect cur_cycle, _cur_cycle_T_1
inst queue of Queue64_TLBundleD_a32d256s5k3z4u_3
connect queue.clock, clock
connect queue.reset, reset
inst release_ready_cycle_q of Queue64_UInt64_7
connect release_ready_cycle_q.clock, clock
connect release_ready_cycle_q.reset, reset
node _release_ready_cycle_q_io_enq_bits_T = add(cur_cycle, io.latency_cycles)
node _release_ready_cycle_q_io_enq_bits_T_1 = tail(_release_ready_cycle_q_io_enq_bits_T, 1)
connect release_ready_cycle_q.io.enq.bits, _release_ready_cycle_q_io_enq_bits_T_1
connect queue.io.enq.bits.corrupt, io.enq.bits.corrupt
connect queue.io.enq.bits.data, io.enq.bits.data
connect queue.io.enq.bits.denied, io.enq.bits.denied
connect queue.io.enq.bits.sink, io.enq.bits.sink
connect queue.io.enq.bits.source, io.enq.bits.source
connect queue.io.enq.bits.size, io.enq.bits.size
connect queue.io.enq.bits.param, io.enq.bits.param
connect queue.io.enq.bits.opcode, io.enq.bits.opcode
connect io.deq.bits, queue.io.deq.bits
node _queue_io_enq_valid_T = and(release_ready_cycle_q.io.enq.ready, io.enq.valid)
connect queue.io.enq.valid, _queue_io_enq_valid_T
node _release_ready_cycle_q_io_enq_valid_T = and(queue.io.enq.ready, io.enq.valid)
connect release_ready_cycle_q.io.enq.valid, _release_ready_cycle_q_io_enq_valid_T
node _io_enq_ready_T = and(queue.io.enq.ready, release_ready_cycle_q.io.enq.ready)
connect io.enq.ready, _io_enq_ready_T
node _T = leq(release_ready_cycle_q.io.deq.bits, cur_cycle)
node _queue_io_deq_ready_T = and(release_ready_cycle_q.io.deq.valid, _T)
node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, io.deq.ready)
connect queue.io.deq.ready, _queue_io_deq_ready_T_1
node _release_ready_cycle_q_io_deq_ready_T = and(queue.io.deq.valid, _T)
node _release_ready_cycle_q_io_deq_ready_T_1 = and(_release_ready_cycle_q_io_deq_ready_T, io.deq.ready)
connect release_ready_cycle_q.io.deq.ready, _release_ready_cycle_q_io_deq_ready_T_1
node _io_deq_valid_T = and(queue.io.deq.valid, release_ready_cycle_q.io.deq.valid)
node _io_deq_valid_T_1 = and(_io_deq_valid_T, _T)
connect io.deq.valid, _io_deq_valid_T_1 | module LatencyInjectionQueue_11( // @[LatencyInjectionQueue.scala:9:7]
input clock, // @[LatencyInjectionQueue.scala:9:7]
input reset, // @[LatencyInjectionQueue.scala:9:7]
input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14]
output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14]
input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14]
input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14]
input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14]
output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14]
);
wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37]
wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37]
wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37]
wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21]
wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21]
wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7]
wire _io_enq_ready_T; // @[Misc.scala:26:53]
wire _io_deq_valid_T_1; // @[Misc.scala:26:53]
wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26]
wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26]
wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26]
wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50]
wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50]
wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53]
wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39]
wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53]
always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7]
if (reset) // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26]
else // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26]
always @(posedge)
Queue64_TLBundleD_a32d256s5k3z4u_3 queue ( // @[LatencyInjectionQueue.scala:18:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7]
.io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_deq_bits_opcode),
.io_deq_bits_param (io_deq_bits_param),
.io_deq_bits_size (io_deq_bits_size),
.io_deq_bits_source (io_deq_bits_source_0),
.io_deq_bits_sink (io_deq_bits_sink),
.io_deq_bits_denied (io_deq_bits_denied),
.io_deq_bits_data (io_deq_bits_data_0),
.io_deq_bits_corrupt (io_deq_bits_corrupt)
); // @[LatencyInjectionQueue.scala:18:21]
Queue64_UInt64_7 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37]
.clock (clock),
.reset (reset),
.io_enq_ready (_release_ready_cycle_q_io_enq_ready),
.io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50]
.io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_release_ready_cycle_q_io_deq_valid),
.io_deq_bits (_release_ready_cycle_q_io_deq_bits)
); // @[LatencyInjectionQueue.scala:19:37]
assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TwoPortSyncMem_1 :
input clock : Clock
input reset : Reset
output io : { flip waddr : UInt<9>, flip raddr : UInt<9>, flip wdata : SInt<32>[1][16], rdata : SInt<32>[1][16], flip wen : UInt<1>, flip ren : UInt<1>, flip mask : UInt<1>[64]}
node _T = and(io.wen, io.ren)
node _T_1 = eq(io.raddr, io.waddr)
node _T_2 = and(_T, _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed: undefined behavior in dual-ported SRAM\n at SyncMem.scala:41 assert(!(io.wen && io.ren && io.raddr === io.waddr), \"undefined behavior in dual-ported SRAM\")\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
smem mem : UInt<8>[64] [512]
wire _io_rdata_WIRE : UInt<9>
invalidate _io_rdata_WIRE
when io.ren :
connect _io_rdata_WIRE, io.raddr
read mport io_rdata_MPORT = mem[_io_rdata_WIRE], clock
wire _io_rdata_WIRE_1 : SInt<32>[1][16]
node io_rdata_lo_lo_lo_lo_lo = cat(io_rdata_MPORT[1], io_rdata_MPORT[0])
node io_rdata_lo_lo_lo_lo_hi = cat(io_rdata_MPORT[3], io_rdata_MPORT[2])
node io_rdata_lo_lo_lo_lo = cat(io_rdata_lo_lo_lo_lo_hi, io_rdata_lo_lo_lo_lo_lo)
node io_rdata_lo_lo_lo_hi_lo = cat(io_rdata_MPORT[5], io_rdata_MPORT[4])
node io_rdata_lo_lo_lo_hi_hi = cat(io_rdata_MPORT[7], io_rdata_MPORT[6])
node io_rdata_lo_lo_lo_hi = cat(io_rdata_lo_lo_lo_hi_hi, io_rdata_lo_lo_lo_hi_lo)
node io_rdata_lo_lo_lo = cat(io_rdata_lo_lo_lo_hi, io_rdata_lo_lo_lo_lo)
node io_rdata_lo_lo_hi_lo_lo = cat(io_rdata_MPORT[9], io_rdata_MPORT[8])
node io_rdata_lo_lo_hi_lo_hi = cat(io_rdata_MPORT[11], io_rdata_MPORT[10])
node io_rdata_lo_lo_hi_lo = cat(io_rdata_lo_lo_hi_lo_hi, io_rdata_lo_lo_hi_lo_lo)
node io_rdata_lo_lo_hi_hi_lo = cat(io_rdata_MPORT[13], io_rdata_MPORT[12])
node io_rdata_lo_lo_hi_hi_hi = cat(io_rdata_MPORT[15], io_rdata_MPORT[14])
node io_rdata_lo_lo_hi_hi = cat(io_rdata_lo_lo_hi_hi_hi, io_rdata_lo_lo_hi_hi_lo)
node io_rdata_lo_lo_hi = cat(io_rdata_lo_lo_hi_hi, io_rdata_lo_lo_hi_lo)
node io_rdata_lo_lo = cat(io_rdata_lo_lo_hi, io_rdata_lo_lo_lo)
node io_rdata_lo_hi_lo_lo_lo = cat(io_rdata_MPORT[17], io_rdata_MPORT[16])
node io_rdata_lo_hi_lo_lo_hi = cat(io_rdata_MPORT[19], io_rdata_MPORT[18])
node io_rdata_lo_hi_lo_lo = cat(io_rdata_lo_hi_lo_lo_hi, io_rdata_lo_hi_lo_lo_lo)
node io_rdata_lo_hi_lo_hi_lo = cat(io_rdata_MPORT[21], io_rdata_MPORT[20])
node io_rdata_lo_hi_lo_hi_hi = cat(io_rdata_MPORT[23], io_rdata_MPORT[22])
node io_rdata_lo_hi_lo_hi = cat(io_rdata_lo_hi_lo_hi_hi, io_rdata_lo_hi_lo_hi_lo)
node io_rdata_lo_hi_lo = cat(io_rdata_lo_hi_lo_hi, io_rdata_lo_hi_lo_lo)
node io_rdata_lo_hi_hi_lo_lo = cat(io_rdata_MPORT[25], io_rdata_MPORT[24])
node io_rdata_lo_hi_hi_lo_hi = cat(io_rdata_MPORT[27], io_rdata_MPORT[26])
node io_rdata_lo_hi_hi_lo = cat(io_rdata_lo_hi_hi_lo_hi, io_rdata_lo_hi_hi_lo_lo)
node io_rdata_lo_hi_hi_hi_lo = cat(io_rdata_MPORT[29], io_rdata_MPORT[28])
node io_rdata_lo_hi_hi_hi_hi = cat(io_rdata_MPORT[31], io_rdata_MPORT[30])
node io_rdata_lo_hi_hi_hi = cat(io_rdata_lo_hi_hi_hi_hi, io_rdata_lo_hi_hi_hi_lo)
node io_rdata_lo_hi_hi = cat(io_rdata_lo_hi_hi_hi, io_rdata_lo_hi_hi_lo)
node io_rdata_lo_hi = cat(io_rdata_lo_hi_hi, io_rdata_lo_hi_lo)
node io_rdata_lo = cat(io_rdata_lo_hi, io_rdata_lo_lo)
node io_rdata_hi_lo_lo_lo_lo = cat(io_rdata_MPORT[33], io_rdata_MPORT[32])
node io_rdata_hi_lo_lo_lo_hi = cat(io_rdata_MPORT[35], io_rdata_MPORT[34])
node io_rdata_hi_lo_lo_lo = cat(io_rdata_hi_lo_lo_lo_hi, io_rdata_hi_lo_lo_lo_lo)
node io_rdata_hi_lo_lo_hi_lo = cat(io_rdata_MPORT[37], io_rdata_MPORT[36])
node io_rdata_hi_lo_lo_hi_hi = cat(io_rdata_MPORT[39], io_rdata_MPORT[38])
node io_rdata_hi_lo_lo_hi = cat(io_rdata_hi_lo_lo_hi_hi, io_rdata_hi_lo_lo_hi_lo)
node io_rdata_hi_lo_lo = cat(io_rdata_hi_lo_lo_hi, io_rdata_hi_lo_lo_lo)
node io_rdata_hi_lo_hi_lo_lo = cat(io_rdata_MPORT[41], io_rdata_MPORT[40])
node io_rdata_hi_lo_hi_lo_hi = cat(io_rdata_MPORT[43], io_rdata_MPORT[42])
node io_rdata_hi_lo_hi_lo = cat(io_rdata_hi_lo_hi_lo_hi, io_rdata_hi_lo_hi_lo_lo)
node io_rdata_hi_lo_hi_hi_lo = cat(io_rdata_MPORT[45], io_rdata_MPORT[44])
node io_rdata_hi_lo_hi_hi_hi = cat(io_rdata_MPORT[47], io_rdata_MPORT[46])
node io_rdata_hi_lo_hi_hi = cat(io_rdata_hi_lo_hi_hi_hi, io_rdata_hi_lo_hi_hi_lo)
node io_rdata_hi_lo_hi = cat(io_rdata_hi_lo_hi_hi, io_rdata_hi_lo_hi_lo)
node io_rdata_hi_lo = cat(io_rdata_hi_lo_hi, io_rdata_hi_lo_lo)
node io_rdata_hi_hi_lo_lo_lo = cat(io_rdata_MPORT[49], io_rdata_MPORT[48])
node io_rdata_hi_hi_lo_lo_hi = cat(io_rdata_MPORT[51], io_rdata_MPORT[50])
node io_rdata_hi_hi_lo_lo = cat(io_rdata_hi_hi_lo_lo_hi, io_rdata_hi_hi_lo_lo_lo)
node io_rdata_hi_hi_lo_hi_lo = cat(io_rdata_MPORT[53], io_rdata_MPORT[52])
node io_rdata_hi_hi_lo_hi_hi = cat(io_rdata_MPORT[55], io_rdata_MPORT[54])
node io_rdata_hi_hi_lo_hi = cat(io_rdata_hi_hi_lo_hi_hi, io_rdata_hi_hi_lo_hi_lo)
node io_rdata_hi_hi_lo = cat(io_rdata_hi_hi_lo_hi, io_rdata_hi_hi_lo_lo)
node io_rdata_hi_hi_hi_lo_lo = cat(io_rdata_MPORT[57], io_rdata_MPORT[56])
node io_rdata_hi_hi_hi_lo_hi = cat(io_rdata_MPORT[59], io_rdata_MPORT[58])
node io_rdata_hi_hi_hi_lo = cat(io_rdata_hi_hi_hi_lo_hi, io_rdata_hi_hi_hi_lo_lo)
node io_rdata_hi_hi_hi_hi_lo = cat(io_rdata_MPORT[61], io_rdata_MPORT[60])
node io_rdata_hi_hi_hi_hi_hi = cat(io_rdata_MPORT[63], io_rdata_MPORT[62])
node io_rdata_hi_hi_hi_hi = cat(io_rdata_hi_hi_hi_hi_hi, io_rdata_hi_hi_hi_hi_lo)
node io_rdata_hi_hi_hi = cat(io_rdata_hi_hi_hi_hi, io_rdata_hi_hi_hi_lo)
node io_rdata_hi_hi = cat(io_rdata_hi_hi_hi, io_rdata_hi_hi_lo)
node io_rdata_hi = cat(io_rdata_hi_hi, io_rdata_hi_lo)
node _io_rdata_T = cat(io_rdata_hi, io_rdata_lo)
wire _io_rdata_WIRE_2 : UInt<512>
connect _io_rdata_WIRE_2, _io_rdata_T
node _io_rdata_T_1 = bits(_io_rdata_WIRE_2, 31, 0)
node _io_rdata_T_2 = asSInt(_io_rdata_T_1)
connect _io_rdata_WIRE_1[0][0], _io_rdata_T_2
node _io_rdata_T_3 = bits(_io_rdata_WIRE_2, 63, 32)
node _io_rdata_T_4 = asSInt(_io_rdata_T_3)
connect _io_rdata_WIRE_1[1][0], _io_rdata_T_4
node _io_rdata_T_5 = bits(_io_rdata_WIRE_2, 95, 64)
node _io_rdata_T_6 = asSInt(_io_rdata_T_5)
connect _io_rdata_WIRE_1[2][0], _io_rdata_T_6
node _io_rdata_T_7 = bits(_io_rdata_WIRE_2, 127, 96)
node _io_rdata_T_8 = asSInt(_io_rdata_T_7)
connect _io_rdata_WIRE_1[3][0], _io_rdata_T_8
node _io_rdata_T_9 = bits(_io_rdata_WIRE_2, 159, 128)
node _io_rdata_T_10 = asSInt(_io_rdata_T_9)
connect _io_rdata_WIRE_1[4][0], _io_rdata_T_10
node _io_rdata_T_11 = bits(_io_rdata_WIRE_2, 191, 160)
node _io_rdata_T_12 = asSInt(_io_rdata_T_11)
connect _io_rdata_WIRE_1[5][0], _io_rdata_T_12
node _io_rdata_T_13 = bits(_io_rdata_WIRE_2, 223, 192)
node _io_rdata_T_14 = asSInt(_io_rdata_T_13)
connect _io_rdata_WIRE_1[6][0], _io_rdata_T_14
node _io_rdata_T_15 = bits(_io_rdata_WIRE_2, 255, 224)
node _io_rdata_T_16 = asSInt(_io_rdata_T_15)
connect _io_rdata_WIRE_1[7][0], _io_rdata_T_16
node _io_rdata_T_17 = bits(_io_rdata_WIRE_2, 287, 256)
node _io_rdata_T_18 = asSInt(_io_rdata_T_17)
connect _io_rdata_WIRE_1[8][0], _io_rdata_T_18
node _io_rdata_T_19 = bits(_io_rdata_WIRE_2, 319, 288)
node _io_rdata_T_20 = asSInt(_io_rdata_T_19)
connect _io_rdata_WIRE_1[9][0], _io_rdata_T_20
node _io_rdata_T_21 = bits(_io_rdata_WIRE_2, 351, 320)
node _io_rdata_T_22 = asSInt(_io_rdata_T_21)
connect _io_rdata_WIRE_1[10][0], _io_rdata_T_22
node _io_rdata_T_23 = bits(_io_rdata_WIRE_2, 383, 352)
node _io_rdata_T_24 = asSInt(_io_rdata_T_23)
connect _io_rdata_WIRE_1[11][0], _io_rdata_T_24
node _io_rdata_T_25 = bits(_io_rdata_WIRE_2, 415, 384)
node _io_rdata_T_26 = asSInt(_io_rdata_T_25)
connect _io_rdata_WIRE_1[12][0], _io_rdata_T_26
node _io_rdata_T_27 = bits(_io_rdata_WIRE_2, 447, 416)
node _io_rdata_T_28 = asSInt(_io_rdata_T_27)
connect _io_rdata_WIRE_1[13][0], _io_rdata_T_28
node _io_rdata_T_29 = bits(_io_rdata_WIRE_2, 479, 448)
node _io_rdata_T_30 = asSInt(_io_rdata_T_29)
connect _io_rdata_WIRE_1[14][0], _io_rdata_T_30
node _io_rdata_T_31 = bits(_io_rdata_WIRE_2, 511, 480)
node _io_rdata_T_32 = asSInt(_io_rdata_T_31)
connect _io_rdata_WIRE_1[15][0], _io_rdata_T_32
connect io.rdata, _io_rdata_WIRE_1
when io.wen :
wire _WIRE : UInt<8>[64]
node _T_7 = asUInt(io.wdata[0][0])
node _T_8 = asUInt(io.wdata[1][0])
node _T_9 = asUInt(io.wdata[2][0])
node _T_10 = asUInt(io.wdata[3][0])
node _T_11 = asUInt(io.wdata[4][0])
node _T_12 = asUInt(io.wdata[5][0])
node _T_13 = asUInt(io.wdata[6][0])
node _T_14 = asUInt(io.wdata[7][0])
node _T_15 = asUInt(io.wdata[8][0])
node _T_16 = asUInt(io.wdata[9][0])
node _T_17 = asUInt(io.wdata[10][0])
node _T_18 = asUInt(io.wdata[11][0])
node _T_19 = asUInt(io.wdata[12][0])
node _T_20 = asUInt(io.wdata[13][0])
node _T_21 = asUInt(io.wdata[14][0])
node _T_22 = asUInt(io.wdata[15][0])
node lo_lo_lo = cat(_T_8, _T_7)
node lo_lo_hi = cat(_T_10, _T_9)
node lo_lo = cat(lo_lo_hi, lo_lo_lo)
node lo_hi_lo = cat(_T_12, _T_11)
node lo_hi_hi = cat(_T_14, _T_13)
node lo_hi = cat(lo_hi_hi, lo_hi_lo)
node lo = cat(lo_hi, lo_lo)
node hi_lo_lo = cat(_T_16, _T_15)
node hi_lo_hi = cat(_T_18, _T_17)
node hi_lo = cat(hi_lo_hi, hi_lo_lo)
node hi_hi_lo = cat(_T_20, _T_19)
node hi_hi_hi = cat(_T_22, _T_21)
node hi_hi = cat(hi_hi_hi, hi_hi_lo)
node hi = cat(hi_hi, hi_lo)
node _T_23 = cat(hi, lo)
wire _WIRE_1 : UInt<512>
connect _WIRE_1, _T_23
node _T_24 = bits(_WIRE_1, 7, 0)
connect _WIRE[0], _T_24
node _T_25 = bits(_WIRE_1, 15, 8)
connect _WIRE[1], _T_25
node _T_26 = bits(_WIRE_1, 23, 16)
connect _WIRE[2], _T_26
node _T_27 = bits(_WIRE_1, 31, 24)
connect _WIRE[3], _T_27
node _T_28 = bits(_WIRE_1, 39, 32)
connect _WIRE[4], _T_28
node _T_29 = bits(_WIRE_1, 47, 40)
connect _WIRE[5], _T_29
node _T_30 = bits(_WIRE_1, 55, 48)
connect _WIRE[6], _T_30
node _T_31 = bits(_WIRE_1, 63, 56)
connect _WIRE[7], _T_31
node _T_32 = bits(_WIRE_1, 71, 64)
connect _WIRE[8], _T_32
node _T_33 = bits(_WIRE_1, 79, 72)
connect _WIRE[9], _T_33
node _T_34 = bits(_WIRE_1, 87, 80)
connect _WIRE[10], _T_34
node _T_35 = bits(_WIRE_1, 95, 88)
connect _WIRE[11], _T_35
node _T_36 = bits(_WIRE_1, 103, 96)
connect _WIRE[12], _T_36
node _T_37 = bits(_WIRE_1, 111, 104)
connect _WIRE[13], _T_37
node _T_38 = bits(_WIRE_1, 119, 112)
connect _WIRE[14], _T_38
node _T_39 = bits(_WIRE_1, 127, 120)
connect _WIRE[15], _T_39
node _T_40 = bits(_WIRE_1, 135, 128)
connect _WIRE[16], _T_40
node _T_41 = bits(_WIRE_1, 143, 136)
connect _WIRE[17], _T_41
node _T_42 = bits(_WIRE_1, 151, 144)
connect _WIRE[18], _T_42
node _T_43 = bits(_WIRE_1, 159, 152)
connect _WIRE[19], _T_43
node _T_44 = bits(_WIRE_1, 167, 160)
connect _WIRE[20], _T_44
node _T_45 = bits(_WIRE_1, 175, 168)
connect _WIRE[21], _T_45
node _T_46 = bits(_WIRE_1, 183, 176)
connect _WIRE[22], _T_46
node _T_47 = bits(_WIRE_1, 191, 184)
connect _WIRE[23], _T_47
node _T_48 = bits(_WIRE_1, 199, 192)
connect _WIRE[24], _T_48
node _T_49 = bits(_WIRE_1, 207, 200)
connect _WIRE[25], _T_49
node _T_50 = bits(_WIRE_1, 215, 208)
connect _WIRE[26], _T_50
node _T_51 = bits(_WIRE_1, 223, 216)
connect _WIRE[27], _T_51
node _T_52 = bits(_WIRE_1, 231, 224)
connect _WIRE[28], _T_52
node _T_53 = bits(_WIRE_1, 239, 232)
connect _WIRE[29], _T_53
node _T_54 = bits(_WIRE_1, 247, 240)
connect _WIRE[30], _T_54
node _T_55 = bits(_WIRE_1, 255, 248)
connect _WIRE[31], _T_55
node _T_56 = bits(_WIRE_1, 263, 256)
connect _WIRE[32], _T_56
node _T_57 = bits(_WIRE_1, 271, 264)
connect _WIRE[33], _T_57
node _T_58 = bits(_WIRE_1, 279, 272)
connect _WIRE[34], _T_58
node _T_59 = bits(_WIRE_1, 287, 280)
connect _WIRE[35], _T_59
node _T_60 = bits(_WIRE_1, 295, 288)
connect _WIRE[36], _T_60
node _T_61 = bits(_WIRE_1, 303, 296)
connect _WIRE[37], _T_61
node _T_62 = bits(_WIRE_1, 311, 304)
connect _WIRE[38], _T_62
node _T_63 = bits(_WIRE_1, 319, 312)
connect _WIRE[39], _T_63
node _T_64 = bits(_WIRE_1, 327, 320)
connect _WIRE[40], _T_64
node _T_65 = bits(_WIRE_1, 335, 328)
connect _WIRE[41], _T_65
node _T_66 = bits(_WIRE_1, 343, 336)
connect _WIRE[42], _T_66
node _T_67 = bits(_WIRE_1, 351, 344)
connect _WIRE[43], _T_67
node _T_68 = bits(_WIRE_1, 359, 352)
connect _WIRE[44], _T_68
node _T_69 = bits(_WIRE_1, 367, 360)
connect _WIRE[45], _T_69
node _T_70 = bits(_WIRE_1, 375, 368)
connect _WIRE[46], _T_70
node _T_71 = bits(_WIRE_1, 383, 376)
connect _WIRE[47], _T_71
node _T_72 = bits(_WIRE_1, 391, 384)
connect _WIRE[48], _T_72
node _T_73 = bits(_WIRE_1, 399, 392)
connect _WIRE[49], _T_73
node _T_74 = bits(_WIRE_1, 407, 400)
connect _WIRE[50], _T_74
node _T_75 = bits(_WIRE_1, 415, 408)
connect _WIRE[51], _T_75
node _T_76 = bits(_WIRE_1, 423, 416)
connect _WIRE[52], _T_76
node _T_77 = bits(_WIRE_1, 431, 424)
connect _WIRE[53], _T_77
node _T_78 = bits(_WIRE_1, 439, 432)
connect _WIRE[54], _T_78
node _T_79 = bits(_WIRE_1, 447, 440)
connect _WIRE[55], _T_79
node _T_80 = bits(_WIRE_1, 455, 448)
connect _WIRE[56], _T_80
node _T_81 = bits(_WIRE_1, 463, 456)
connect _WIRE[57], _T_81
node _T_82 = bits(_WIRE_1, 471, 464)
connect _WIRE[58], _T_82
node _T_83 = bits(_WIRE_1, 479, 472)
connect _WIRE[59], _T_83
node _T_84 = bits(_WIRE_1, 487, 480)
connect _WIRE[60], _T_84
node _T_85 = bits(_WIRE_1, 495, 488)
connect _WIRE[61], _T_85
node _T_86 = bits(_WIRE_1, 503, 496)
connect _WIRE[62], _T_86
node _T_87 = bits(_WIRE_1, 511, 504)
connect _WIRE[63], _T_87
write mport MPORT = mem[io.waddr], clock
when io.mask[0] :
connect MPORT[0], _WIRE[0]
when io.mask[1] :
connect MPORT[1], _WIRE[1]
when io.mask[2] :
connect MPORT[2], _WIRE[2]
when io.mask[3] :
connect MPORT[3], _WIRE[3]
when io.mask[4] :
connect MPORT[4], _WIRE[4]
when io.mask[5] :
connect MPORT[5], _WIRE[5]
when io.mask[6] :
connect MPORT[6], _WIRE[6]
when io.mask[7] :
connect MPORT[7], _WIRE[7]
when io.mask[8] :
connect MPORT[8], _WIRE[8]
when io.mask[9] :
connect MPORT[9], _WIRE[9]
when io.mask[10] :
connect MPORT[10], _WIRE[10]
when io.mask[11] :
connect MPORT[11], _WIRE[11]
when io.mask[12] :
connect MPORT[12], _WIRE[12]
when io.mask[13] :
connect MPORT[13], _WIRE[13]
when io.mask[14] :
connect MPORT[14], _WIRE[14]
when io.mask[15] :
connect MPORT[15], _WIRE[15]
when io.mask[16] :
connect MPORT[16], _WIRE[16]
when io.mask[17] :
connect MPORT[17], _WIRE[17]
when io.mask[18] :
connect MPORT[18], _WIRE[18]
when io.mask[19] :
connect MPORT[19], _WIRE[19]
when io.mask[20] :
connect MPORT[20], _WIRE[20]
when io.mask[21] :
connect MPORT[21], _WIRE[21]
when io.mask[22] :
connect MPORT[22], _WIRE[22]
when io.mask[23] :
connect MPORT[23], _WIRE[23]
when io.mask[24] :
connect MPORT[24], _WIRE[24]
when io.mask[25] :
connect MPORT[25], _WIRE[25]
when io.mask[26] :
connect MPORT[26], _WIRE[26]
when io.mask[27] :
connect MPORT[27], _WIRE[27]
when io.mask[28] :
connect MPORT[28], _WIRE[28]
when io.mask[29] :
connect MPORT[29], _WIRE[29]
when io.mask[30] :
connect MPORT[30], _WIRE[30]
when io.mask[31] :
connect MPORT[31], _WIRE[31]
when io.mask[32] :
connect MPORT[32], _WIRE[32]
when io.mask[33] :
connect MPORT[33], _WIRE[33]
when io.mask[34] :
connect MPORT[34], _WIRE[34]
when io.mask[35] :
connect MPORT[35], _WIRE[35]
when io.mask[36] :
connect MPORT[36], _WIRE[36]
when io.mask[37] :
connect MPORT[37], _WIRE[37]
when io.mask[38] :
connect MPORT[38], _WIRE[38]
when io.mask[39] :
connect MPORT[39], _WIRE[39]
when io.mask[40] :
connect MPORT[40], _WIRE[40]
when io.mask[41] :
connect MPORT[41], _WIRE[41]
when io.mask[42] :
connect MPORT[42], _WIRE[42]
when io.mask[43] :
connect MPORT[43], _WIRE[43]
when io.mask[44] :
connect MPORT[44], _WIRE[44]
when io.mask[45] :
connect MPORT[45], _WIRE[45]
when io.mask[46] :
connect MPORT[46], _WIRE[46]
when io.mask[47] :
connect MPORT[47], _WIRE[47]
when io.mask[48] :
connect MPORT[48], _WIRE[48]
when io.mask[49] :
connect MPORT[49], _WIRE[49]
when io.mask[50] :
connect MPORT[50], _WIRE[50]
when io.mask[51] :
connect MPORT[51], _WIRE[51]
when io.mask[52] :
connect MPORT[52], _WIRE[52]
when io.mask[53] :
connect MPORT[53], _WIRE[53]
when io.mask[54] :
connect MPORT[54], _WIRE[54]
when io.mask[55] :
connect MPORT[55], _WIRE[55]
when io.mask[56] :
connect MPORT[56], _WIRE[56]
when io.mask[57] :
connect MPORT[57], _WIRE[57]
when io.mask[58] :
connect MPORT[58], _WIRE[58]
when io.mask[59] :
connect MPORT[59], _WIRE[59]
when io.mask[60] :
connect MPORT[60], _WIRE[60]
when io.mask[61] :
connect MPORT[61], _WIRE[61]
when io.mask[62] :
connect MPORT[62], _WIRE[62]
when io.mask[63] :
connect MPORT[63], _WIRE[63] | module TwoPortSyncMem_1( // @[SyncMem.scala:30:7]
input clock, // @[SyncMem.scala:30:7]
input reset, // @[SyncMem.scala:30:7]
input [8:0] io_waddr, // @[SyncMem.scala:31:14]
input [8:0] io_raddr, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_0_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_1_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_2_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_3_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_4_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_5_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_6_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_7_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_8_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_9_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_10_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_11_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_12_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_13_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_14_0, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_15_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_0_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_1_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_2_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_3_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_4_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_5_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_6_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_7_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_8_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_9_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_10_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_11_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_12_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_13_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_14_0, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_15_0, // @[SyncMem.scala:31:14]
input io_wen, // @[SyncMem.scala:31:14]
input io_ren, // @[SyncMem.scala:31:14]
input io_mask_0, // @[SyncMem.scala:31:14]
input io_mask_1, // @[SyncMem.scala:31:14]
input io_mask_2, // @[SyncMem.scala:31:14]
input io_mask_3, // @[SyncMem.scala:31:14]
input io_mask_4, // @[SyncMem.scala:31:14]
input io_mask_5, // @[SyncMem.scala:31:14]
input io_mask_6, // @[SyncMem.scala:31:14]
input io_mask_7, // @[SyncMem.scala:31:14]
input io_mask_8, // @[SyncMem.scala:31:14]
input io_mask_9, // @[SyncMem.scala:31:14]
input io_mask_10, // @[SyncMem.scala:31:14]
input io_mask_11, // @[SyncMem.scala:31:14]
input io_mask_12, // @[SyncMem.scala:31:14]
input io_mask_13, // @[SyncMem.scala:31:14]
input io_mask_14, // @[SyncMem.scala:31:14]
input io_mask_15, // @[SyncMem.scala:31:14]
input io_mask_16, // @[SyncMem.scala:31:14]
input io_mask_17, // @[SyncMem.scala:31:14]
input io_mask_18, // @[SyncMem.scala:31:14]
input io_mask_19, // @[SyncMem.scala:31:14]
input io_mask_20, // @[SyncMem.scala:31:14]
input io_mask_21, // @[SyncMem.scala:31:14]
input io_mask_22, // @[SyncMem.scala:31:14]
input io_mask_23, // @[SyncMem.scala:31:14]
input io_mask_24, // @[SyncMem.scala:31:14]
input io_mask_25, // @[SyncMem.scala:31:14]
input io_mask_26, // @[SyncMem.scala:31:14]
input io_mask_27, // @[SyncMem.scala:31:14]
input io_mask_28, // @[SyncMem.scala:31:14]
input io_mask_29, // @[SyncMem.scala:31:14]
input io_mask_30, // @[SyncMem.scala:31:14]
input io_mask_31, // @[SyncMem.scala:31:14]
input io_mask_32, // @[SyncMem.scala:31:14]
input io_mask_33, // @[SyncMem.scala:31:14]
input io_mask_34, // @[SyncMem.scala:31:14]
input io_mask_35, // @[SyncMem.scala:31:14]
input io_mask_36, // @[SyncMem.scala:31:14]
input io_mask_37, // @[SyncMem.scala:31:14]
input io_mask_38, // @[SyncMem.scala:31:14]
input io_mask_39, // @[SyncMem.scala:31:14]
input io_mask_40, // @[SyncMem.scala:31:14]
input io_mask_41, // @[SyncMem.scala:31:14]
input io_mask_42, // @[SyncMem.scala:31:14]
input io_mask_43, // @[SyncMem.scala:31:14]
input io_mask_44, // @[SyncMem.scala:31:14]
input io_mask_45, // @[SyncMem.scala:31:14]
input io_mask_46, // @[SyncMem.scala:31:14]
input io_mask_47, // @[SyncMem.scala:31:14]
input io_mask_48, // @[SyncMem.scala:31:14]
input io_mask_49, // @[SyncMem.scala:31:14]
input io_mask_50, // @[SyncMem.scala:31:14]
input io_mask_51, // @[SyncMem.scala:31:14]
input io_mask_52, // @[SyncMem.scala:31:14]
input io_mask_53, // @[SyncMem.scala:31:14]
input io_mask_54, // @[SyncMem.scala:31:14]
input io_mask_55, // @[SyncMem.scala:31:14]
input io_mask_56, // @[SyncMem.scala:31:14]
input io_mask_57, // @[SyncMem.scala:31:14]
input io_mask_58, // @[SyncMem.scala:31:14]
input io_mask_59, // @[SyncMem.scala:31:14]
input io_mask_60, // @[SyncMem.scala:31:14]
input io_mask_61, // @[SyncMem.scala:31:14]
input io_mask_62, // @[SyncMem.scala:31:14]
input io_mask_63 // @[SyncMem.scala:31:14]
);
wire [511:0] _mem_R0_data; // @[SyncMem.scala:45:24]
wire [8:0] io_waddr_0 = io_waddr; // @[SyncMem.scala:30:7]
wire [8:0] io_raddr_0 = io_raddr; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_0_0_0 = io_wdata_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_1_0_0 = io_wdata_1_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_2_0_0 = io_wdata_2_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_3_0_0 = io_wdata_3_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_4_0_0 = io_wdata_4_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_5_0_0 = io_wdata_5_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_6_0_0 = io_wdata_6_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_7_0_0 = io_wdata_7_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_8_0_0 = io_wdata_8_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_9_0_0 = io_wdata_9_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_10_0_0 = io_wdata_10_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_11_0_0 = io_wdata_11_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_12_0_0 = io_wdata_12_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_13_0_0 = io_wdata_13_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_14_0_0 = io_wdata_14_0; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_15_0_0 = io_wdata_15_0; // @[SyncMem.scala:30:7]
wire io_wen_0 = io_wen; // @[SyncMem.scala:30:7]
wire io_ren_0 = io_ren; // @[SyncMem.scala:30:7]
wire io_mask_0_0 = io_mask_0; // @[SyncMem.scala:30:7]
wire io_mask_1_0 = io_mask_1; // @[SyncMem.scala:30:7]
wire io_mask_2_0 = io_mask_2; // @[SyncMem.scala:30:7]
wire io_mask_3_0 = io_mask_3; // @[SyncMem.scala:30:7]
wire io_mask_4_0 = io_mask_4; // @[SyncMem.scala:30:7]
wire io_mask_5_0 = io_mask_5; // @[SyncMem.scala:30:7]
wire io_mask_6_0 = io_mask_6; // @[SyncMem.scala:30:7]
wire io_mask_7_0 = io_mask_7; // @[SyncMem.scala:30:7]
wire io_mask_8_0 = io_mask_8; // @[SyncMem.scala:30:7]
wire io_mask_9_0 = io_mask_9; // @[SyncMem.scala:30:7]
wire io_mask_10_0 = io_mask_10; // @[SyncMem.scala:30:7]
wire io_mask_11_0 = io_mask_11; // @[SyncMem.scala:30:7]
wire io_mask_12_0 = io_mask_12; // @[SyncMem.scala:30:7]
wire io_mask_13_0 = io_mask_13; // @[SyncMem.scala:30:7]
wire io_mask_14_0 = io_mask_14; // @[SyncMem.scala:30:7]
wire io_mask_15_0 = io_mask_15; // @[SyncMem.scala:30:7]
wire io_mask_16_0 = io_mask_16; // @[SyncMem.scala:30:7]
wire io_mask_17_0 = io_mask_17; // @[SyncMem.scala:30:7]
wire io_mask_18_0 = io_mask_18; // @[SyncMem.scala:30:7]
wire io_mask_19_0 = io_mask_19; // @[SyncMem.scala:30:7]
wire io_mask_20_0 = io_mask_20; // @[SyncMem.scala:30:7]
wire io_mask_21_0 = io_mask_21; // @[SyncMem.scala:30:7]
wire io_mask_22_0 = io_mask_22; // @[SyncMem.scala:30:7]
wire io_mask_23_0 = io_mask_23; // @[SyncMem.scala:30:7]
wire io_mask_24_0 = io_mask_24; // @[SyncMem.scala:30:7]
wire io_mask_25_0 = io_mask_25; // @[SyncMem.scala:30:7]
wire io_mask_26_0 = io_mask_26; // @[SyncMem.scala:30:7]
wire io_mask_27_0 = io_mask_27; // @[SyncMem.scala:30:7]
wire io_mask_28_0 = io_mask_28; // @[SyncMem.scala:30:7]
wire io_mask_29_0 = io_mask_29; // @[SyncMem.scala:30:7]
wire io_mask_30_0 = io_mask_30; // @[SyncMem.scala:30:7]
wire io_mask_31_0 = io_mask_31; // @[SyncMem.scala:30:7]
wire io_mask_32_0 = io_mask_32; // @[SyncMem.scala:30:7]
wire io_mask_33_0 = io_mask_33; // @[SyncMem.scala:30:7]
wire io_mask_34_0 = io_mask_34; // @[SyncMem.scala:30:7]
wire io_mask_35_0 = io_mask_35; // @[SyncMem.scala:30:7]
wire io_mask_36_0 = io_mask_36; // @[SyncMem.scala:30:7]
wire io_mask_37_0 = io_mask_37; // @[SyncMem.scala:30:7]
wire io_mask_38_0 = io_mask_38; // @[SyncMem.scala:30:7]
wire io_mask_39_0 = io_mask_39; // @[SyncMem.scala:30:7]
wire io_mask_40_0 = io_mask_40; // @[SyncMem.scala:30:7]
wire io_mask_41_0 = io_mask_41; // @[SyncMem.scala:30:7]
wire io_mask_42_0 = io_mask_42; // @[SyncMem.scala:30:7]
wire io_mask_43_0 = io_mask_43; // @[SyncMem.scala:30:7]
wire io_mask_44_0 = io_mask_44; // @[SyncMem.scala:30:7]
wire io_mask_45_0 = io_mask_45; // @[SyncMem.scala:30:7]
wire io_mask_46_0 = io_mask_46; // @[SyncMem.scala:30:7]
wire io_mask_47_0 = io_mask_47; // @[SyncMem.scala:30:7]
wire io_mask_48_0 = io_mask_48; // @[SyncMem.scala:30:7]
wire io_mask_49_0 = io_mask_49; // @[SyncMem.scala:30:7]
wire io_mask_50_0 = io_mask_50; // @[SyncMem.scala:30:7]
wire io_mask_51_0 = io_mask_51; // @[SyncMem.scala:30:7]
wire io_mask_52_0 = io_mask_52; // @[SyncMem.scala:30:7]
wire io_mask_53_0 = io_mask_53; // @[SyncMem.scala:30:7]
wire io_mask_54_0 = io_mask_54; // @[SyncMem.scala:30:7]
wire io_mask_55_0 = io_mask_55; // @[SyncMem.scala:30:7]
wire io_mask_56_0 = io_mask_56; // @[SyncMem.scala:30:7]
wire io_mask_57_0 = io_mask_57; // @[SyncMem.scala:30:7]
wire io_mask_58_0 = io_mask_58; // @[SyncMem.scala:30:7]
wire io_mask_59_0 = io_mask_59; // @[SyncMem.scala:30:7]
wire io_mask_60_0 = io_mask_60; // @[SyncMem.scala:30:7]
wire io_mask_61_0 = io_mask_61; // @[SyncMem.scala:30:7]
wire io_mask_62_0 = io_mask_62; // @[SyncMem.scala:30:7]
wire io_mask_63_0 = io_mask_63; // @[SyncMem.scala:30:7]
wire [8:0] _io_rdata_WIRE = io_raddr_0; // @[SyncMem.scala:30:7, :47:23]
wire [31:0] _io_rdata_WIRE_1_0_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_1_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_2_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_3_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_4_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_5_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_6_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_7_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_8_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_9_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_10_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_11_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_12_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_13_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_14_0; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_15_0; // @[SyncMem.scala:47:50]
wire [31:0] io_rdata_0_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_1_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_2_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_3_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_4_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_5_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_6_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_7_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_8_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_9_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_10_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_11_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_12_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_13_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_14_0_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_15_0_0; // @[SyncMem.scala:30:7] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_32 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_32
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_32
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_48
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_32( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_32 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_32 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_48 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_30 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_30( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] _CDom_reduced4SigExtra_T_4 = 3'h7; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = 9'h1FE; // @[primitives.scala:76:56]
wire [3:0] _CDom_reduced4SigExtra_T_6 = 4'hF; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = 4'hF; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_7 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_5 = 6'h3F; // @[primitives.scala:77:20, :78:22]
wire [5:0] _CDom_reduced4SigExtra_T_20 = 6'h3F; // @[primitives.scala:77:20, :78:22]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_3 = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51]
wire [4:0] io_fromPreMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA = 1'h1; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _CDom_reduced4SigExtra_T_8 = 1'h1; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = 1'h1; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20]
wire _notNaN_addZeros_T = 1'h1; // @[MulAddRecFN.scala:267:32]
wire _io_invalidExc_T_4 = 1'h1; // @[MulAddRecFN.scala:274:10]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire _io_rawOut_sign_T_9 = 1'h1; // @[MulAddRecFN.scala:290:37]
wire io_fromPreMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire notNaN_isInfProd = 1'h0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_invalidExc_T_5 = 1'h0; // @[MulAddRecFN.scala:275:36]
wire _io_invalidExc_T_6 = 1'h0; // @[MulAddRecFN.scala:274:36]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T = 1'h0; // @[MulAddRecFN.scala:285:27]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire notNaN_isInfOut = io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:58]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = ~io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum}; // @[MulAddRecFN.scala:205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}, :223:51]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0]}; // @[primitives.scala:124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = ~notCDom_signSigSum; // @[MulAddRecFN.scala:232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:54, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4; // @[MulAddRecFN.scala:287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = and(_T_11, _T_24)
node _T_81 = and(_T_80, _T_37)
node _T_82 = and(_T_81, _T_50)
node _T_83 = and(_T_82, _T_63)
node _T_84 = and(_T_83, _T_71)
node _T_85 = and(_T_84, _T_79)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_85, UInt<1>(0h1), "") : assert_1
node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_89 :
node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_100 = shr(io.in.a.bits.source, 2)
node _T_101 = eq(_T_100, UInt<1>(0h1))
node _T_102 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_103 = and(_T_101, _T_102)
node _T_104 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_105 = and(_T_103, _T_104)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_106 = shr(io.in.a.bits.source, 2)
node _T_107 = eq(_T_106, UInt<2>(0h2))
node _T_108 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_109 = and(_T_107, _T_108)
node _T_110 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_111 = and(_T_109, _T_110)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<2>(0h3))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_119 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_120 = or(_T_93, _T_99)
node _T_121 = or(_T_120, _T_105)
node _T_122 = or(_T_121, _T_111)
node _T_123 = or(_T_122, _T_117)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_124, _T_119)
node _T_126 = and(_T_92, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = and(_T_128, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = and(_T_127, _T_135)
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_136, UInt<1>(0h1), "") : assert_2
node _T_140 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_141 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_142 = and(_T_140, _T_141)
node _T_143 = or(UInt<1>(0h0), _T_142)
node _T_144 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = and(_T_143, _T_148)
node _T_150 = or(UInt<1>(0h0), _T_149)
node _T_151 = and(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_151, UInt<1>(0h1), "") : assert_3
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(source_ok, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_158 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_158, UInt<1>(0h1), "") : assert_5
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(is_aligned, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_165 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_165, UInt<1>(0h1), "") : assert_7
node _T_169 = not(io.in.a.bits.mask)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_170, UInt<1>(0h1), "") : assert_8
node _T_174 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_175 = asUInt(reset)
node _T_176 = eq(_T_175, UInt<1>(0h0))
when _T_176 :
node _T_177 = eq(_T_174, UInt<1>(0h0))
when _T_177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_174, UInt<1>(0h1), "") : assert_9
node _T_178 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_178 :
node _T_179 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_180 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_183 = shr(io.in.a.bits.source, 2)
node _T_184 = eq(_T_183, UInt<1>(0h0))
node _T_185 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_186 = and(_T_184, _T_185)
node _T_187 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_188 = and(_T_186, _T_187)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_189 = shr(io.in.a.bits.source, 2)
node _T_190 = eq(_T_189, UInt<1>(0h1))
node _T_191 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_192 = and(_T_190, _T_191)
node _T_193 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_194 = and(_T_192, _T_193)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_195 = shr(io.in.a.bits.source, 2)
node _T_196 = eq(_T_195, UInt<2>(0h2))
node _T_197 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_198 = and(_T_196, _T_197)
node _T_199 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_200 = and(_T_198, _T_199)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_201 = shr(io.in.a.bits.source, 2)
node _T_202 = eq(_T_201, UInt<2>(0h3))
node _T_203 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_204 = and(_T_202, _T_203)
node _T_205 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_206 = and(_T_204, _T_205)
node _T_207 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_208 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_209 = or(_T_182, _T_188)
node _T_210 = or(_T_209, _T_194)
node _T_211 = or(_T_210, _T_200)
node _T_212 = or(_T_211, _T_206)
node _T_213 = or(_T_212, _T_207)
node _T_214 = or(_T_213, _T_208)
node _T_215 = and(_T_181, _T_214)
node _T_216 = or(UInt<1>(0h0), _T_215)
node _T_217 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = and(_T_217, _T_222)
node _T_224 = or(UInt<1>(0h0), _T_223)
node _T_225 = and(_T_216, _T_224)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_225, UInt<1>(0h1), "") : assert_10
node _T_229 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_230 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_231 = and(_T_229, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_234 = cvt(_T_233)
node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000)))
node _T_236 = asSInt(_T_235)
node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0)))
node _T_238 = and(_T_232, _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = and(UInt<1>(0h0), _T_239)
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_240, UInt<1>(0h1), "") : assert_11
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(source_ok, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_248 = asUInt(reset)
node _T_249 = eq(_T_248, UInt<1>(0h0))
when _T_249 :
node _T_250 = eq(_T_247, UInt<1>(0h0))
when _T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_247, UInt<1>(0h1), "") : assert_13
node _T_251 = asUInt(reset)
node _T_252 = eq(_T_251, UInt<1>(0h0))
when _T_252 :
node _T_253 = eq(is_aligned, UInt<1>(0h0))
when _T_253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_254, UInt<1>(0h1), "") : assert_15
node _T_258 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_258, UInt<1>(0h1), "") : assert_16
node _T_262 = not(io.in.a.bits.mask)
node _T_263 = eq(_T_262, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_263, UInt<1>(0h1), "") : assert_17
node _T_267 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_267, UInt<1>(0h1), "") : assert_18
node _T_271 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_271 :
node _T_272 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_273 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_276 = shr(io.in.a.bits.source, 2)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_281 = and(_T_279, _T_280)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_282 = shr(io.in.a.bits.source, 2)
node _T_283 = eq(_T_282, UInt<1>(0h1))
node _T_284 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_285 = and(_T_283, _T_284)
node _T_286 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_287 = and(_T_285, _T_286)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_288 = shr(io.in.a.bits.source, 2)
node _T_289 = eq(_T_288, UInt<2>(0h2))
node _T_290 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_291 = and(_T_289, _T_290)
node _T_292 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_293 = and(_T_291, _T_292)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_294 = shr(io.in.a.bits.source, 2)
node _T_295 = eq(_T_294, UInt<2>(0h3))
node _T_296 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_297 = and(_T_295, _T_296)
node _T_298 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_301 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_302 = or(_T_275, _T_281)
node _T_303 = or(_T_302, _T_287)
node _T_304 = or(_T_303, _T_293)
node _T_305 = or(_T_304, _T_299)
node _T_306 = or(_T_305, _T_300)
node _T_307 = or(_T_306, _T_301)
node _T_308 = and(_T_274, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_309, UInt<1>(0h1), "") : assert_19
node _T_313 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_314 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_315 = and(_T_313, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<13>(0h1000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = and(_T_316, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(_T_323, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_323, UInt<1>(0h1), "") : assert_20
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(source_ok, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_330 = asUInt(reset)
node _T_331 = eq(_T_330, UInt<1>(0h0))
when _T_331 :
node _T_332 = eq(is_aligned, UInt<1>(0h0))
when _T_332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_333 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_333, UInt<1>(0h1), "") : assert_23
node _T_337 = eq(io.in.a.bits.mask, mask)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_337, UInt<1>(0h1), "") : assert_24
node _T_341 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_341, UInt<1>(0h1), "") : assert_25
node _T_345 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_345 :
node _T_346 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_347 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_350 = shr(io.in.a.bits.source, 2)
node _T_351 = eq(_T_350, UInt<1>(0h0))
node _T_352 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_353 = and(_T_351, _T_352)
node _T_354 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_355 = and(_T_353, _T_354)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_356 = shr(io.in.a.bits.source, 2)
node _T_357 = eq(_T_356, UInt<1>(0h1))
node _T_358 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_359 = and(_T_357, _T_358)
node _T_360 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_361 = and(_T_359, _T_360)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_362 = shr(io.in.a.bits.source, 2)
node _T_363 = eq(_T_362, UInt<2>(0h2))
node _T_364 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_365 = and(_T_363, _T_364)
node _T_366 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_367 = and(_T_365, _T_366)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_368 = shr(io.in.a.bits.source, 2)
node _T_369 = eq(_T_368, UInt<2>(0h3))
node _T_370 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_371 = and(_T_369, _T_370)
node _T_372 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_375 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_376 = or(_T_349, _T_355)
node _T_377 = or(_T_376, _T_361)
node _T_378 = or(_T_377, _T_367)
node _T_379 = or(_T_378, _T_373)
node _T_380 = or(_T_379, _T_374)
node _T_381 = or(_T_380, _T_375)
node _T_382 = and(_T_348, _T_381)
node _T_383 = or(UInt<1>(0h0), _T_382)
node _T_384 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_385 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_386 = and(_T_384, _T_385)
node _T_387 = or(UInt<1>(0h0), _T_386)
node _T_388 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_389 = cvt(_T_388)
node _T_390 = and(_T_389, asSInt(UInt<13>(0h1000)))
node _T_391 = asSInt(_T_390)
node _T_392 = eq(_T_391, asSInt(UInt<1>(0h0)))
node _T_393 = and(_T_387, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = and(_T_383, _T_394)
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_395, UInt<1>(0h1), "") : assert_26
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(source_ok, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(is_aligned, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_405 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_405, UInt<1>(0h1), "") : assert_29
node _T_409 = eq(io.in.a.bits.mask, mask)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_409, UInt<1>(0h1), "") : assert_30
node _T_413 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_413 :
node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_418 = shr(io.in.a.bits.source, 2)
node _T_419 = eq(_T_418, UInt<1>(0h0))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_424 = shr(io.in.a.bits.source, 2)
node _T_425 = eq(_T_424, UInt<1>(0h1))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_430 = shr(io.in.a.bits.source, 2)
node _T_431 = eq(_T_430, UInt<2>(0h2))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_436 = shr(io.in.a.bits.source, 2)
node _T_437 = eq(_T_436, UInt<2>(0h3))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_444 = or(_T_417, _T_423)
node _T_445 = or(_T_444, _T_429)
node _T_446 = or(_T_445, _T_435)
node _T_447 = or(_T_446, _T_441)
node _T_448 = or(_T_447, _T_442)
node _T_449 = or(_T_448, _T_443)
node _T_450 = and(_T_416, _T_449)
node _T_451 = or(UInt<1>(0h0), _T_450)
node _T_452 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_453 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_454 = and(_T_452, _T_453)
node _T_455 = or(UInt<1>(0h0), _T_454)
node _T_456 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = and(_T_455, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = and(_T_451, _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_463, UInt<1>(0h1), "") : assert_31
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(source_ok, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(is_aligned, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_473 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_473, UInt<1>(0h1), "") : assert_34
node _T_477 = not(mask)
node _T_478 = and(io.in.a.bits.mask, _T_477)
node _T_479 = eq(_T_478, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_479, UInt<1>(0h1), "") : assert_35
node _T_483 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_483 :
node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_488 = shr(io.in.a.bits.source, 2)
node _T_489 = eq(_T_488, UInt<1>(0h0))
node _T_490 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_491 = and(_T_489, _T_490)
node _T_492 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_493 = and(_T_491, _T_492)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_494 = shr(io.in.a.bits.source, 2)
node _T_495 = eq(_T_494, UInt<1>(0h1))
node _T_496 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_497 = and(_T_495, _T_496)
node _T_498 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_499 = and(_T_497, _T_498)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_500 = shr(io.in.a.bits.source, 2)
node _T_501 = eq(_T_500, UInt<2>(0h2))
node _T_502 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_503 = and(_T_501, _T_502)
node _T_504 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_505 = and(_T_503, _T_504)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_506 = shr(io.in.a.bits.source, 2)
node _T_507 = eq(_T_506, UInt<2>(0h3))
node _T_508 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_509 = and(_T_507, _T_508)
node _T_510 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_511 = and(_T_509, _T_510)
node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_513 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_514 = or(_T_487, _T_493)
node _T_515 = or(_T_514, _T_499)
node _T_516 = or(_T_515, _T_505)
node _T_517 = or(_T_516, _T_511)
node _T_518 = or(_T_517, _T_512)
node _T_519 = or(_T_518, _T_513)
node _T_520 = and(_T_486, _T_519)
node _T_521 = or(UInt<1>(0h0), _T_520)
node _T_522 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_524 = cvt(_T_523)
node _T_525 = and(_T_524, asSInt(UInt<13>(0h1000)))
node _T_526 = asSInt(_T_525)
node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0)))
node _T_528 = and(_T_522, _T_527)
node _T_529 = or(UInt<1>(0h0), _T_528)
node _T_530 = and(_T_521, _T_529)
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_530, UInt<1>(0h1), "") : assert_36
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(source_ok, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(is_aligned, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_540 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_540, UInt<1>(0h1), "") : assert_39
node _T_544 = eq(io.in.a.bits.mask, mask)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_544, UInt<1>(0h1), "") : assert_40
node _T_548 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_548 :
node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<1>(0h0))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_559 = shr(io.in.a.bits.source, 2)
node _T_560 = eq(_T_559, UInt<1>(0h1))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<2>(0h2))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<2>(0h3))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_578 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_579 = or(_T_552, _T_558)
node _T_580 = or(_T_579, _T_564)
node _T_581 = or(_T_580, _T_570)
node _T_582 = or(_T_581, _T_576)
node _T_583 = or(_T_582, _T_577)
node _T_584 = or(_T_583, _T_578)
node _T_585 = and(_T_551, _T_584)
node _T_586 = or(UInt<1>(0h0), _T_585)
node _T_587 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_588 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = and(_T_587, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = and(_T_586, _T_594)
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_595, UInt<1>(0h1), "") : assert_41
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(source_ok, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(is_aligned, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_605 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_605, UInt<1>(0h1), "") : assert_44
node _T_609 = eq(io.in.a.bits.mask, mask)
node _T_610 = asUInt(reset)
node _T_611 = eq(_T_610, UInt<1>(0h0))
when _T_611 :
node _T_612 = eq(_T_609, UInt<1>(0h0))
when _T_612 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_609, UInt<1>(0h1), "") : assert_45
node _T_613 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_613 :
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_616 = and(_T_614, _T_615)
node _T_617 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_618 = shr(io.in.a.bits.source, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_624 = shr(io.in.a.bits.source, 2)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_630 = shr(io.in.a.bits.source, 2)
node _T_631 = eq(_T_630, UInt<2>(0h2))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_636 = shr(io.in.a.bits.source, 2)
node _T_637 = eq(_T_636, UInt<2>(0h3))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_644 = or(_T_617, _T_623)
node _T_645 = or(_T_644, _T_629)
node _T_646 = or(_T_645, _T_635)
node _T_647 = or(_T_646, _T_641)
node _T_648 = or(_T_647, _T_642)
node _T_649 = or(_T_648, _T_643)
node _T_650 = and(_T_616, _T_649)
node _T_651 = or(UInt<1>(0h0), _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<13>(0h1000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = and(_T_651, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_660, UInt<1>(0h1), "") : assert_46
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(source_ok, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(is_aligned, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_670 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(_T_670, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_670, UInt<1>(0h1), "") : assert_49
node _T_674 = eq(io.in.a.bits.mask, mask)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_674, UInt<1>(0h1), "") : assert_50
node _T_678 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_678, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_682 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_T_682, UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_682, UInt<1>(0h1), "") : assert_52
node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_33 = shr(io.in.d.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_32
connect _source_ok_WIRE_1[1], _source_ok_T_38
connect _source_ok_WIRE_1[2], _source_ok_T_44
connect _source_ok_WIRE_1[3], _source_ok_T_50
connect _source_ok_WIRE_1[4], _source_ok_T_56
connect _source_ok_WIRE_1[5], _source_ok_T_57
connect _source_ok_WIRE_1[6], _source_ok_T_58
node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_686 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_686 :
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(source_ok_1, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_690 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_690, UInt<1>(0h1), "") : assert_54
node _T_694 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(_T_694, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_694, UInt<1>(0h1), "") : assert_55
node _T_698 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_698, UInt<1>(0h1), "") : assert_56
node _T_702 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_702, UInt<1>(0h1), "") : assert_57
node _T_706 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_706 :
node _T_707 = asUInt(reset)
node _T_708 = eq(_T_707, UInt<1>(0h0))
when _T_708 :
node _T_709 = eq(source_ok_1, UInt<1>(0h0))
when _T_709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_710 = asUInt(reset)
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(sink_ok, UInt<1>(0h0))
when _T_712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_713 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_714 = asUInt(reset)
node _T_715 = eq(_T_714, UInt<1>(0h0))
when _T_715 :
node _T_716 = eq(_T_713, UInt<1>(0h0))
when _T_716 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_713, UInt<1>(0h1), "") : assert_60
node _T_717 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(_T_717, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_717, UInt<1>(0h1), "") : assert_61
node _T_721 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_721, UInt<1>(0h1), "") : assert_62
node _T_725 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_725, UInt<1>(0h1), "") : assert_63
node _T_729 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_730 = or(UInt<1>(0h0), _T_729)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_730, UInt<1>(0h1), "") : assert_64
node _T_734 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_734 :
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(source_ok_1, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(sink_ok, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_741 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_741, UInt<1>(0h1), "") : assert_67
node _T_745 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_745, UInt<1>(0h1), "") : assert_68
node _T_749 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_749, UInt<1>(0h1), "") : assert_69
node _T_753 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_754 = or(_T_753, io.in.d.bits.corrupt)
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_754, UInt<1>(0h1), "") : assert_70
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_759, UInt<1>(0h1), "") : assert_71
node _T_763 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_763 :
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(source_ok_1, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_767 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_767, UInt<1>(0h1), "") : assert_73
node _T_771 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_771, UInt<1>(0h1), "") : assert_74
node _T_775 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_776, UInt<1>(0h1), "") : assert_75
node _T_780 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_780 :
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(source_ok_1, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_784 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(_T_784, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_784, UInt<1>(0h1), "") : assert_77
node _T_788 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_789 = or(_T_788, io.in.d.bits.corrupt)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_789, UInt<1>(0h1), "") : assert_78
node _T_793 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = asUInt(reset)
node _T_796 = eq(_T_795, UInt<1>(0h0))
when _T_796 :
node _T_797 = eq(_T_794, UInt<1>(0h0))
when _T_797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_794, UInt<1>(0h1), "") : assert_79
node _T_798 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_798 :
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(source_ok_1, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_802 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_803 = asUInt(reset)
node _T_804 = eq(_T_803, UInt<1>(0h0))
when _T_804 :
node _T_805 = eq(_T_802, UInt<1>(0h0))
when _T_805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_802, UInt<1>(0h1), "") : assert_81
node _T_806 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(_T_806, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_806, UInt<1>(0h1), "") : assert_82
node _T_810 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_811 = or(UInt<1>(0h0), _T_810)
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_811, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_815 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(_T_815, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_815, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_819 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_819, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_823 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_823, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_827 = eq(a_first, UInt<1>(0h0))
node _T_828 = and(io.in.a.valid, _T_827)
when _T_828 :
node _T_829 = eq(io.in.a.bits.opcode, opcode)
node _T_830 = asUInt(reset)
node _T_831 = eq(_T_830, UInt<1>(0h0))
when _T_831 :
node _T_832 = eq(_T_829, UInt<1>(0h0))
when _T_832 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_829, UInt<1>(0h1), "") : assert_87
node _T_833 = eq(io.in.a.bits.param, param)
node _T_834 = asUInt(reset)
node _T_835 = eq(_T_834, UInt<1>(0h0))
when _T_835 :
node _T_836 = eq(_T_833, UInt<1>(0h0))
when _T_836 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_833, UInt<1>(0h1), "") : assert_88
node _T_837 = eq(io.in.a.bits.size, size)
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(_T_837, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_837, UInt<1>(0h1), "") : assert_89
node _T_841 = eq(io.in.a.bits.source, source)
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_841, UInt<1>(0h1), "") : assert_90
node _T_845 = eq(io.in.a.bits.address, address)
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_845, UInt<1>(0h1), "") : assert_91
node _T_849 = and(io.in.a.ready, io.in.a.valid)
node _T_850 = and(_T_849, a_first)
when _T_850 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_851 = eq(d_first, UInt<1>(0h0))
node _T_852 = and(io.in.d.valid, _T_851)
when _T_852 :
node _T_853 = eq(io.in.d.bits.opcode, opcode_1)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_853, UInt<1>(0h1), "") : assert_92
node _T_857 = eq(io.in.d.bits.param, param_1)
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_857, UInt<1>(0h1), "") : assert_93
node _T_861 = eq(io.in.d.bits.size, size_1)
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_861, UInt<1>(0h1), "") : assert_94
node _T_865 = eq(io.in.d.bits.source, source_1)
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_865, UInt<1>(0h1), "") : assert_95
node _T_869 = eq(io.in.d.bits.sink, sink)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_869, UInt<1>(0h1), "") : assert_96
node _T_873 = eq(io.in.d.bits.denied, denied)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_873, UInt<1>(0h1), "") : assert_97
node _T_877 = and(io.in.d.ready, io.in.d.valid)
node _T_878 = and(_T_877, d_first)
when _T_878 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_879 = and(io.in.a.valid, a_first_1)
node _T_880 = and(_T_879, UInt<1>(0h1))
when _T_880 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_881 = and(io.in.a.ready, io.in.a.valid)
node _T_882 = and(_T_881, a_first_1)
node _T_883 = and(_T_882, UInt<1>(0h1))
when _T_883 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_884 = dshr(inflight, io.in.a.bits.source)
node _T_885 = bits(_T_884, 0, 0)
node _T_886 = eq(_T_885, UInt<1>(0h0))
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_886, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_890 = and(io.in.d.valid, d_first_1)
node _T_891 = and(_T_890, UInt<1>(0h1))
node _T_892 = eq(d_release_ack, UInt<1>(0h0))
node _T_893 = and(_T_891, _T_892)
when _T_893 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_894 = and(io.in.d.ready, io.in.d.valid)
node _T_895 = and(_T_894, d_first_1)
node _T_896 = and(_T_895, UInt<1>(0h1))
node _T_897 = eq(d_release_ack, UInt<1>(0h0))
node _T_898 = and(_T_896, _T_897)
when _T_898 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_899 = and(io.in.d.valid, d_first_1)
node _T_900 = and(_T_899, UInt<1>(0h1))
node _T_901 = eq(d_release_ack, UInt<1>(0h0))
node _T_902 = and(_T_900, _T_901)
when _T_902 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_903 = dshr(inflight, io.in.d.bits.source)
node _T_904 = bits(_T_903, 0, 0)
node _T_905 = or(_T_904, same_cycle_resp)
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_905, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_909 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_910 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_911 = or(_T_909, _T_910)
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_911, UInt<1>(0h1), "") : assert_100
node _T_915 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_915, UInt<1>(0h1), "") : assert_101
else :
node _T_919 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_920 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_921 = or(_T_919, _T_920)
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_921, UInt<1>(0h1), "") : assert_102
node _T_925 = eq(io.in.d.bits.size, a_size_lookup)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_925, UInt<1>(0h1), "") : assert_103
node _T_929 = and(io.in.d.valid, d_first_1)
node _T_930 = and(_T_929, a_first_1)
node _T_931 = and(_T_930, io.in.a.valid)
node _T_932 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_933 = and(_T_931, _T_932)
node _T_934 = eq(d_release_ack, UInt<1>(0h0))
node _T_935 = and(_T_933, _T_934)
when _T_935 :
node _T_936 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_937 = or(_T_936, io.in.a.ready)
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_937, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_16
node _T_941 = orr(inflight)
node _T_942 = eq(_T_941, UInt<1>(0h0))
node _T_943 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_944 = or(_T_942, _T_943)
node _T_945 = lt(watchdog, plusarg_reader.out)
node _T_946 = or(_T_944, _T_945)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_946, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_950 = and(io.in.a.ready, io.in.a.valid)
node _T_951 = and(io.in.d.ready, io.in.d.valid)
node _T_952 = or(_T_950, _T_951)
when _T_952 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<13>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_953 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<13>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_954 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_955 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_956 = and(_T_954, _T_955)
node _T_957 = and(_T_953, _T_956)
when _T_957 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<13>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_958 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_959 = and(_T_958, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<13>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_960 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_961 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_962 = and(_T_960, _T_961)
node _T_963 = and(_T_959, _T_962)
when _T_963 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<13>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_964 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_965 = bits(_T_964, 0, 0)
node _T_966 = eq(_T_965, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_966, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_970 = and(io.in.d.valid, d_first_2)
node _T_971 = and(_T_970, UInt<1>(0h1))
node _T_972 = and(_T_971, d_release_ack_1)
when _T_972 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_973 = and(io.in.d.ready, io.in.d.valid)
node _T_974 = and(_T_973, d_first_2)
node _T_975 = and(_T_974, UInt<1>(0h1))
node _T_976 = and(_T_975, d_release_ack_1)
when _T_976 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_977 = and(io.in.d.valid, d_first_2)
node _T_978 = and(_T_977, UInt<1>(0h1))
node _T_979 = and(_T_978, d_release_ack_1)
when _T_979 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_980 = dshr(inflight_1, io.in.d.bits.source)
node _T_981 = bits(_T_980, 0, 0)
node _T_982 = or(_T_981, same_cycle_resp_1)
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_982, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<13>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_986 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_986, UInt<1>(0h1), "") : assert_108
else :
node _T_990 = eq(io.in.d.bits.size, c_size_lookup)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_990, UInt<1>(0h1), "") : assert_109
node _T_994 = and(io.in.d.valid, d_first_2)
node _T_995 = and(_T_994, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<13>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_996 = and(_T_995, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<13>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_997 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_998 = and(_T_996, _T_997)
node _T_999 = and(_T_998, d_release_ack_1)
node _T_1000 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1001 = and(_T_999, _T_1000)
when _T_1001 :
node _T_1002 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<13>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1003 = or(_T_1002, _WIRE_23.ready)
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_17
node _T_1007 = orr(inflight_1)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
node _T_1009 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1010 = or(_T_1008, _T_1009)
node _T_1011 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1012 = or(_T_1010, _T_1011)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<13>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1016 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1017 = and(io.in.d.ready, io.in.d.valid)
node _T_1018 = or(_T_1016, _T_1017)
when _T_1018 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_8( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [12:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_33 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_45 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_51 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_950 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_950; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_950; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
wire _T_1018 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1018; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1018; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1018; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_883 = _T_950 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_883 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_883 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_883 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_883 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_883 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_929 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_929 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_898 = _T_1018 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_898 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_898 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_898 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_994 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_976 = _T_1018 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_976 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_976 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_976 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o2_a32d64s6k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn_1.e.bits.sink
invalidate anonIn_1.e.valid
invalidate anonIn_1.e.ready
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.c.bits.corrupt
invalidate anonIn_1.c.bits.data
invalidate anonIn_1.c.bits.address
invalidate anonIn_1.c.bits.source
invalidate anonIn_1.c.bits.size
invalidate anonIn_1.c.bits.param
invalidate anonIn_1.c.bits.opcode
invalidate anonIn_1.c.valid
invalidate anonIn_1.c.ready
invalidate anonIn_1.b.bits.corrupt
invalidate anonIn_1.b.bits.data
invalidate anonIn_1.b.bits.mask
invalidate anonIn_1.b.bits.address
invalidate anonIn_1.b.bits.source
invalidate anonIn_1.b.bits.size
invalidate anonIn_1.b.bits.param
invalidate anonIn_1.b.bits.opcode
invalidate anonIn_1.b.valid
invalidate anonIn_1.b.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, anonIn_1.e.valid
connect monitor_1.io.in.e.ready, anonIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, anonIn_1.c.valid
connect monitor_1.io.in.c.ready, anonIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, anonIn_1.b.valid
connect monitor_1.io.in.b.ready, anonIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_anonOut.e.bits.sink
invalidate x1_anonOut.e.valid
invalidate x1_anonOut.e.ready
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.c.bits.corrupt
invalidate x1_anonOut.c.bits.data
invalidate x1_anonOut.c.bits.address
invalidate x1_anonOut.c.bits.source
invalidate x1_anonOut.c.bits.size
invalidate x1_anonOut.c.bits.param
invalidate x1_anonOut.c.bits.opcode
invalidate x1_anonOut.c.valid
invalidate x1_anonOut.c.ready
invalidate x1_anonOut.b.bits.corrupt
invalidate x1_anonOut.b.bits.data
invalidate x1_anonOut.b.bits.mask
invalidate x1_anonOut.b.bits.address
invalidate x1_anonOut.b.bits.source
invalidate x1_anonOut.b.bits.size
invalidate x1_anonOut.b.bits.param
invalidate x1_anonOut.b.bits.opcode
invalidate x1_anonOut.b.valid
invalidate x1_anonOut.b.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
invalidate in[0].b.valid
invalidate in[0].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[0].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[0].c.bits.corrupt
invalidate in[0].c.bits.data
invalidate in[0].c.bits.address
invalidate in[0].c.bits.source
invalidate in[0].c.bits.size
invalidate in[0].c.bits.param
invalidate in[0].c.bits.opcode
invalidate in[0].c.valid
invalidate in[0].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[0].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
invalidate in[0].e.bits.sink
invalidate in[0].e.valid
invalidate in[0].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[0].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20))
connect in[1].a.bits.source, _in_1_a_bits_source_T
connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt
connect anonIn_1.b.bits.data, in[1].b.bits.data
connect anonIn_1.b.bits.mask, in[1].b.bits.mask
connect anonIn_1.b.bits.address, in[1].b.bits.address
connect anonIn_1.b.bits.source, in[1].b.bits.source
connect anonIn_1.b.bits.size, in[1].b.bits.size
connect anonIn_1.b.bits.param, in[1].b.bits.param
connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode
connect anonIn_1.b.valid, in[1].b.valid
connect in[1].b.ready, anonIn_1.b.ready
node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0)
connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T
connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt
connect in[1].c.bits.data, anonIn_1.c.bits.data
connect in[1].c.bits.address, anonIn_1.c.bits.address
connect in[1].c.bits.source, anonIn_1.c.bits.source
connect in[1].c.bits.size, anonIn_1.c.bits.size
connect in[1].c.bits.param, anonIn_1.c.bits.param
connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode
connect in[1].c.valid, anonIn_1.c.valid
connect anonIn_1.c.ready, in[1].c.ready
node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<6>(0h20))
connect in[1].c.bits.source, _in_1_c_bits_source_T
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
connect in[1].e.bits.sink, anonIn_1.e.bits.sink
connect in[1].e.valid, anonIn_1.e.valid
connect anonIn_1.e.ready, in[1].e.ready
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
invalidate out[0].b.bits.corrupt
invalidate out[0].b.bits.data
invalidate out[0].b.bits.mask
invalidate out[0].b.bits.address
invalidate out[0].b.bits.source
invalidate out[0].b.bits.size
invalidate out[0].b.bits.param
invalidate out[0].b.bits.opcode
invalidate out[0].b.valid
invalidate out[0].b.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.mask, UInt<8>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<2>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
invalidate _WIRE_13.bits.corrupt
invalidate _WIRE_13.bits.data
invalidate _WIRE_13.bits.mask
invalidate _WIRE_13.bits.address
invalidate _WIRE_13.bits.source
invalidate _WIRE_13.bits.size
invalidate _WIRE_13.bits.param
invalidate _WIRE_13.bits.opcode
invalidate _WIRE_13.valid
invalidate _WIRE_13.ready
connect out[0].b.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.mask, UInt<8>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<2>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].c.valid
invalidate out[0].c.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.corrupt
invalidate _WIRE_17.bits.data
invalidate _WIRE_17.bits.address
invalidate _WIRE_17.bits.source
invalidate _WIRE_17.bits.size
invalidate _WIRE_17.bits.param
invalidate _WIRE_17.bits.opcode
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
connect out[0].c.ready, UInt<1>(0h1)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
invalidate out[0].e.bits.sink
invalidate out[0].e.valid
invalidate out[0].e.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
invalidate _WIRE_21.bits.sink
invalidate _WIRE_21.valid
invalidate _WIRE_21.ready
connect out[0].e.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.valid, UInt<1>(0h0)
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt
connect out[1].b.bits.data, x1_anonOut.b.bits.data
connect out[1].b.bits.mask, x1_anonOut.b.bits.mask
connect out[1].b.bits.address, x1_anonOut.b.bits.address
connect out[1].b.bits.source, x1_anonOut.b.bits.source
connect out[1].b.bits.size, x1_anonOut.b.bits.size
connect out[1].b.bits.param, x1_anonOut.b.bits.param
connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode
connect out[1].b.valid, x1_anonOut.b.valid
connect x1_anonOut.b.ready, out[1].b.ready
connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt
connect x1_anonOut.c.bits.data, out[1].c.bits.data
connect x1_anonOut.c.bits.address, out[1].c.bits.address
connect x1_anonOut.c.bits.source, out[1].c.bits.source
connect x1_anonOut.c.bits.size, out[1].c.bits.size
connect x1_anonOut.c.bits.param, out[1].c.bits.param
connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode
connect x1_anonOut.c.valid, out[1].c.valid
connect out[1].c.ready, x1_anonOut.c.ready
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
connect x1_anonOut.e.bits.sink, out[1].e.bits.sink
connect x1_anonOut.e.valid, out[1].e.valid
connect out[1].e.ready, x1_anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 2, 0)
connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c012000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9)
node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14)
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16)
node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_18 = cvt(_requestAIO_T_17)
node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_20 = asSInt(_requestAIO_T_19)
node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0)))
node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_23 = cvt(_requestAIO_T_22)
node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_25 = asSInt(_requestAIO_T_24)
node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0)))
node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26)
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27)
node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_29 = cvt(_requestAIO_T_28)
node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_31 = asSInt(_requestAIO_T_30)
node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0)))
node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_34 = cvt(_requestAIO_T_33)
node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c012000)))
node _requestAIO_T_36 = asSInt(_requestAIO_T_35)
node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0)))
node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_39 = cvt(_requestAIO_T_38)
node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_41 = asSInt(_requestAIO_T_40)
node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0)))
node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37)
node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42)
node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44)
node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_46 = cvt(_requestAIO_T_45)
node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_48 = asSInt(_requestAIO_T_47)
node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0)))
node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_51 = cvt(_requestAIO_T_50)
node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_53 = asSInt(_requestAIO_T_52)
node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0)))
node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54)
node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0)
node _requestBOI_T_5 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<4>(0h8))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestBOI_uncommonBits_T_2 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0)
node _requestBOI_T_10 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f))
node requestBOI_1_0 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestBOI_uncommonBits_T_3 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 1, 0)
node _requestBOI_T_15 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<4>(0h8))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<2>(0h3))
node requestBOI_1_1 = and(_requestBOI_T_18, _requestBOI_T_19)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<4>(0h8))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0)
node _requestDOI_T_10 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f))
node requestDOI_1_0 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 1, 0)
node _requestDOI_T_15 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<4>(0h8))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<2>(0h3))
node requestDOI_1_1 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect portsAOI_filtered_1[1].bits, in[1].a.bits
node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2)
connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3
node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1)
wire _portsAOI_in_1_a_ready_WIRE : UInt<1>
connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2
connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2)
connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3
node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_2 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1)
wire _portsBIO_out_1_b_ready_WIRE : UInt<1>
connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_2
connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, in[0].c.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1)
wire _portsCOI_in_0_c_ready_WIRE : UInt<1>
connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2
connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect portsCOI_filtered_1[1].bits, in[1].c.bits
node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2)
connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3
node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1)
wire _portsCOI_in_1_c_ready_WIRE : UInt<1>
connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2
connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2)
connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3
node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_2 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1)
wire _portsDIO_out_1_d_ready_WIRE : UInt<1>
connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_2
connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, in[0].e.bits
node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1)
wire _portsEOI_in_0_e_ready_WIRE : UInt<1>
connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2
connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect portsEOI_filtered_1[1].bits, in[1].e.bits
node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2)
connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3
node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1)
wire _portsEOI_in_1_e_ready_WIRE : UInt<1>
connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2
connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<6>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].e.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, out[1].a.ready)
node _readys_T_10 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid)
node readys_valid_1 = bits(_readys_T_10, 1, 0)
node _readys_T_11 = eq(readys_valid_1, _readys_T_10)
node _readys_T_12 = asUInt(reset)
node _readys_T_13 = eq(_readys_T_12, UInt<1>(0h0))
when _readys_T_13 :
node _readys_T_14 = eq(_readys_T_11, UInt<1>(0h0))
when _readys_T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1
assert(clock, _readys_T_11, UInt<1>(0h1), "") : readys_assert_1
regreset readys_mask_1 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_2 = not(readys_mask_1)
node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2)
node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1)
node _readys_unready_T_5 = shr(readys_filter_1, 1)
node _readys_unready_T_6 = or(readys_filter_1, _readys_unready_T_5)
node _readys_unready_T_7 = bits(_readys_unready_T_6, 3, 0)
node _readys_unready_T_8 = shr(_readys_unready_T_7, 1)
node _readys_unready_T_9 = shl(readys_mask_1, 2)
node readys_unready_1 = or(_readys_unready_T_8, _readys_unready_T_9)
node _readys_readys_T_3 = shr(readys_unready_1, 2)
node _readys_readys_T_4 = bits(readys_unready_1, 1, 0)
node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4)
node readys_readys_1 = not(_readys_readys_T_5)
node _readys_T_15 = orr(readys_valid_1)
node _readys_T_16 = and(latch_1, _readys_T_15)
when _readys_T_16 :
node _readys_mask_T_5 = and(readys_readys_1, readys_valid_1)
node _readys_mask_T_6 = shl(_readys_mask_T_5, 1)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 1, 0)
node _readys_mask_T_8 = or(_readys_mask_T_5, _readys_mask_T_7)
node _readys_mask_T_9 = bits(_readys_mask_T_8, 1, 0)
connect readys_mask_1, _readys_mask_T_9
node _readys_T_17 = bits(readys_readys_1, 1, 0)
node _readys_T_18 = bits(_readys_T_17, 0, 0)
node _readys_T_19 = bits(_readys_T_17, 1, 1)
wire readys_1 : UInt<1>[2]
connect readys_1[0], _readys_T_18
connect readys_1[1], _readys_T_19
node _winner_T_2 = and(readys_1[0], portsAOI_filtered[1].valid)
node _winner_T_3 = and(readys_1[1], portsAOI_filtered_1[1].valid)
wire winner_1 : UInt<1>[2]
connect winner_1[0], _winner_T_2
connect winner_1[1], _winner_T_3
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1])
node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_18 = eq(winner_1[0], UInt<1>(0h0))
node _T_19 = or(_T_17, _T_18)
node _T_20 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_21 = eq(winner_1[1], UInt<1>(0h0))
node _T_22 = or(_T_20, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_23, UInt<1>(0h1), "") : assert_2
node _T_27 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = or(winner_1[0], winner_1[1])
node _T_30 = or(_T_28, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_30, UInt<1>(0h1), "") : assert_3
node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0))
node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1)
node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[2]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0])
connect portsAOI_filtered[1].ready, _filtered_1_ready_T
node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1])
connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1
node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _out_1_a_valid_T_1 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_2 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_1, _out_1_a_valid_T_2)
wire _out_1_a_valid_WIRE : UInt<1>
connect _out_1_a_valid_WIRE, _out_1_a_valid_T_3
node _out_1_a_valid_T_4 = mux(idle_1, _out_1_a_valid_T, _out_1_a_valid_WIRE)
connect out[1].a.valid, _out_1_a_valid_T_4
wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_2 = or(_out_1_a_bits_T, _out_1_a_bits_T_1)
wire _out_1_a_bits_WIRE_1 : UInt<1>
connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_2
connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1
node _out_1_a_bits_T_3 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_4 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_4)
wire _out_1_a_bits_WIRE_2 : UInt<64>
connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_5
connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2
node _out_1_a_bits_T_6 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_7 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_7)
wire _out_1_a_bits_WIRE_3 : UInt<8>
connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_8
connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3
wire _out_1_a_bits_WIRE_4 : { }
connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4
wire _out_1_a_bits_WIRE_5 : { }
connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5
node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10)
wire _out_1_a_bits_WIRE_6 : UInt<32>
connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_11
connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6
node _out_1_a_bits_T_12 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_13 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_13)
wire _out_1_a_bits_WIRE_7 : UInt<6>
connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_14
connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7
node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16)
wire _out_1_a_bits_WIRE_8 : UInt<4>
connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_17
connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8
node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19)
wire _out_1_a_bits_WIRE_9 : UInt<3>
connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_20
connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9
node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22)
wire _out_1_a_bits_WIRE_10 : UInt<3>
connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_23
connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10
connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt
connect out[1].a.bits.data, _out_1_a_bits_WIRE.data
connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask
connect out[1].a.bits.address, _out_1_a_bits_WIRE.address
connect out[1].a.bits.source, _out_1_a_bits_WIRE.source
connect out[1].a.bits.size, _out_1_a_bits_WIRE.size
connect out[1].a.bits.param, _out_1_a_bits_WIRE.param
connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode
connect out[1].c, portsCOI_filtered_1[1]
connect out[1].e, portsEOI_filtered_1[1]
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, in[0].d.ready)
node _readys_T_20 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid_2 = bits(_readys_T_20, 1, 0)
node _readys_T_21 = eq(readys_valid_2, _readys_T_20)
node _readys_T_22 = asUInt(reset)
node _readys_T_23 = eq(_readys_T_22, UInt<1>(0h0))
when _readys_T_23 :
node _readys_T_24 = eq(_readys_T_21, UInt<1>(0h0))
when _readys_T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2
assert(clock, _readys_T_21, UInt<1>(0h1), "") : readys_assert_2
regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_4 = not(readys_mask_2)
node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4)
node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2)
node _readys_unready_T_10 = shr(readys_filter_2, 1)
node _readys_unready_T_11 = or(readys_filter_2, _readys_unready_T_10)
node _readys_unready_T_12 = bits(_readys_unready_T_11, 3, 0)
node _readys_unready_T_13 = shr(_readys_unready_T_12, 1)
node _readys_unready_T_14 = shl(readys_mask_2, 2)
node readys_unready_2 = or(_readys_unready_T_13, _readys_unready_T_14)
node _readys_readys_T_6 = shr(readys_unready_2, 2)
node _readys_readys_T_7 = bits(readys_unready_2, 1, 0)
node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7)
node readys_readys_2 = not(_readys_readys_T_8)
node _readys_T_25 = orr(readys_valid_2)
node _readys_T_26 = and(latch_2, _readys_T_25)
when _readys_T_26 :
node _readys_mask_T_10 = and(readys_readys_2, readys_valid_2)
node _readys_mask_T_11 = shl(_readys_mask_T_10, 1)
node _readys_mask_T_12 = bits(_readys_mask_T_11, 1, 0)
node _readys_mask_T_13 = or(_readys_mask_T_10, _readys_mask_T_12)
node _readys_mask_T_14 = bits(_readys_mask_T_13, 1, 0)
connect readys_mask_2, _readys_mask_T_14
node _readys_T_27 = bits(readys_readys_2, 1, 0)
node _readys_T_28 = bits(_readys_T_27, 0, 0)
node _readys_T_29 = bits(_readys_T_27, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_28
connect readys_2[1], _readys_T_29
node _winner_T_4 = and(readys_2[0], portsDIO_filtered[0].valid)
node _winner_T_5 = and(readys_2[1], portsDIO_filtered_1[0].valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_4
connect winner_2[1], _winner_T_5
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_34 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_35 = eq(winner_2[0], UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_38 = eq(winner_2[1], UInt<1>(0h0))
node _T_39 = or(_T_37, _T_38)
node _T_40 = and(_T_36, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_40, UInt<1>(0h1), "") : assert_4
node _T_44 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = or(winner_2[0], winner_2[1])
node _T_47 = or(_T_45, _T_46)
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_47, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed_2[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_3
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<3>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<6>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<4>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect in[1].b, portsBIO_filtered_1[1]
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in[1].d.ready)
node _readys_T_30 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid)
node readys_valid_3 = bits(_readys_T_30, 1, 0)
node _readys_T_31 = eq(readys_valid_3, _readys_T_30)
node _readys_T_32 = asUInt(reset)
node _readys_T_33 = eq(_readys_T_32, UInt<1>(0h0))
when _readys_T_33 :
node _readys_T_34 = eq(_readys_T_31, UInt<1>(0h0))
when _readys_T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3
assert(clock, _readys_T_31, UInt<1>(0h1), "") : readys_assert_3
regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_6 = not(readys_mask_3)
node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6)
node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3)
node _readys_unready_T_15 = shr(readys_filter_3, 1)
node _readys_unready_T_16 = or(readys_filter_3, _readys_unready_T_15)
node _readys_unready_T_17 = bits(_readys_unready_T_16, 3, 0)
node _readys_unready_T_18 = shr(_readys_unready_T_17, 1)
node _readys_unready_T_19 = shl(readys_mask_3, 2)
node readys_unready_3 = or(_readys_unready_T_18, _readys_unready_T_19)
node _readys_readys_T_9 = shr(readys_unready_3, 2)
node _readys_readys_T_10 = bits(readys_unready_3, 1, 0)
node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10)
node readys_readys_3 = not(_readys_readys_T_11)
node _readys_T_35 = orr(readys_valid_3)
node _readys_T_36 = and(latch_3, _readys_T_35)
when _readys_T_36 :
node _readys_mask_T_15 = and(readys_readys_3, readys_valid_3)
node _readys_mask_T_16 = shl(_readys_mask_T_15, 1)
node _readys_mask_T_17 = bits(_readys_mask_T_16, 1, 0)
node _readys_mask_T_18 = or(_readys_mask_T_15, _readys_mask_T_17)
node _readys_mask_T_19 = bits(_readys_mask_T_18, 1, 0)
connect readys_mask_3, _readys_mask_T_19
node _readys_T_37 = bits(readys_readys_3, 1, 0)
node _readys_T_38 = bits(_readys_T_37, 0, 0)
node _readys_T_39 = bits(_readys_T_37, 1, 1)
wire readys_3 : UInt<1>[2]
connect readys_3[0], _readys_T_38
connect readys_3[1], _readys_T_39
node _winner_T_6 = and(readys_3[0], portsDIO_filtered[1].valid)
node _winner_T_7 = and(readys_3[1], portsDIO_filtered_1[1].valid)
wire winner_3 : UInt<1>[2]
connect winner_3[0], _winner_T_6
connect winner_3[1], _winner_T_7
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1])
node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_52 = eq(winner_3[0], UInt<1>(0h0))
node _T_53 = or(_T_51, _T_52)
node _T_54 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_55 = eq(winner_3[1], UInt<1>(0h0))
node _T_56 = or(_T_54, _T_55)
node _T_57 = and(_T_53, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6
assert(clock, _T_57, UInt<1>(0h1), "") : assert_6
node _T_61 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _T_62 = eq(_T_61, UInt<1>(0h0))
node _T_63 = or(winner_3[0], winner_3[1])
node _T_64 = or(_T_62, _T_63)
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7
assert(clock, _T_64, UInt<1>(0h1), "") : assert_7
node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0))
node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3)
node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[2]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _filtered_1_ready_T_2 = and(in[1].d.ready, allowed_3[0])
connect portsDIO_filtered[1].ready, _filtered_1_ready_T_2
node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[1])
connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_3
node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2)
wire _in_1_d_valid_WIRE : UInt<1>
connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3
node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE)
connect in[1].d.valid, _in_1_d_valid_T_4
wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1)
wire _in_1_d_bits_WIRE_1 : UInt<1>
connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2
connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1
node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4)
wire _in_1_d_bits_WIRE_2 : UInt<64>
connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5
connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2
wire _in_1_d_bits_WIRE_3 : { }
connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3
wire _in_1_d_bits_WIRE_4 : { }
connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4
node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7)
wire _in_1_d_bits_WIRE_5 : UInt<1>
connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8
connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5
node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10)
wire _in_1_d_bits_WIRE_6 : UInt<3>
connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11
connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6
node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13)
wire _in_1_d_bits_WIRE_7 : UInt<6>
connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14
connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7
node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16)
wire _in_1_d_bits_WIRE_8 : UInt<4>
connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17
connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8
node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19)
wire _in_1_d_bits_WIRE_9 : UInt<2>
connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20
connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9
node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22)
wire _in_1_d_bits_WIRE_10 : UInt<3>
connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23
connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10
connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt
connect in[1].d.bits.data, _in_1_d_bits_WIRE.data
connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied
connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink
connect in[1].d.bits.source, _in_1_d_bits_WIRE.source
connect in[1].d.bits.size, _in_1_d_bits_WIRE.size
connect in[1].d.bits.param, _in_1_d_bits_WIRE.param
connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_sbus_i2_o2_a32d64s6k3z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire allowed_3_1; // @[Arbiter.scala:92:24]
wire allowed_3_0; // @[Arbiter.scala:92:24]
wire allowed_2_1; // @[Arbiter.scala:92:24]
wire allowed_2_0; // @[Arbiter.scala:92:24]
wire allowed_1_1; // @[Arbiter.scala:92:24]
wire allowed_1_0; // @[Arbiter.scala:92:24]
wire allowed_1; // @[Arbiter.scala:92:24]
wire allowed_0; // @[Arbiter.scala:92:24]
wire [5:0] in_0_a_bits_source = {1'h0, auto_anon_in_0_a_bits_source}; // @[Xbar.scala:74:9, :166:29]
wire [5:0] in_1_a_bits_source = {4'h8, auto_anon_in_1_a_bits_source}; // @[Xbar.scala:166:55]
wire [2:0] out_0_d_bits_sink = {2'h0, auto_anon_out_0_d_bits_sink}; // @[Xbar.scala:74:9, :251:28]
wire [3:0] out_1_d_bits_size = {1'h0, auto_anon_out_1_d_bits_size}; // @[Xbar.scala:74:9, :250:29]
wire requestAIO_0_0 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26]} == 3'h0 | {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26], ~(auto_anon_in_0_a_bits_address[16]), auto_anon_in_0_a_bits_address[13]} == 5'h0 | {auto_anon_in_0_a_bits_address[31], ~(auto_anon_in_0_a_bits_address[27:26])} == 3'h0; // @[Xbar.scala:291:92]
wire requestAIO_0_1 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26] ^ 2'h2, auto_anon_in_0_a_bits_address[16]} == 4'h0 | auto_anon_in_0_a_bits_address[31]; // @[Xbar.scala:74:9, :291:92]
wire requestAIO_1_0 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26]} == 3'h0 | {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26], ~(auto_anon_in_1_a_bits_address[16]), auto_anon_in_1_a_bits_address[13]} == 5'h0 | {auto_anon_in_1_a_bits_address[31], ~(auto_anon_in_1_a_bits_address[27:26])} == 3'h0; // @[Xbar.scala:291:92]
wire requestAIO_1_1 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26] ^ 2'h2, auto_anon_in_1_a_bits_address[16]} == 4'h0 | auto_anon_in_1_a_bits_address[31]; // @[Xbar.scala:74:9, :291:92]
wire requestDOI_0_1 = auto_anon_out_0_d_bits_source[5:2] == 4'h8; // @[Parameters.scala:54:{10,32}]
wire requestDOI_1_1 = auto_anon_out_1_d_bits_source[5:2] == 4'h8; // @[Parameters.scala:54:{10,32}]
wire portsAOI_filtered_0_valid = auto_anon_in_0_a_valid & requestAIO_0_0; // @[Xbar.scala:291:92, :355:40]
wire portsAOI_filtered_1_valid = auto_anon_in_0_a_valid & requestAIO_0_1; // @[Xbar.scala:291:92, :355:40]
wire _portsAOI_in_0_a_ready_T_2 = requestAIO_0_0 & auto_anon_out_0_a_ready & allowed_0 | requestAIO_0_1 & auto_anon_out_1_a_ready & allowed_1_0; // @[Mux.scala:30:73]
wire portsAOI_filtered_1_0_valid = auto_anon_in_1_a_valid & requestAIO_1_0; // @[Xbar.scala:291:92, :355:40]
wire portsAOI_filtered_1_1_valid = auto_anon_in_1_a_valid & requestAIO_1_1; // @[Xbar.scala:291:92, :355:40]
wire _portsAOI_in_1_a_ready_T_2 = requestAIO_1_0 & auto_anon_out_0_a_ready & allowed_1 | requestAIO_1_1 & auto_anon_out_1_a_ready & allowed_1_1; // @[Mux.scala:30:73]
wire portsDIO_filtered_0_valid = auto_anon_out_0_d_valid & ~(auto_anon_out_0_d_bits_source[5]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_0_valid = auto_anon_out_1_d_valid & ~(auto_anon_out_1_d_bits_source[5]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_1_valid = auto_anon_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala:355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], portsAOI_filtered_1_0_valid} | _readys_filter_T_1)); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & portsAOI_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_1 = readys_readys[1] & portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_0 = idle ? readys_readys[0] : state_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1 = idle ? readys_readys[1] : state_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_0_a_valid = idle ? _out_0_a_valid_T : state_0 & portsAOI_filtered_0_valid | state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_1 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_1; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_3 = readys_valid_1 & ~readys_mask_1; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_1 = ~({readys_mask_1[1], _readys_filter_T_3[1] | readys_mask_1[0]} & ({_readys_filter_T_3[0], portsAOI_filtered_1_1_valid} | _readys_filter_T_3)); // @[package.scala:262:43]
wire winner_1_0 = readys_readys_1[0] & portsAOI_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_1_1 = readys_readys_1[1] & portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_1_0 = idle_1 ? readys_readys_1[0] : state_1_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1_1 = idle_1 ? readys_readys_1[1] : state_1_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_1_a_valid = idle_1 ? _out_1_a_valid_T : state_1_0 & portsAOI_filtered_1_valid | state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_2 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_5 = readys_valid_2 & ~readys_mask_2; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_2 = ~({readys_mask_2[1], _readys_filter_T_5[1] | readys_mask_2[0]} & ({_readys_filter_T_5[0], portsDIO_filtered_1_0_valid} | _readys_filter_T_5)); // @[package.scala:262:43]
wire winner_2_0 = readys_readys_2[0] & portsDIO_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_2_1 = readys_readys_2[1] & portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_2_0 = idle_2 ? readys_readys_2[0] : state_2_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_2_1 = idle_2 ? readys_readys_2[1] : state_2_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire in_0_d_valid = idle_2 ? _in_0_d_valid_T : state_2_0 & portsDIO_filtered_0_valid | state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = muxState_2_0 & auto_anon_out_0_d_bits_corrupt | muxState_2_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = muxState_2_0 & auto_anon_out_0_d_bits_denied | muxState_2_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_11 = (muxState_2_0 ? out_0_d_bits_sink : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_sink : 3'h0); // @[Mux.scala:30:73]
wire [4:0] _in_0_d_bits_T_14 = (muxState_2_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_17 = (muxState_2_0 ? auto_anon_out_0_d_bits_size : 4'h0) | (muxState_2_1 ? out_1_d_bits_size : 4'h0); // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = (muxState_2_0 ? auto_anon_out_0_d_bits_param : 2'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_param : 2'h0); // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_23 = (muxState_2_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73]
reg [8:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_3 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_7 = readys_valid_3 & ~readys_mask_3; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_3 = ~({readys_mask_3[1], _readys_filter_T_7[1] | readys_mask_3[0]} & ({_readys_filter_T_7[0], portsDIO_filtered_1_1_valid} | _readys_filter_T_7)); // @[package.scala:262:43]
wire winner_3_0 = readys_readys_3[0] & portsDIO_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_3_1 = readys_readys_3[1] & portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_178 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_178( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_from_port_named_rerocc_0 :
input clock : Clock
input reset : Reset
output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
inst buffer of TLBuffer_a32d64s1k3z4c
connect buffer.clock, clock
connect buffer.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlOut.e.bits.sink
invalidate tlOut.e.valid
invalidate tlOut.e.ready
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.c.bits.corrupt
invalidate tlOut.c.bits.data
invalidate tlOut.c.bits.address
invalidate tlOut.c.bits.source
invalidate tlOut.c.bits.size
invalidate tlOut.c.bits.param
invalidate tlOut.c.bits.opcode
invalidate tlOut.c.valid
invalidate tlOut.c.ready
invalidate tlOut.b.bits.corrupt
invalidate tlOut.b.bits.data
invalidate tlOut.b.bits.mask
invalidate tlOut.b.bits.address
invalidate tlOut.b.bits.source
invalidate tlOut.b.bits.size
invalidate tlOut.b.bits.param
invalidate tlOut.b.bits.opcode
invalidate tlOut.b.valid
invalidate tlOut.b.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlIn.e.bits.sink
invalidate tlIn.e.valid
invalidate tlIn.e.ready
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.c.bits.corrupt
invalidate tlIn.c.bits.data
invalidate tlIn.c.bits.address
invalidate tlIn.c.bits.source
invalidate tlIn.c.bits.size
invalidate tlIn.c.bits.param
invalidate tlIn.c.bits.opcode
invalidate tlIn.c.valid
invalidate tlIn.c.ready
invalidate tlIn.b.bits.corrupt
invalidate tlIn.b.bits.data
invalidate tlIn.b.bits.mask
invalidate tlIn.b.bits.address
invalidate tlIn.b.bits.source
invalidate tlIn.b.bits.size
invalidate tlIn.b.bits.param
invalidate tlIn.b.bits.opcode
invalidate tlIn.b.valid
invalidate tlIn.b.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect tlIn.e.bits, buffer.auto.out.e.bits
connect tlIn.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, tlIn.e.ready
connect buffer.auto.out.d, tlIn.d
connect tlIn.c.bits, buffer.auto.out.c.bits
connect tlIn.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, tlIn.c.ready
connect buffer.auto.out.b, tlIn.b
connect tlIn.a.bits, buffer.auto.out.a.bits
connect tlIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, tlIn.a.ready
connect auto.tl_out, tlOut
connect buffer.auto.in, auto.buffer_in | module TLInterconnectCoupler_sbus_from_port_named_rerocc_0( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_buffer_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_buffer_in_a_valid_0 = auto_buffer_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_opcode_0 = auto_buffer_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_param_0 = auto_buffer_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_size_0 = auto_buffer_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_bits_source_0 = auto_buffer_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_buffer_in_a_bits_address_0 = auto_buffer_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_buffer_in_a_bits_mask_0 = auto_buffer_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_a_bits_data_0 = auto_buffer_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_bits_corrupt_0 = auto_buffer_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_b_ready_0 = auto_buffer_in_b_ready; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_c_valid_0 = auto_buffer_in_c_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_c_bits_opcode_0 = auto_buffer_in_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_c_bits_param_0 = auto_buffer_in_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_c_bits_size_0 = auto_buffer_in_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_c_bits_source_0 = auto_buffer_in_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_buffer_in_c_bits_address_0 = auto_buffer_in_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_c_bits_data_0 = auto_buffer_in_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_c_bits_corrupt_0 = auto_buffer_in_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_ready_0 = auto_buffer_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_e_valid_0 = auto_buffer_in_e_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_e_bits_sink_0 = auto_buffer_in_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_b_valid_0 = auto_tl_out_b_valid; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_out_b_bits_param_0 = auto_tl_out_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_b_bits_source_0 = auto_tl_out_b_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_b_bits_address_0 = auto_tl_out_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_c_ready_0 = auto_tl_out_c_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_out_d_bits_param_0 = auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_sink_0 = auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_e_ready_0 = auto_tl_out_e_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:75:28]
wire tlOut_b_bits_corrupt = 1'h0; // @[Buffer.scala:75:28]
wire tlIn_b_bits_corrupt = 1'h0; // @[Buffer.scala:75:28]
wire [63:0] auto_tl_out_b_bits_data = 64'h0; // @[Buffer.scala:75:28]
wire [63:0] tlOut_b_bits_data = 64'h0; // @[Buffer.scala:75:28]
wire [63:0] tlIn_b_bits_data = 64'h0; // @[Buffer.scala:75:28]
wire [7:0] auto_tl_out_b_bits_mask = 8'hFF; // @[Buffer.scala:75:28]
wire [7:0] tlOut_b_bits_mask = 8'hFF; // @[Buffer.scala:75:28]
wire [7:0] tlIn_b_bits_mask = 8'hFF; // @[Buffer.scala:75:28]
wire [3:0] auto_tl_out_b_bits_size = 4'h6; // @[Buffer.scala:75:28]
wire [3:0] tlOut_b_bits_size = 4'h6; // @[Buffer.scala:75:28]
wire [3:0] tlIn_b_bits_size = 4'h6; // @[Buffer.scala:75:28]
wire [2:0] auto_tl_out_b_bits_opcode = 3'h6; // @[Buffer.scala:75:28]
wire [2:0] tlOut_b_bits_opcode = 3'h6; // @[Buffer.scala:75:28]
wire [2:0] tlIn_b_bits_opcode = 3'h6; // @[Buffer.scala:75:28]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_b_ready; // @[MixedNode.scala:542:17]
wire tlOut_b_valid = auto_tl_out_b_valid_0; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_b_bits_param = auto_tl_out_b_bits_param_0; // @[MixedNode.scala:542:17]
wire tlOut_b_bits_source = auto_tl_out_b_bits_source_0; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_b_bits_address = auto_tl_out_b_bits_address_0; // @[MixedNode.scala:542:17]
wire tlOut_c_ready = auto_tl_out_c_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param = auto_tl_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_sink = auto_tl_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire tlOut_e_ready = auto_tl_out_e_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_b_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_buffer_in_b_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_b_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_b_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_buffer_in_b_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_buffer_in_b_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_b_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_b_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_b_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_c_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_e_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_c_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_c_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_c_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_c_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_c_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_c_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_c_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_c_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_e_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_e_valid_0; // @[LazyModuleImp.scala:138:7]
wire tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_b_ready_0 = tlOut_b_ready; // @[MixedNode.scala:542:17]
wire tlIn_b_valid = tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlIn_b_bits_param = tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_b_bits_source = tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlIn_b_bits_address = tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_c_ready = tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_valid_0 = tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_opcode_0 = tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_param_0 = tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_size_0 = tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_source_0 = tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_address_0 = tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_data_0 = tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_c_bits_corrupt_0 = tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_e_ready = tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_e_valid_0 = tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_out_e_bits_sink_0 = tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_b_ready = tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_valid = tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_opcode = tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_param = tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_size = tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_source = tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_address = tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_data = tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_c_bits_corrupt = tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_e_valid = tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_e_bits_sink = tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
TLBuffer_a32d64s1k3z4c buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready_0),
.auto_in_a_valid (auto_buffer_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_param (auto_buffer_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_size (auto_buffer_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_source (auto_buffer_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_address (auto_buffer_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_data (auto_buffer_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_in_b_ready (auto_buffer_in_b_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_in_b_valid (auto_buffer_in_b_valid_0),
.auto_in_b_bits_opcode (auto_buffer_in_b_bits_opcode_0),
.auto_in_b_bits_param (auto_buffer_in_b_bits_param_0),
.auto_in_b_bits_size (auto_buffer_in_b_bits_size_0),
.auto_in_b_bits_source (auto_buffer_in_b_bits_source_0),
.auto_in_b_bits_address (auto_buffer_in_b_bits_address_0),
.auto_in_b_bits_mask (auto_buffer_in_b_bits_mask_0),
.auto_in_b_bits_data (auto_buffer_in_b_bits_data_0),
.auto_in_b_bits_corrupt (auto_buffer_in_b_bits_corrupt_0),
.auto_in_c_ready (auto_buffer_in_c_ready_0),
.auto_in_c_valid (auto_buffer_in_c_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_opcode (auto_buffer_in_c_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_param (auto_buffer_in_c_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_size (auto_buffer_in_c_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_source (auto_buffer_in_c_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_address (auto_buffer_in_c_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_data (auto_buffer_in_c_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_in_c_bits_corrupt (auto_buffer_in_c_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_ready (auto_buffer_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_valid (auto_buffer_in_d_valid_0),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode_0),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param_0),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size_0),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source_0),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink_0),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied_0),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data_0),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt_0),
.auto_in_e_ready (auto_buffer_in_e_ready_0),
.auto_in_e_valid (auto_buffer_in_e_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_e_bits_sink (auto_buffer_in_e_bits_sink_0), // @[LazyModuleImp.scala:138:7]
.auto_out_a_ready (tlIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlIn_a_valid),
.auto_out_a_bits_opcode (tlIn_a_bits_opcode),
.auto_out_a_bits_param (tlIn_a_bits_param),
.auto_out_a_bits_size (tlIn_a_bits_size),
.auto_out_a_bits_source (tlIn_a_bits_source),
.auto_out_a_bits_address (tlIn_a_bits_address),
.auto_out_a_bits_mask (tlIn_a_bits_mask),
.auto_out_a_bits_data (tlIn_a_bits_data),
.auto_out_a_bits_corrupt (tlIn_a_bits_corrupt),
.auto_out_b_ready (tlIn_b_ready),
.auto_out_b_valid (tlIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_source (tlIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlIn_c_valid),
.auto_out_c_bits_opcode (tlIn_c_bits_opcode),
.auto_out_c_bits_param (tlIn_c_bits_param),
.auto_out_c_bits_size (tlIn_c_bits_size),
.auto_out_c_bits_source (tlIn_c_bits_source),
.auto_out_c_bits_address (tlIn_c_bits_address),
.auto_out_c_bits_data (tlIn_c_bits_data),
.auto_out_c_bits_corrupt (tlIn_c_bits_corrupt),
.auto_out_d_ready (tlIn_d_ready),
.auto_out_d_valid (tlIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_ready (tlIn_e_ready), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlIn_e_valid),
.auto_out_e_bits_sink (tlIn_e_bits_sink)
); // @[Buffer.scala:75:28]
assign auto_buffer_in_a_ready = auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_valid = auto_buffer_in_b_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_opcode = auto_buffer_in_b_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_param = auto_buffer_in_b_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_size = auto_buffer_in_b_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_source = auto_buffer_in_b_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_address = auto_buffer_in_b_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_mask = auto_buffer_in_b_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_data = auto_buffer_in_b_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_b_bits_corrupt = auto_buffer_in_b_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_c_ready = auto_buffer_in_c_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_valid = auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_opcode = auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_param = auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_size = auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_source = auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_sink = auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_denied = auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_data = auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_corrupt = auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_e_ready = auto_buffer_in_e_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_b_ready = auto_tl_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_valid = auto_tl_out_c_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_opcode = auto_tl_out_c_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_param = auto_tl_out_c_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_size = auto_tl_out_c_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_source = auto_tl_out_c_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_address = auto_tl_out_c_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_data = auto_tl_out_c_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_c_bits_corrupt = auto_tl_out_c_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_e_valid = auto_tl_out_e_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_e_bits_sink = auto_tl_out_e_bits_sink_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_348 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_348( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8_5 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}}, count : UInt<1>}
cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}} [1]
wire enq_ptr_value : UInt
connect enq_ptr_value, UInt<1>(0h0)
wire deq_ptr_value : UInt
connect deq_ptr_value, UInt<1>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _empty_T = eq(maybe_full, UInt<1>(0h0))
node empty = and(ptr_match, _empty_T)
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = and(io.deq.ready, io.deq.valid)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T
when do_enq :
wire _WIRE : UInt
connect _WIRE, UInt<1>(0h0)
infer mport MPORT = ram[_WIRE], clock
connect MPORT.extra, io.enq.bits.extra
connect MPORT.mask, io.enq.bits.mask
connect MPORT.data, io.enq.bits.data
connect MPORT.index, io.enq.bits.index
connect MPORT.read, io.enq.bits.read
when do_deq :
skip
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
when UInt<1>(0h0) :
connect enq_ptr_value, UInt<1>(0h0)
connect deq_ptr_value, UInt<1>(0h0)
connect maybe_full, UInt<1>(0h0)
node _io_deq_valid_T = eq(empty, UInt<1>(0h0))
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire _io_deq_bits_WIRE : UInt
connect _io_deq_bits_WIRE, UInt<1>(0h0)
infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock
connect io.deq.bits, io_deq_bits_MPORT
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0))
node _io_count_T_2 = or(_io_count_T_1, ptr_diff)
connect io.count, _io_count_T_2 | module Queue1_RegMapperInput_i9_m8_5( // @[RegMapper.scala:71:32]
input clock, // @[RegMapper.scala:71:32]
input reset, // @[RegMapper.scala:71:32]
output io_enq_ready, // @[Decoupled.scala:255:14]
input io_enq_valid, // @[Decoupled.scala:255:14]
input io_enq_bits_read, // @[Decoupled.scala:255:14]
input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14]
input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14]
input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14]
input [6:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
input [2:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14]
input io_deq_ready, // @[Decoupled.scala:255:14]
output io_deq_valid, // @[Decoupled.scala:255:14]
output io_deq_bits_read, // @[Decoupled.scala:255:14]
output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14]
output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14]
output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14]
output [6:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
output [2:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32]
wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32]
wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32]
wire [6:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32]
wire [2:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32]
wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32]
wire ptr_match = 1'h1; // @[Decoupled.scala:260:33]
wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32]
wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23]
wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32]
wire _io_deq_valid_T; // @[Decoupled.scala:285:19]
wire _io_count_T_2; // @[Decoupled.scala:312:62]
wire io_enq_ready_0; // @[RegMapper.scala:71:32]
wire [6:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
wire [2:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
wire io_deq_bits_read_0; // @[RegMapper.scala:71:32]
wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32]
wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32]
wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
wire io_deq_valid_0; // @[RegMapper.scala:71:32]
wire io_count; // @[RegMapper.scala:71:32]
reg [91:0] ram; // @[Decoupled.scala:256:91]
assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91]
assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91]
assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91]
assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_source_0 = ram[88:82]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_size_0 = ram[91:89]; // @[Decoupled.scala:256:91]
reg maybe_full; // @[Decoupled.scala:259:27]
wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24]
wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32]
wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28]
wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27]
wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27]
assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19]
assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}]
assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}]
assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62]
always @(posedge clock) begin // @[RegMapper.scala:71:32]
if (do_enq) // @[Decoupled.scala:263:27]
ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91]
if (reset) // @[RegMapper.scala:71:32]
maybe_full <= 1'h0; // @[Decoupled.scala:259:27]
else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16]
maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27]
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32]
assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_6 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_6( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_82
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_83
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_28( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PLICFanIn_9 :
input clock : Clock
input reset : Reset
output io : { flip prio : UInt<1>[1], flip ip : UInt<1>, dev : UInt<1>, max : UInt<1>}
node effectivePriority_0 = shl(UInt<1>(0h1), 1)
node _effectivePriority_T = bits(io.ip, 0, 0)
node effectivePriority_1 = cat(_effectivePriority_T, io.prio[0])
node _T = geq(effectivePriority_0, effectivePriority_1)
node _T_1 = or(UInt<1>(0h1), UInt<1>(0h0))
node maxPri = mux(_T, effectivePriority_0, effectivePriority_1)
node maxDev = mux(_T, UInt<1>(0h0), _T_1)
connect io.max, maxPri
connect io.dev, maxDev | module PLICFanIn_9( // @[Plic.scala:338:7]
input clock, // @[Plic.scala:338:7]
input reset, // @[Plic.scala:338:7]
input io_prio_0, // @[Plic.scala:339:14]
input io_ip, // @[Plic.scala:339:14]
output io_dev, // @[Plic.scala:339:14]
output io_max // @[Plic.scala:339:14]
);
wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7]
wire io_ip_0 = io_ip; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32]
wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55]
wire maxDev; // @[Misc.scala:35:36]
wire io_dev_0; // @[Plic.scala:338:7]
wire io_max_0; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}]
wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9]
assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36]
assign io_dev_0 = maxDev; // @[Misc.scala:35:36]
assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9]
assign io_dev = io_dev_0; // @[Plic.scala:338:7]
assign io_max = io_max_0; // @[Plic.scala:338:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_197 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_453
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_197( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_453 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater :
input clock : Clock
input reset : Reset
output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}}
wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clock_gaterOut.member.allClocks_uncore.reset
invalidate clock_gaterOut.member.allClocks_uncore.clock
wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clock_gaterIn.member.allClocks_uncore.reset
invalidate clock_gaterIn.member.allClocks_uncore.clock
connect clock_gaterOut, clock_gaterIn
wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate clock_gaterIn_1.d.bits.corrupt
invalidate clock_gaterIn_1.d.bits.data
invalidate clock_gaterIn_1.d.bits.denied
invalidate clock_gaterIn_1.d.bits.sink
invalidate clock_gaterIn_1.d.bits.source
invalidate clock_gaterIn_1.d.bits.size
invalidate clock_gaterIn_1.d.bits.param
invalidate clock_gaterIn_1.d.bits.opcode
invalidate clock_gaterIn_1.d.valid
invalidate clock_gaterIn_1.d.ready
invalidate clock_gaterIn_1.a.bits.corrupt
invalidate clock_gaterIn_1.a.bits.data
invalidate clock_gaterIn_1.a.bits.mask
invalidate clock_gaterIn_1.a.bits.address
invalidate clock_gaterIn_1.a.bits.source
invalidate clock_gaterIn_1.a.bits.size
invalidate clock_gaterIn_1.a.bits.param
invalidate clock_gaterIn_1.a.bits.opcode
invalidate clock_gaterIn_1.a.valid
invalidate clock_gaterIn_1.a.ready
inst monitor of TLMonitor_63
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt
connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data
connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied
connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink
connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source
connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size
connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param
connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode
connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid
connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready
connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt
connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data
connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask
connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address
connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source
connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size
connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param
connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode
connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid
connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready
connect auto.clock_gater_out, clock_gaterOut
connect clock_gaterIn, auto.clock_gater_in_0
connect clock_gaterIn_1, auto.clock_gater_in_1
inst regs_0 of AsyncResetRegVec_w1_i1
connect regs_0.clock, clock
connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset
connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, clock_gaterIn_1.a.bits.data
connect in.bits.mask, clock_gaterIn_1.a.bits.mask
connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source
connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h0))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[1]
wire out_wivalid : UInt<1>[1]
wire out_roready : UInt<1>[1]
wire out_woready : UInt<1>[1]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_2 = bits(out_front.bits.data, 0, 0)
connect regs_0.io.en, out_f_woready
connect regs_0.io.d, _out_T_2
node _out_T_3 = eq(out_rimask, UInt<1>(0h0))
node _out_T_4 = eq(out_wimask, UInt<1>(0h0))
node _out_T_5 = eq(out_romask, UInt<1>(0h0))
node _out_T_6 = eq(out_womask, UInt<1>(0h0))
node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0))
node _out_T_8 = bits(_out_T_7, 0, 0)
node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rifireMux_WIRE : UInt<1>[1]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wifireMux_WIRE : UInt<1>[1]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rofireMux_WIRE : UInt<1>[1]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wofireMux_WIRE : UInt<1>[1]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE : UInt<1>[1]
connect _out_out_bits_data_WIRE[0], _out_T_1
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0])
node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE_1 : UInt<1>[1]
connect _out_out_bits_data_WIRE_1[0], _out_T_8
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, clock_gaterIn_1.a.valid
connect clock_gaterIn_1.a.ready, in.ready
connect clock_gaterIn_1.d.valid, out.valid
connect out.ready, clock_gaterIn_1.d.ready
wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0)
invalidate clock_gaterIn_d_bits_d.data
connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0)
connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt
connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data
connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied
connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink
connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source
connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size
connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param
connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode
connect clock_gaterIn_1.d.bits.data, out.bits.data
node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
extmodule plusarg_reader_131 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_132 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TileClockGater( // @[TileClockGater.scala:27:25]
input clock, // @[TileClockGater.scala:27:25]
input reset, // @[TileClockGater.scala:27:25]
output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25]
wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25]
wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25]
wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25]
wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25]
wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25]
wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25]
wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25]
wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25]
wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17]
wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17]
wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25]
wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25]
wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25]
wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25]
wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25]
wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17]
wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17]
assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10]
assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24]
assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17]
assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17]
assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
TLMonitor_63 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53]
.clock (clock),
.reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17]
.io_d (_out_T_2), // @[RegisterRouter.scala:87:24]
.io_q (_out_T_7),
.io_en (out_f_woready) // @[RegisterRouter.scala:87:24]
); // @[TileClockGater.scala:33:53]
assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_6ClockSinkDomain :
output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<74>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<74>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_19
connect routers.clock, childClock
connect routers.reset, childReset
inst ingress_width_widget of IngressWidthWidget_6
connect ingress_width_widget.clock, childClock
connect ingress_width_widget.reset, childReset
inst egress_width_widget of EgressWidthWidget_6
connect egress_width_widget.clock, childClock
connect egress_width_widget.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect egress_width_widget.auto.in, routers.auto.egress_nodes_out
connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect ingress_width_widget.auto.in, auto.ingress_width_widget_in
connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits
connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid
connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLSplitACDxBENoC_be_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_egress_width_widget_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [73:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [73:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43]
wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44]
wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44]
wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44]
wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44]
wire [3:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44]
wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22]
wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22]
wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22]
wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22]
wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22]
Router_19 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43]
.auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid),
.auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head),
.auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail),
.auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload),
.auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready),
.auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44]
.auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44]
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready),
.auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid),
.auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head),
.auto_in_flit_bits_tail (1'h1), // @[LazyModuleImp.scala:107:25]
.auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload),
.auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id),
.auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22]
.auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid),
.auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head),
.auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail),
.auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload),
.auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id)
); // @[WidthWidget.scala:88:44]
EgressWidthWidget egress_width_widget ( // @[WidthWidget.scala:111:43]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready),
.auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22]
.auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22]
.auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22]
.auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22]
.auto_out_flit_ready (auto_egress_width_widget_out_flit_ready),
.auto_out_flit_valid (auto_egress_width_widget_out_flit_valid),
.auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head),
.auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail),
.auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload)
); // @[WidthWidget.scala:111:43]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[12]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2])
node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3])
node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4])
node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5])
node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6])
node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7])
node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8])
node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9])
node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10])
node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000)))
node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19)
node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22)
node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24)
node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26)
node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30
node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_31
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14)
node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19)
node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24)
node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29)
node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34)
node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_42 = cvt(_io_resp_w_T_41)
node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43)
node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_48
node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_49
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14)
node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19)
node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24)
node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29)
node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34)
node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41)
node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43)
node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_48
node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_49
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14)
node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19)
node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24)
node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29)
node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34)
node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_42 = cvt(_io_resp_al_T_41)
node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43)
node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_48
node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_49
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14)
node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19)
node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24)
node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29)
node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34)
node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41)
node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43)
node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_48
node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_49
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43)
node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48)
node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53)
node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58)
node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_66
node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_67
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14)
node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19)
node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24)
node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29)
node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35)
node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37)
node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40)
node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42)
node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45)
node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47)
node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50)
node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000)))
node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52)
node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44)
node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49)
node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54)
node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_60
node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_61 | module PMAChecker( // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [8:0] _GEN = io_paddr[20:12] ^ 9'h100; // @[Parameters.scala:137:31]
wire [9:0] _GEN_0 = io_paddr[25:16] ^ 10'h200; // @[Parameters.scala:137:31]
wire [13:0] _GEN_1 = io_paddr[25:12] ^ 14'h2010; // @[Parameters.scala:137:31]
wire [11:0] _GEN_2 = io_paddr[27:16] ^ 12'h800; // @[Parameters.scala:137:31]
wire [3:0] _GEN_3 = io_paddr[31:28] ^ 4'h8; // @[Parameters.scala:137:31]
wire legal_address = io_paddr[39:12] == 28'h0 | {io_paddr[39:13], ~(io_paddr[12])} == 28'h0 | {io_paddr[39:14], ~(io_paddr[13:12])} == 28'h0 | {io_paddr[39:17], ~(io_paddr[16])} == 24'h0 | {io_paddr[39:21], _GEN} == 28'h0 | {io_paddr[39:21], io_paddr[20:12] ^ 9'h110} == 28'h0 | {io_paddr[39:26], _GEN_0} == 24'h0 | {io_paddr[39:26], _GEN_1} == 28'h0 | {io_paddr[39:28], _GEN_2} == 24'h0 | {io_paddr[39:28], ~(io_paddr[27:26])} == 14'h0 | {io_paddr[39:29], io_paddr[28:12] ^ 17'h10020} == 28'h0 | {io_paddr[39:32], _GEN_3} == 12'h0; // @[PMA.scala:19:14, :36:58]
wire [4:0] _GEN_4 = {io_paddr[31], io_paddr[28:27], io_paddr[20], io_paddr[16]}; // @[Parameters.scala:137:{31,41,46}]
wire [5:0] _GEN_5 = {io_paddr[31], io_paddr[28:27], io_paddr[25], _GEN[8], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}]
wire [6:0] _GEN_6 = {io_paddr[31], io_paddr[28:27], _GEN_1[13], io_paddr[20], _GEN_1[4], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}]
wire [2:0] _GEN_7 = {io_paddr[31], io_paddr[28], _GEN_2[11]}; // @[Parameters.scala:137:{31,41,46}]
wire [5:0] _GEN_8 = {io_paddr[31], io_paddr[28], _GEN_2[11], io_paddr[25], io_paddr[20], io_paddr[16]}; // @[Parameters.scala:137:{31,41,46}]
wire [3:0] _GEN_9 = io_paddr[28:25] ^ 4'h8; // @[Parameters.scala:137:31]
wire [6:0] _GEN_10 = {io_paddr[31], _GEN_9[3:2], io_paddr[25], io_paddr[20], io_paddr[16], io_paddr[12]}; // @[Parameters.scala:137:{31,41,46}]
wire [1:0] _GEN_11 = {_GEN_3[3], io_paddr[28]}; // @[Parameters.scala:137:{31,41,46}]
assign io_resp_cacheable = legal_address & ({io_paddr[31], _GEN_2[11:10], io_paddr[16]} == 4'h0 | ~(_GEN_3[3])); // @[Parameters.scala:629:89]
assign io_resp_r = legal_address; // @[PMA.scala:18:7, :36:58]
assign io_resp_w = legal_address & (~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_10) | ~(|_GEN_11)); // @[Parameters.scala:629:89]
assign io_resp_pp = legal_address & (~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_10) | ~(|_GEN_11)); // @[Parameters.scala:629:89]
assign io_resp_al = legal_address & (~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_10) | ~(|_GEN_11)); // @[Parameters.scala:629:89]
assign io_resp_aa = legal_address & (~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8) | ~(|_GEN_10) | ~(|_GEN_11)); // @[Parameters.scala:629:89]
assign io_resp_x = legal_address & ({io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], io_paddr[13:12]} == 9'h0 | {io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], ~(io_paddr[13:12])} == 9'h0 | {io_paddr[31], io_paddr[28:25], io_paddr[20], ~(io_paddr[16])} == 7'h0 | {io_paddr[31], io_paddr[28], _GEN_2[11:9], io_paddr[20], io_paddr[16]} == 7'h0 | ~(|_GEN_11)); // @[Parameters.scala:629:89]
assign io_resp_eff = legal_address & ({io_paddr[31], io_paddr[28:25], io_paddr[20], io_paddr[16], io_paddr[13]} == 8'h0 | {io_paddr[31], io_paddr[28:25], _GEN[8], io_paddr[13:12]} == 8'h0 | {io_paddr[31], io_paddr[28:26], _GEN_0[9], io_paddr[20], io_paddr[16]} == 7'h0 | {io_paddr[31], io_paddr[28:26], _GEN_1[13], io_paddr[20], _GEN_1[4], io_paddr[13:12]} == 9'h0 | {io_paddr[31], io_paddr[28], ~(io_paddr[27:26])} == 4'h0 | {io_paddr[31], _GEN_9, io_paddr[20], io_paddr[16], io_paddr[13:12]} == 9'h0); // @[Parameters.scala:629:89]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRawFN_small_e5_s11_6 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}}
regreset cycleNum : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1)
regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0)
reg sqrtOp_Z : UInt<1>, clock
reg majorExc_Z : UInt<1>, clock
reg isNaN_Z : UInt<1>, clock
reg isInf_Z : UInt<1>, clock
reg isZero_Z : UInt<1>, clock
reg sign_Z : UInt<1>, clock
reg sExp_Z : SInt<7>, clock
reg fractB_Z : UInt<11>, clock
reg roundingMode_Z : UInt<3>, clock
reg rem_Z : UInt<13>, clock
reg notZeroRem_Z : UInt<1>, clock
reg sigX_Z : UInt<13>, clock
node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero)
node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf)
node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1)
node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0))
node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0))
node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1)
node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign)
node _majorExc_S_T = bits(io.a.sig, 9, 9)
node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0))
node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1)
node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt)
node _majorExc_S_T_4 = bits(io.a.sig, 9, 9)
node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0))
node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5)
node _majorExc_S_T_7 = bits(io.b.sig, 9, 9)
node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0))
node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8)
node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9)
node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div)
node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0))
node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0))
node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13)
node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero)
node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15)
node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16)
node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt)
node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN)
node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div)
node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2)
node _isInf_S_T = or(io.a.isInf, io.b.isZero)
node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T)
node _isZero_S_T = or(io.a.isZero, io.b.isInf)
node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T)
node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0))
node _sign_S_T_1 = and(_sign_S_T, io.b.sign)
node sign_S = xor(io.a.sign, _sign_S_T_1)
node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf)
node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero)
node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf)
node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero)
node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0))
node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0))
node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1)
node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0))
node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0))
node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1)
node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
node _sExpQuot_S_div_T = bits(io.b.sExp, 5, 5)
node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 4, 0)
node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1)
node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2)
node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3)
node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4)
node _sSatExpQuot_S_div_T = leq(asSInt(UInt<7>(0h38)), sExpQuot_S_div)
node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 6, 3)
node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1)
node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 2, 0)
node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3)
node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4)
node _evenSqrt_S_T = bits(io.a.sExp, 0, 0)
node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0))
node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1)
node _oddSqrt_S_T = bits(io.a.sExp, 0, 0)
node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T)
node idle = eq(cycleNum, UInt<1>(0h0))
node entering = and(inReady, io.inValid)
node entering_normalCase = and(entering, normalCase_S)
node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3))
node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0))
node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3))
node _skipCycle2_T_1 = bits(sigX_Z, 12, 12)
node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1)
node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1))
node _T = eq(idle, UInt<1>(0h0))
node _T_1 = or(_T, entering)
when _T_1 :
node _inReady_T = eq(normalCase_S, UInt<1>(0h0))
node _inReady_T_1 = and(entering, _inReady_T)
node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1))
node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0))
node _inReady_T_4 = bits(io.a.sExp, 0, 0)
node _inReady_T_5 = leq(UInt<4>(0hb), UInt<1>(0h1))
node _inReady_T_6 = leq(UInt<4>(0hc), UInt<1>(0h1))
node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6)
node _inReady_T_8 = leq(UInt<4>(0hd), UInt<1>(0h1))
node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8)
node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0))
node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10)
node _inReady_T_12 = eq(entering, UInt<1>(0h0))
node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0))
node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13)
node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _inReady_T_16 = sub(cycleNum, _inReady_T_15)
node _inReady_T_17 = tail(_inReady_T_16, 1)
node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1))
node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0))
node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19)
node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1))
node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0))
node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22)
node _inReady_T_24 = bits(_inReady_T_23, 0, 0)
connect inReady, _inReady_T_24
node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0))
node _rawOutValid_T_1 = and(entering, _rawOutValid_T)
node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0))
node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0)
node _rawOutValid_T_5 = eq(UInt<4>(0hb), UInt<1>(0h1))
node _rawOutValid_T_6 = eq(UInt<4>(0hc), UInt<1>(0h1))
node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6)
node _rawOutValid_T_8 = eq(UInt<4>(0hd), UInt<1>(0h1))
node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8)
node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0))
node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10)
node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0))
node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0))
node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13)
node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15)
node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1)
node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1))
node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0))
node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19)
node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0))
node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22)
node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0)
connect rawOutValid, _rawOutValid_T_24
node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0))
node _cycleNum_T_1 = and(entering, _cycleNum_T)
node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _cycleNum_T_3 = bits(io.a.sExp, 0, 0)
node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<4>(0hb), UInt<4>(0hc))
node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<4>(0hd))
node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0))
node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6)
node _cycleNum_T_8 = eq(entering, UInt<1>(0h0))
node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0))
node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9)
node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11)
node _cycleNum_T_13 = tail(_cycleNum_T_12, 1)
node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0))
node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14)
node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0))
node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16)
connect cycleNum, _cycleNum_T_17
connect io.inReady, inReady
when entering :
connect sqrtOp_Z, io.sqrtOp
connect majorExc_Z, majorExc_S
connect isNaN_Z, isNaN_S
connect isInf_Z, isInf_S
connect isZero_Z, isZero_S
connect sign_Z, sign_S
node _sExp_Z_T = shr(io.a.sExp, 1)
node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<6>(0h10)))
node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div)
connect sExp_Z, _sExp_Z_T_2
connect roundingMode_Z, io.roundingMode
node _T_2 = eq(inReady, UInt<1>(0h0))
node _T_3 = and(_T_2, sqrtOp_Z)
node _T_4 = or(entering, _T_3)
when _T_4 :
node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0))
node _fractB_Z_T_1 = and(inReady, _fractB_Z_T)
node _fractB_Z_T_2 = bits(io.b.sig, 9, 0)
node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1)
node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0))
node _fractB_Z_T_5 = and(inReady, io.sqrtOp)
node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0)
node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6)
node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<10>(0h200), UInt<1>(0h0))
node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8)
node _fractB_Z_T_10 = and(inReady, io.sqrtOp)
node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0)
node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0))
node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12)
node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<11>(0h400), UInt<1>(0h0))
node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14)
node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0))
node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits)
node _fractB_Z_T_18 = shr(fractB_Z, 2)
node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0))
node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19)
node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0))
node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0))
node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22)
node _fractB_Z_T_24 = shr(fractB_Z, 1)
node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0))
node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25)
connect fractB_Z, _fractB_Z_T_26
node _rem_T = eq(oddSqrt_S, UInt<1>(0h0))
node _rem_T_1 = and(inReady, _rem_T)
node _rem_T_2 = shl(io.a.sig, 1)
node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0))
node _rem_T_4 = and(inReady, oddSqrt_S)
node _rem_T_5 = bits(io.a.sig, 10, 9)
node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1))
node _rem_T_7 = tail(_rem_T_6, 1)
node _rem_T_8 = bits(io.a.sig, 8, 0)
node _rem_T_9 = shl(_rem_T_8, 3)
node _rem_T_10 = cat(_rem_T_7, _rem_T_9)
node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0))
node _rem_T_12 = or(_rem_T_3, _rem_T_11)
node _rem_T_13 = eq(inReady, UInt<1>(0h0))
node _rem_T_14 = shl(rem_Z, 1)
node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0))
node rem = or(_rem_T_12, _rem_T_15)
node _bitMask_T = dshl(UInt<1>(0h1), cycleNum)
node bitMask = shr(_bitMask_T, 2)
node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0))
node _trialTerm_T_1 = and(inReady, _trialTerm_T)
node _trialTerm_T_2 = shl(io.b.sig, 1)
node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0))
node _trialTerm_T_4 = and(inReady, evenSqrt_S)
node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<12>(0h800), UInt<1>(0h0))
node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5)
node _trialTerm_T_7 = and(inReady, oddSqrt_S)
node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<13>(0h1400), UInt<1>(0h0))
node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8)
node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0))
node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11)
node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0))
node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14)
node _trialTerm_T_16 = shl(UInt<1>(0h1), 11)
node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0))
node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17)
node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z)
node _trialTerm_T_21 = shl(sigX_Z, 1)
node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0))
node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22)
node _trialRem_T = cvt(rem)
node _trialRem_T_1 = cvt(trialTerm)
node trialRem = sub(_trialRem_T, _trialRem_T_1)
node newBit = leq(asSInt(UInt<1>(0h0)), trialRem)
node _nextRem_Z_T = asUInt(trialRem)
node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem)
node nextRem_Z = bits(_nextRem_Z_T_1, 12, 0)
node rem2 = shl(nextRem_Z, 1)
node _trialTerm2_newBit0_T = shr(fractB_Z, 1)
node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1)
node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1)
node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 11)
node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3)
node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4)
node _trialTerm2_newBit1_T = shl(fractB_Z, 1)
node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0))
node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1)
node _trialRem2_T = shl(trialRem, 1)
node _trialRem2_T_1 = cvt(trialTerm2_newBit1)
node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1)
node _trialRem2_T_3 = tail(_trialRem2_T_2, 1)
node _trialRem2_T_4 = asSInt(_trialRem2_T_3)
node _trialRem2_T_5 = shl(rem_Z, 2)
node _trialRem2_T_6 = bits(_trialRem2_T_5, 13, 0)
node _trialRem2_T_7 = cvt(_trialRem2_T_6)
node _trialRem2_T_8 = cvt(trialTerm2_newBit0)
node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8)
node _trialRem2_T_10 = tail(_trialRem2_T_9, 1)
node _trialRem2_T_11 = asSInt(_trialRem2_T_10)
node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11)
node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2)
node _nextNotZeroRem_Z_T = or(inReady, newBit)
node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0)))
node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z)
node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit)
node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1)
node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1)
node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2)
node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1)
node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4)
node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5)
node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6)
node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0))
node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8)
node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2)
node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 13, 0)
node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11)
node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0)
node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13)
node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1)
node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15)
node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16)
node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17)
node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18)
node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2)
node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0))
node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z)
node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22)
node _nextRem_Z_2_T = and(processTwoBits, newBit2)
node _nextRem_Z_2_T_1 = asUInt(trialRem2)
node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 12, 0)
node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0))
node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0))
node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4)
node _nextRem_Z_2_T_6 = bits(rem2, 12, 0)
node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0))
node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7)
node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0))
node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0))
node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10)
node _T_5 = eq(inReady, UInt<1>(0h0))
node _T_6 = or(entering, _T_5)
when _T_6 :
connect notZeroRem_Z, nextNotZeroRem_Z_2
connect rem_Z, nextRem_Z_2
node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0))
node _sigX_Z_T_1 = and(inReady, _sigX_Z_T)
node _sigX_Z_T_2 = shl(newBit, 12)
node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0))
node _sigX_Z_T_4 = and(inReady, io.sqrtOp)
node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<12>(0h800), UInt<1>(0h0))
node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5)
node _sigX_Z_T_7 = and(inReady, oddSqrt_S)
node _sigX_Z_T_8 = shl(newBit, 10)
node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0))
node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9)
node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0))
node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0))
node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12)
node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0))
node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit)
node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0))
node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16)
node _sigX_Z_T_18 = and(processTwoBits, newBit2)
node _sigX_Z_T_19 = shr(bitMask, 1)
node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0))
node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20)
connect sigX_Z, _sigX_Z_T_21
node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0))
node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T)
connect io.rawOutValid_div, _io_rawOutValid_div_T_1
node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z)
connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T
connect io.roundingModeOut, roundingMode_Z
node _io_invalidExc_T = and(majorExc_Z, isNaN_Z)
connect io.invalidExc, _io_invalidExc_T
node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0))
node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T)
connect io.infiniteExc, _io_infiniteExc_T_1
connect io.rawOut.isNaN, isNaN_Z
connect io.rawOut.isInf, isInf_Z
connect io.rawOut.isZero, isZero_Z
connect io.rawOut.sign, sign_Z
connect io.rawOut.sExp, sExp_Z
node _io_rawOut_sig_T = shl(sigX_Z, 1)
node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z)
connect io.rawOut.sig, _io_rawOut_sig_T_1 | module DivSqrtRawFN_small_e5_s11_6( // @[DivSqrtRecFN_small.scala:199:5]
input clock, // @[DivSqrtRecFN_small.scala:199:5]
input reset, // @[DivSqrtRecFN_small.scala:199:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:203:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:203:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16]
output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16]
output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [11:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [11:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5]
wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [8:0] _fractB_Z_T_19 = 9'h0; // @[DivSqrtRecFN_small.scala:345:16]
wire [11:0] _trialTerm_T_16 = 12'h800; // @[DivSqrtRecFN_small.scala:366:42]
wire [11:0] _trialTerm2_newBit0_T_3 = 12'h800; // @[DivSqrtRecFN_small.scala:373:85]
wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45]
wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9]
wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13]
wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42]
wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42]
wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24]
wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34]
wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24]
wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35]
wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85]
wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26]
wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28]
wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28]
wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32]
wire [12:0] _nextRem_Z_2_T_3 = 13'h0; // @[DivSqrtRecFN_small.scala:386:12]
wire [12:0] _nextRem_Z_2_T_7 = 13'h0; // @[DivSqrtRecFN_small.scala:387:12]
wire [12:0] _nextRem_Z_2_T_8 = 13'h0; // @[DivSqrtRecFN_small.scala:386:81]
wire [12:0] _sigX_Z_T_20 = 13'h0; // @[DivSqrtRecFN_small.scala:399:16]
wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40]
wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40]
wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36]
wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36]
wire [13:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
reg [3:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33]
reg inReady; // @[DivSqrtRecFN_small.scala:225:33]
assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33]
reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33]
reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29]
reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29]
reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29]
assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29]
reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29]
assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29]
reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29]
assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29]
reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29]
assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29]
reg [6:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29]
assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29]
reg [10:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29]
reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29]
assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
reg [12:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29]
reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29]
reg [12:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29]
wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24]
wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59]
wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}]
wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9]
wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27]
wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}]
wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}]
wire _majorExc_S_T = io_a_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_4 = io_a_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46]
wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_7 = io_b_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46]
wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}]
wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18]
wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36]
wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}]
wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}]
wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51]
wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46]
wire _isNaN_S_T = io_a_isNaN_0 | notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26]
wire _isNaN_S_T_1 = io_a_isNaN_0 | io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26]
wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}]
wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42]
wire _isInf_S_T = io_a_isInf_0 | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63]
wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}]
wire _isZero_S_T = io_a_isZero_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64]
wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}]
wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33]
wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}]
wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}]
wire _specialCaseA_S_T = io_a_isNaN_0 | io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39]
wire specialCaseA_S = _specialCaseA_S_T | io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}]
wire _specialCaseB_S_T = io_b_isNaN_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39]
wire specialCaseB_S = _specialCaseB_S_T | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}]
wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28]
wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48]
wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}]
wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29]
wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49]
wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}]
wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27]
wire _sExpQuot_S_div_T = io_b_sExp_0[5]; // @[DivSqrtRecFN_small.scala:199:5, :281:28]
wire [4:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[4:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52]
wire [4:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}]
wire [5:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}]
wire [5:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}]
wire [7:0] sExpQuot_S_div = {io_a_sExp_0[6], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[5]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71]
wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 8'sh37; // @[DivSqrtRecFN_small.scala:280:21, :284:48]
wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[6:3]; // @[DivSqrtRecFN_small.scala:280:21, :286:31]
wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31]
wire [2:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[2:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27]
wire [6:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27]
wire [6:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11]
wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48]
wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48]
wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52]
wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54]
wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}]
wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}]
wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}]
wire idle = cycleNum == 4'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25]
wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28]
wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40]
wire _processTwoBits_T = cycleNum > 4'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35]
wire _skipCycle2_T = cycleNum == 4'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31]
wire _skipCycle2_T_1 = sigX_Z[12]; // @[DivSqrtRecFN_small.scala:245:29, :301:48]
wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}]
wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}]
wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [4:0] _GEN = {1'h0, cycleNum} - 5'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56]
wire [4:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [4:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [4:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56]
assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [3:0] _inReady_T_17 = _inReady_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _inReady_T_18 = _inReady_T_17 < 4'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38]
wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38]
wire _inReady_T_20 = _inReady_T_11 | _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _inReady_T_23 = _inReady_T_20 | _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46]
wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [3:0] _rawOutValid_T_17 = _rawOutValid_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _rawOutValid_T_18 = _rawOutValid_T_17 == 4'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42]
wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42]
wire _rawOutValid_T_20 = _rawOutValid_T_11 | _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _rawOutValid_T_23 = _rawOutValid_T_20 | _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51]
wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire [3:0] _cycleNum_T_4 = _cycleNum_T_3 ? 4'hB : 4'hC; // @[DivSqrtRecFN_small.scala:308:{24,36}]
wire [3:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 4'hD; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24]
wire [3:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 4'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20]
wire [3:0] _cycleNum_T_7 = {3'h0, _cycleNum_T_2} | _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56]
wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [3:0] _cycleNum_T_13 = _cycleNum_T_12[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire [3:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 4'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}]
wire [3:0] _cycleNum_T_15 = _cycleNum_T_7 | _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire [3:0] _cycleNum_T_17 = {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire [5:0] _sExp_Z_T = io_a_sExp_0[6:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29]
wire [6:0] _sExp_Z_T_1 = {_sExp_Z_T[5], _sExp_Z_T} + 7'h10; // @[DivSqrtRecFN_small.scala:335:{29,34}]
wire [6:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34]
wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28]
wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}]
wire [9:0] _fractB_Z_T_2 = io_b_sig_0[9:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73]
wire [10:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}]
wire [10:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 11'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}]
wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25]
wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25]
assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25]
wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25]
assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25]
wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25]
assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25]
wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}]
wire [9:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 9'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}]
wire [10:0] _fractB_Z_T_9 = {_fractB_Z_T_4[10], _fractB_Z_T_4[9:0] | _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16]
wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}]
wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}]
wire [10:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 10'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}]
wire [10:0] _fractB_Z_T_15 = _fractB_Z_T_9 | _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16]
wire [10:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100]
wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17]
wire [8:0] _fractB_Z_T_18 = fractB_Z[10:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71]
wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17]
wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}]
wire [9:0] _fractB_Z_T_24 = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71]
wire [9:0] _trialTerm2_newBit0_T = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52]
wire [9:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 10'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}]
wire [10:0] _fractB_Z_T_26 = {_fractB_Z_T_20[10], _fractB_Z_T_20[9:0] | _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16]
wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24]
wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}]
wire [12:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47]
wire [12:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}]
wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21]
wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21]
assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21]
wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21]
assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21]
wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25]
assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25]
wire [1:0] _rem_T_5 = io_a_sig_0[10:9]; // @[DivSqrtRecFN_small.scala:199:5, :354:27]
wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}]
wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56]
wire [8:0] _rem_T_8 = io_a_sig_0[8:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27]
wire [11:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:313:56, :355:{27,44}]
wire [13:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44]
wire [13:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 14'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16]
wire [13:0] _rem_T_12 = {1'h0, _rem_T_3} | _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12]
wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13]
wire [13:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29]
wire [13:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 14'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}]
wire [13:0] rem = _rem_T_12 | _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12]
wire [15:0] _bitMask_T = 16'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23]
wire [13:0] bitMask = _bitMask_T[15:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}]
wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24]
wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}]
wire [12:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48]
wire [12:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}]
wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21]
wire [11:0] _trialTerm_T_5 = {_trialTerm_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}]
wire [12:0] _trialTerm_T_6 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12]
wire [12:0] _trialTerm_T_8 = _trialTerm_T_7 ? 13'h1400 : 13'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}]
wire [12:0] _trialTerm_T_9 = _trialTerm_T_6 | _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12]
wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13]
wire [10:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 11'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}]
wire [12:0] _trialTerm_T_12 = {_trialTerm_T_9[12:11], _trialTerm_T_9[10:0] | _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12]
wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13]
wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26]
wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}]
wire [11:0] _trialTerm_T_17 = {_trialTerm_T_15, 11'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}]
wire [12:0] _trialTerm_T_18 = {_trialTerm_T_12[12], _trialTerm_T_12[11:0] | _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12]
wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13]
wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}]
wire [13:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44]
wire [13:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44]
assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44]
wire [13:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64]
assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64]
wire [13:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31]
assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31]
wire [13:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 14'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}]
wire [13:0] trialTerm = {1'h0, _trialTerm_T_18} | _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12]
wire [14:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24]
wire [14:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42]
wire [15:0] trialRem = {_trialRem_T[14], _trialRem_T} - {_trialRem_T_1[14], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}]
wire [15:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42]
wire newBit = $signed(trialRem) > -16'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23]
wire [15:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:300:35, :358:11, :369:23, :371:{24,42}]
wire [12:0] nextRem_Z = _nextRem_Z_T_1[12:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}]
wire [12:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12]
wire [13:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25]
wire [13:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} | _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:{52,56,64}]
wire [11:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78]
wire [13:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :300:35, :373:{33,56,78}]
wire [11:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73]
wire [11:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 12'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}]
wire [13:0] trialTerm2_newBit1 = {trialTerm2_newBit0[13:12], trialTerm2_newBit0[11:0] | _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}]
wire [16:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22]
wire [16:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22]
assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22]
wire [16:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53]
assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53]
wire [14:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48]
wire [14:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48]
assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48]
wire [14:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79]
assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79]
wire [17:0] _trialRem2_T_2 = {_trialRem2_T[16], _trialRem2_T} - {{3{_trialRem2_T_1[14]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}]
wire [16:0] _trialRem2_T_3 = _trialRem2_T_2[16:0]; // @[DivSqrtRecFN_small.scala:377:27]
wire [16:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27]
wire [14:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :300:35, :378:19]
wire [14:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19]
assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19]
wire [14:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51]
assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51]
wire [13:0] _trialRem2_T_6 = _trialRem2_T_5[13:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}]
wire [14:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}]
wire [14:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65]
wire [14:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65]
assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65]
wire [14:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97]
assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97]
wire [15:0] _trialRem2_T_9 = {_trialRem2_T_7[14], _trialRem2_T_7} - {_trialRem2_T_8[14], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}]
wire [14:0] _trialRem2_T_10 = _trialRem2_T_9[14:0]; // @[DivSqrtRecFN_small.scala:378:44]
wire [14:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44]
wire [16:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[14]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44]
wire [16:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51]
wire newBit2 = $signed(trialRem2) > -17'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24]
wire _nextNotZeroRem_Z_T = inReady | newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40]
wire _nextNotZeroRem_Z_T_1 = |trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60]
wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}]
wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38]
wire [17:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[16], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[14]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}]
wire [16:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[16:0]; // @[DivSqrtRecFN_small.scala:382:58]
wire [16:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58]
wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 17'sh0; // @[DivSqrtRecFN_small.scala:382:{42,58}]
wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27]
wire [13:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[13:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}]
wire [14:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}]
wire [15:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[14], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[14], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}]
wire [14:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[14:0]; // @[DivSqrtRecFN_small.scala:383:76]
wire [14:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76]
wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 15'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}]
wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38]
wire [12:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[12:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}]
wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31]
wire [12:0] _nextRem_Z_2_T_6 = rem2[12:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45]
wire [12:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12]
wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28]
wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}]
wire [12:0] _sigX_Z_T_2 = {newBit, 12'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50]
wire [12:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}]
wire [11:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}]
wire [12:0] _sigX_Z_T_6 = {_sigX_Z_T_3[12], _sigX_Z_T_3[11:0] | _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16]
wire [10:0] _sigX_Z_T_8 = {newBit, 10'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50]
wire [10:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 11'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}]
wire [12:0] _sigX_Z_T_10 = {_sigX_Z_T_6[12:11], _sigX_Z_T_6[10:0] | _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16]
wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17]
wire [12:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 13'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}]
wire [12:0] _sigX_Z_T_13 = _sigX_Z_T_10 | _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16]
wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17]
wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}]
wire [13:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 14'h0; // @[DivSqrtRecFN_small.scala:360:34, :398:{16,27}]
wire [13:0] _sigX_Z_T_17 = {1'h0, _sigX_Z_T_13} | _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:396:74, :397:74, :398:16]
wire [13:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74]
wire [12:0] _sigX_Z_T_19 = bitMask[13:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51]
wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43]
assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}]
assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40]
assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40]
assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40]
assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36]
assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36]
wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39]
assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}]
assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36]
assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[13:1], _io_rawOut_sig_T[0] | notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35]
always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5]
if (reset) begin // @[DivSqrtRecFN_small.scala:199:5]
cycleNum <= 4'h0; // @[DivSqrtRecFN_small.scala:224:33]
inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33]
rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33]
end
else if (~idle | entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}]
cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95]
inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46]
rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51]
end
if (entering) begin // @[DivSqrtRecFN_small.scala:297:28]
sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29]
majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12]
isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12]
isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23]
isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23]
sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30]
sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16]
roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
end
if (entering | ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}]
fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100]
if (entering | ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20]
rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83]
notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103]
sigX_Z <= _sigX_Z_T_21[12:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74]
end
always @(posedge)
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_1 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
inst main of BranchKillableQueue
connect main.clock, clock
connect main.reset, reset
reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, clock
regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
connect main.io.enq, io.enq
connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect main.io.brupdate.b2.taken, io.brupdate.b2.taken
connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect main.io.flush, io.flush
node _io_empty_T = eq(out_valid, UInt<1>(0h0))
node _io_empty_T_1 = and(main.io.empty, _io_empty_T)
connect io.empty, _io_empty_T_1
node _io_count_T = add(main.io.count, out_valid)
node _io_count_T_1 = tail(_io_count_T, 1)
connect io.count, _io_count_T_1
connect io.deq.valid, out_valid
connect io.deq.bits, out_reg
connect io.deq.bits.uop, out_uop
wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out, out_uop
node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T)
connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1
connect out_uop, out_uop_out
node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask)
node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0))
node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0))
node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0))
node _out_valid_T_4 = and(out_valid, _out_valid_T_3)
node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq)
node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0))
node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6)
connect out_valid, _out_valid_T_7
connect main.io.deq.ready, UInt<1>(0h0)
node _T = and(io.deq.ready, io.deq.valid)
node _T_1 = eq(out_valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
when _T_2 :
node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask)
node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0))
node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0))
node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0))
node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11)
node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq)
node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0))
node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14)
connect out_valid, _out_valid_T_15
connect out_reg, main.io.deq.bits
wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out_1, main.io.deq.bits.uop
node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2)
connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3
connect out_uop, out_uop_out_1
connect main.io.deq.ready, UInt<1>(0h1) | module BranchKillableQueue_1( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [39:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [39:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _main_io_deq_valid; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [11:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [39:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg [1:0] out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg [1:0] out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [11:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [5:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [6:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [6:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [39:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [19:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [3:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [39:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [39:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [11:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
reg [3:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [11:0] _out_uop_out_br_mask_T_1; // @[util.scala:93:25]
wire [11:0] out_uop_out_br_mask; // @[util.scala:104:23]
wire [11:0] _out_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_1 = out_uop_br_mask & _out_uop_out_br_mask_T; // @[util.scala:93:{25,27}, :479:22]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire [11:0] _out_valid_T = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:126:51, :458:7, :479:22]
wire _out_valid_T_1 = |_out_valid_T; // @[util.scala:126:{51,59}]
wire _out_valid_T_2 = _out_valid_T_1; // @[util.scala:61:61, :126:59]
wire _out_valid_T_3 = ~_out_valid_T_2; // @[util.scala:61:61, :492:31]
wire _out_valid_T_4 = out_valid & _out_valid_T_3; // @[util.scala:478:28, :492:{28,31}]
wire _out_valid_T_5 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:458:7, :479:22, :492:94]
wire _out_valid_T_6 = ~_out_valid_T_5; // @[util.scala:492:{83,94}]
wire _out_valid_T_7 = _out_valid_T_4 & _out_valid_T_6; // @[util.scala:492:{28,80,83}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire [11:0] _out_valid_T_8 = io_brupdate_b1_mispredict_mask_0 & _main_io_deq_bits_uop_br_mask; // @[util.scala:126:51, :458:7, :476:22]
wire _out_valid_T_9 = |_out_valid_T_8; // @[util.scala:126:{51,59}]
wire _out_valid_T_10 = _out_valid_T_9; // @[util.scala:61:61, :126:59]
wire _out_valid_T_11 = ~_out_valid_T_10; // @[util.scala:61:61, :496:41]
wire _out_valid_T_12 = _main_io_deq_valid & _out_valid_T_11; // @[util.scala:476:22, :496:{38,41}]
wire _out_valid_T_13 = io_flush_0 & _main_io_deq_bits_uop_uses_ldq; // @[util.scala:458:7, :476:22, :496:117]
wire _out_valid_T_14 = ~_out_valid_T_13; // @[util.scala:496:{106,117}]
wire _out_valid_T_15 = _out_valid_T_12 & _out_valid_T_14; // @[util.scala:496:{38,103,106}]
wire [11:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [39:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [11:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _out_uop_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask & _out_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}, :476:22]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_main_io_deq_valid),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[util.scala:458:7]
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[util.scala:458:7]
.io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[util.scala:458:7]
.io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[util.scala:458:7]
.io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[util.scala:458:7]
.io_flush (io_flush_0), // @[util.scala:458:7]
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_1 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_1( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_6 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_6
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e11_s53_6( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_6 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_35 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_35(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_9 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_106
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_107
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_108
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_9( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_106 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_107 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_108 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MemLoader_2 :
input clock : Clock
input reset : Reset
output io : { l2helperUser : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}}
inst buf_info_queue of Queue16_BufInfoBundle_3
connect buf_info_queue.clock, clock
connect buf_info_queue.reset, reset
inst load_info_queue of Queue256_LoadInfoBundle_4
connect load_info_queue.clock, clock
connect load_info_queue.reset, reset
node base_addr_start_index = and(io.src_info.bits.ip, UInt<5>(0h1f))
node _aligned_loadlen_T = add(io.src_info.bits.isize, base_addr_start_index)
node aligned_loadlen = tail(_aligned_loadlen_T, 1)
node _base_addr_end_index_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_T_1 = tail(_base_addr_end_index_T, 1)
node base_addr_end_index = and(_base_addr_end_index_T_1, UInt<5>(0h1f))
node _base_addr_end_index_inclusive_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_inclusive_T_1 = tail(_base_addr_end_index_inclusive_T, 1)
node _base_addr_end_index_inclusive_T_2 = sub(_base_addr_end_index_inclusive_T_1, UInt<1>(0h1))
node _base_addr_end_index_inclusive_T_3 = tail(_base_addr_end_index_inclusive_T_2, 1)
node base_addr_end_index_inclusive = and(_base_addr_end_index_inclusive_T_3, UInt<5>(0h1f))
node _extra_word_T = and(aligned_loadlen, UInt<5>(0h1f))
node extra_word = neq(_extra_word_T, UInt<1>(0h0))
node _base_addr_bytes_aligned_T = dshr(io.src_info.bits.ip, UInt<3>(0h5))
node base_addr_bytes_aligned = dshl(_base_addr_bytes_aligned_T, UInt<3>(0h5))
node _words_to_load_T = dshr(aligned_loadlen, UInt<3>(0h5))
node _words_to_load_T_1 = add(_words_to_load_T, extra_word)
node words_to_load = tail(_words_to_load_T_1, 1)
node _words_to_load_minus_one_T = sub(words_to_load, UInt<1>(0h1))
node words_to_load_minus_one = tail(_words_to_load_minus_one_T, 1)
regreset print_not_done : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(io.src_info.valid, print_not_done)
when _T :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_1
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "base_len: %x\n", io.src_info.bits.isize) : printf_3
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "base_addr_start_index: %x\n", base_addr_start_index) : printf_5
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "aligned_loadlen: %x\n", aligned_loadlen) : printf_7
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "base_addr_end_index: %x\n", base_addr_end_index) : printf_9
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) : printf_11
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "extra_word: %x\n", extra_word) : printf_13
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) : printf_15
regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1))
node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1)
connect loginfo_cycles_8, _loginfo_cycles_T_17
node _T_33 = asUInt(reset)
node _T_34 = eq(_T_33, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "words_to_load: %x\n", words_to_load) : printf_17
regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1))
node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1)
connect loginfo_cycles_9, _loginfo_cycles_T_19
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "words_to_load_minus_one: %x\n", words_to_load_minus_one) : printf_19
when io.src_info.ready :
connect print_not_done, UInt<1>(0h1)
else :
connect print_not_done, UInt<1>(0h0)
connect io.l2helperUser.req.bits.cmd, UInt<1>(0h0)
connect io.l2helperUser.req.bits.size, UInt<3>(0h5)
connect io.l2helperUser.req.bits.data, UInt<1>(0h0)
regreset addrinc : UInt<64>, clock, reset, UInt<64>(0h0)
node _load_info_queue_io_enq_bits_start_byte_T = eq(addrinc, UInt<1>(0h0))
node _load_info_queue_io_enq_bits_start_byte_T_1 = mux(_load_info_queue_io_enq_bits_start_byte_T, base_addr_start_index, UInt<1>(0h0))
connect load_info_queue.io.enq.bits.start_byte, _load_info_queue_io_enq_bits_start_byte_T_1
node _load_info_queue_io_enq_bits_end_byte_T = eq(addrinc, words_to_load_minus_one)
node _load_info_queue_io_enq_bits_end_byte_T_1 = mux(_load_info_queue_io_enq_bits_end_byte_T, base_addr_end_index_inclusive, UInt<5>(0h1f))
connect load_info_queue.io.enq.bits.end_byte, _load_info_queue_io_enq_bits_end_byte_T_1
node _T_41 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_42 = and(_T_41, buf_info_queue.io.enq.ready)
node _T_43 = and(_T_42, load_info_queue.io.enq.ready)
node _T_44 = eq(addrinc, words_to_load_minus_one)
node _T_45 = and(_T_43, _T_44)
when _T_45 :
connect addrinc, UInt<1>(0h0)
else :
node _T_46 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_47 = and(_T_46, buf_info_queue.io.enq.ready)
node _T_48 = and(_T_47, load_info_queue.io.enq.ready)
when _T_48 :
node _addrinc_T = add(addrinc, UInt<1>(0h1))
node _addrinc_T_1 = tail(_addrinc_T, 1)
connect addrinc, _addrinc_T_1
node _T_49 = and(io.src_info.ready, io.src_info.valid)
when _T_49 :
regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1))
node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1)
connect loginfo_cycles_10, _loginfo_cycles_T_21
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "COMPLETED INPUT LOAD FOR DECOMPRESSION\n") : printf_21
node _io_src_info_ready_T = eq(addrinc, words_to_load_minus_one)
node _io_src_info_ready_T_1 = and(io.l2helperUser.req.ready, buf_info_queue.io.enq.ready)
node _io_src_info_ready_T_2 = and(_io_src_info_ready_T_1, load_info_queue.io.enq.ready)
node _io_src_info_ready_T_3 = and(_io_src_info_ready_T_2, _io_src_info_ready_T)
connect io.src_info.ready, _io_src_info_ready_T_3
node _buf_info_queue_io_enq_valid_T = eq(addrinc, UInt<1>(0h0))
node _buf_info_queue_io_enq_valid_T_1 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _buf_info_queue_io_enq_valid_T_2 = and(_buf_info_queue_io_enq_valid_T_1, load_info_queue.io.enq.ready)
node _buf_info_queue_io_enq_valid_T_3 = and(_buf_info_queue_io_enq_valid_T_2, _buf_info_queue_io_enq_valid_T)
connect buf_info_queue.io.enq.valid, _buf_info_queue_io_enq_valid_T_3
node _load_info_queue_io_enq_valid_T = and(io.l2helperUser.req.ready, io.src_info.valid)
node _load_info_queue_io_enq_valid_T_1 = and(_load_info_queue_io_enq_valid_T, buf_info_queue.io.enq.ready)
connect load_info_queue.io.enq.valid, _load_info_queue_io_enq_valid_T_1
connect buf_info_queue.io.enq.bits.len_bytes, io.src_info.bits.isize
node _io_l2helperUser_req_bits_addr_T = shl(addrinc, 5)
node _io_l2helperUser_req_bits_addr_T_1 = add(base_addr_bytes_aligned, _io_l2helperUser_req_bits_addr_T)
node _io_l2helperUser_req_bits_addr_T_2 = tail(_io_l2helperUser_req_bits_addr_T_1, 1)
connect io.l2helperUser.req.bits.addr, _io_l2helperUser_req_bits_addr_T_2
node _io_l2helperUser_req_valid_T = and(io.src_info.valid, buf_info_queue.io.enq.ready)
node _io_l2helperUser_req_valid_T_1 = and(_io_l2helperUser_req_valid_T, load_info_queue.io.enq.ready)
connect io.l2helperUser.req.valid, _io_l2helperUser_req_valid_T_1
regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
inst Queue64_UInt8 of Queue64_UInt8_160
connect Queue64_UInt8.clock, clock
connect Queue64_UInt8.reset, reset
inst Queue64_UInt8_1 of Queue64_UInt8_161
connect Queue64_UInt8_1.clock, clock
connect Queue64_UInt8_1.reset, reset
inst Queue64_UInt8_2 of Queue64_UInt8_162
connect Queue64_UInt8_2.clock, clock
connect Queue64_UInt8_2.reset, reset
inst Queue64_UInt8_3 of Queue64_UInt8_163
connect Queue64_UInt8_3.clock, clock
connect Queue64_UInt8_3.reset, reset
inst Queue64_UInt8_4 of Queue64_UInt8_164
connect Queue64_UInt8_4.clock, clock
connect Queue64_UInt8_4.reset, reset
inst Queue64_UInt8_5 of Queue64_UInt8_165
connect Queue64_UInt8_5.clock, clock
connect Queue64_UInt8_5.reset, reset
inst Queue64_UInt8_6 of Queue64_UInt8_166
connect Queue64_UInt8_6.clock, clock
connect Queue64_UInt8_6.reset, reset
inst Queue64_UInt8_7 of Queue64_UInt8_167
connect Queue64_UInt8_7.clock, clock
connect Queue64_UInt8_7.reset, reset
inst Queue64_UInt8_8 of Queue64_UInt8_168
connect Queue64_UInt8_8.clock, clock
connect Queue64_UInt8_8.reset, reset
inst Queue64_UInt8_9 of Queue64_UInt8_169
connect Queue64_UInt8_9.clock, clock
connect Queue64_UInt8_9.reset, reset
inst Queue64_UInt8_10 of Queue64_UInt8_170
connect Queue64_UInt8_10.clock, clock
connect Queue64_UInt8_10.reset, reset
inst Queue64_UInt8_11 of Queue64_UInt8_171
connect Queue64_UInt8_11.clock, clock
connect Queue64_UInt8_11.reset, reset
inst Queue64_UInt8_12 of Queue64_UInt8_172
connect Queue64_UInt8_12.clock, clock
connect Queue64_UInt8_12.reset, reset
inst Queue64_UInt8_13 of Queue64_UInt8_173
connect Queue64_UInt8_13.clock, clock
connect Queue64_UInt8_13.reset, reset
inst Queue64_UInt8_14 of Queue64_UInt8_174
connect Queue64_UInt8_14.clock, clock
connect Queue64_UInt8_14.reset, reset
inst Queue64_UInt8_15 of Queue64_UInt8_175
connect Queue64_UInt8_15.clock, clock
connect Queue64_UInt8_15.reset, reset
inst Queue64_UInt8_16 of Queue64_UInt8_176
connect Queue64_UInt8_16.clock, clock
connect Queue64_UInt8_16.reset, reset
inst Queue64_UInt8_17 of Queue64_UInt8_177
connect Queue64_UInt8_17.clock, clock
connect Queue64_UInt8_17.reset, reset
inst Queue64_UInt8_18 of Queue64_UInt8_178
connect Queue64_UInt8_18.clock, clock
connect Queue64_UInt8_18.reset, reset
inst Queue64_UInt8_19 of Queue64_UInt8_179
connect Queue64_UInt8_19.clock, clock
connect Queue64_UInt8_19.reset, reset
inst Queue64_UInt8_20 of Queue64_UInt8_180
connect Queue64_UInt8_20.clock, clock
connect Queue64_UInt8_20.reset, reset
inst Queue64_UInt8_21 of Queue64_UInt8_181
connect Queue64_UInt8_21.clock, clock
connect Queue64_UInt8_21.reset, reset
inst Queue64_UInt8_22 of Queue64_UInt8_182
connect Queue64_UInt8_22.clock, clock
connect Queue64_UInt8_22.reset, reset
inst Queue64_UInt8_23 of Queue64_UInt8_183
connect Queue64_UInt8_23.clock, clock
connect Queue64_UInt8_23.reset, reset
inst Queue64_UInt8_24 of Queue64_UInt8_184
connect Queue64_UInt8_24.clock, clock
connect Queue64_UInt8_24.reset, reset
inst Queue64_UInt8_25 of Queue64_UInt8_185
connect Queue64_UInt8_25.clock, clock
connect Queue64_UInt8_25.reset, reset
inst Queue64_UInt8_26 of Queue64_UInt8_186
connect Queue64_UInt8_26.clock, clock
connect Queue64_UInt8_26.reset, reset
inst Queue64_UInt8_27 of Queue64_UInt8_187
connect Queue64_UInt8_27.clock, clock
connect Queue64_UInt8_27.reset, reset
inst Queue64_UInt8_28 of Queue64_UInt8_188
connect Queue64_UInt8_28.clock, clock
connect Queue64_UInt8_28.reset, reset
inst Queue64_UInt8_29 of Queue64_UInt8_189
connect Queue64_UInt8_29.clock, clock
connect Queue64_UInt8_29.reset, reset
inst Queue64_UInt8_30 of Queue64_UInt8_190
connect Queue64_UInt8_30.clock, clock
connect Queue64_UInt8_30.reset, reset
inst Queue64_UInt8_31 of Queue64_UInt8_191
connect Queue64_UInt8_31.clock, clock
connect Queue64_UInt8_31.reset, reset
node align_shamt = shl(load_info_queue.io.deq.bits.start_byte, 3)
node memresp_bits_shifted = dshr(io.l2helperUser.resp.bits.data, align_shamt)
connect Queue64_UInt8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_1.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_2.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_3.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_4.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_5.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_6.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_7.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_9.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_10.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_11.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_12.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_13.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_14.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_15.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_16.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_17.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_18.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_19.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_20.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_21.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_22.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_23.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_24.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_25.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_26.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_27.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_28.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_29.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_30.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_31.io.enq.bits, UInt<1>(0h0)
node _idx_T = add(write_start_index, UInt<1>(0h0))
node idx = rem(_idx_T, UInt<6>(0h20))
node _T_54 = eq(UInt<1>(0h0), idx)
when _T_54 :
node _T_55 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8.io.enq.bits, _T_55
node _T_56 = eq(UInt<1>(0h1), idx)
when _T_56 :
node _T_57 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_1.io.enq.bits, _T_57
node _T_58 = eq(UInt<2>(0h2), idx)
when _T_58 :
node _T_59 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_2.io.enq.bits, _T_59
node _T_60 = eq(UInt<2>(0h3), idx)
when _T_60 :
node _T_61 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_3.io.enq.bits, _T_61
node _T_62 = eq(UInt<3>(0h4), idx)
when _T_62 :
node _T_63 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_4.io.enq.bits, _T_63
node _T_64 = eq(UInt<3>(0h5), idx)
when _T_64 :
node _T_65 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_5.io.enq.bits, _T_65
node _T_66 = eq(UInt<3>(0h6), idx)
when _T_66 :
node _T_67 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_6.io.enq.bits, _T_67
node _T_68 = eq(UInt<3>(0h7), idx)
when _T_68 :
node _T_69 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_7.io.enq.bits, _T_69
node _T_70 = eq(UInt<4>(0h8), idx)
when _T_70 :
node _T_71 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_8.io.enq.bits, _T_71
node _T_72 = eq(UInt<4>(0h9), idx)
when _T_72 :
node _T_73 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_9.io.enq.bits, _T_73
node _T_74 = eq(UInt<4>(0ha), idx)
when _T_74 :
node _T_75 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_10.io.enq.bits, _T_75
node _T_76 = eq(UInt<4>(0hb), idx)
when _T_76 :
node _T_77 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_11.io.enq.bits, _T_77
node _T_78 = eq(UInt<4>(0hc), idx)
when _T_78 :
node _T_79 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_12.io.enq.bits, _T_79
node _T_80 = eq(UInt<4>(0hd), idx)
when _T_80 :
node _T_81 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_13.io.enq.bits, _T_81
node _T_82 = eq(UInt<4>(0he), idx)
when _T_82 :
node _T_83 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_14.io.enq.bits, _T_83
node _T_84 = eq(UInt<4>(0hf), idx)
when _T_84 :
node _T_85 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_15.io.enq.bits, _T_85
node _T_86 = eq(UInt<5>(0h10), idx)
when _T_86 :
node _T_87 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_16.io.enq.bits, _T_87
node _T_88 = eq(UInt<5>(0h11), idx)
when _T_88 :
node _T_89 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_17.io.enq.bits, _T_89
node _T_90 = eq(UInt<5>(0h12), idx)
when _T_90 :
node _T_91 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_18.io.enq.bits, _T_91
node _T_92 = eq(UInt<5>(0h13), idx)
when _T_92 :
node _T_93 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_19.io.enq.bits, _T_93
node _T_94 = eq(UInt<5>(0h14), idx)
when _T_94 :
node _T_95 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_20.io.enq.bits, _T_95
node _T_96 = eq(UInt<5>(0h15), idx)
when _T_96 :
node _T_97 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_21.io.enq.bits, _T_97
node _T_98 = eq(UInt<5>(0h16), idx)
when _T_98 :
node _T_99 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_22.io.enq.bits, _T_99
node _T_100 = eq(UInt<5>(0h17), idx)
when _T_100 :
node _T_101 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_23.io.enq.bits, _T_101
node _T_102 = eq(UInt<5>(0h18), idx)
when _T_102 :
node _T_103 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_24.io.enq.bits, _T_103
node _T_104 = eq(UInt<5>(0h19), idx)
when _T_104 :
node _T_105 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_25.io.enq.bits, _T_105
node _T_106 = eq(UInt<5>(0h1a), idx)
when _T_106 :
node _T_107 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_26.io.enq.bits, _T_107
node _T_108 = eq(UInt<5>(0h1b), idx)
when _T_108 :
node _T_109 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_27.io.enq.bits, _T_109
node _T_110 = eq(UInt<5>(0h1c), idx)
when _T_110 :
node _T_111 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_28.io.enq.bits, _T_111
node _T_112 = eq(UInt<5>(0h1d), idx)
when _T_112 :
node _T_113 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_29.io.enq.bits, _T_113
node _T_114 = eq(UInt<5>(0h1e), idx)
when _T_114 :
node _T_115 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_30.io.enq.bits, _T_115
node _T_116 = eq(UInt<5>(0h1f), idx)
when _T_116 :
node _T_117 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_31.io.enq.bits, _T_117
node _idx_T_1 = add(write_start_index, UInt<1>(0h1))
node idx_1 = rem(_idx_T_1, UInt<6>(0h20))
node _T_118 = eq(UInt<1>(0h0), idx_1)
when _T_118 :
node _T_119 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8.io.enq.bits, _T_119
node _T_120 = eq(UInt<1>(0h1), idx_1)
when _T_120 :
node _T_121 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_1.io.enq.bits, _T_121
node _T_122 = eq(UInt<2>(0h2), idx_1)
when _T_122 :
node _T_123 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_2.io.enq.bits, _T_123
node _T_124 = eq(UInt<2>(0h3), idx_1)
when _T_124 :
node _T_125 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_3.io.enq.bits, _T_125
node _T_126 = eq(UInt<3>(0h4), idx_1)
when _T_126 :
node _T_127 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_4.io.enq.bits, _T_127
node _T_128 = eq(UInt<3>(0h5), idx_1)
when _T_128 :
node _T_129 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_5.io.enq.bits, _T_129
node _T_130 = eq(UInt<3>(0h6), idx_1)
when _T_130 :
node _T_131 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_6.io.enq.bits, _T_131
node _T_132 = eq(UInt<3>(0h7), idx_1)
when _T_132 :
node _T_133 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_7.io.enq.bits, _T_133
node _T_134 = eq(UInt<4>(0h8), idx_1)
when _T_134 :
node _T_135 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_8.io.enq.bits, _T_135
node _T_136 = eq(UInt<4>(0h9), idx_1)
when _T_136 :
node _T_137 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_9.io.enq.bits, _T_137
node _T_138 = eq(UInt<4>(0ha), idx_1)
when _T_138 :
node _T_139 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_10.io.enq.bits, _T_139
node _T_140 = eq(UInt<4>(0hb), idx_1)
when _T_140 :
node _T_141 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_11.io.enq.bits, _T_141
node _T_142 = eq(UInt<4>(0hc), idx_1)
when _T_142 :
node _T_143 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_12.io.enq.bits, _T_143
node _T_144 = eq(UInt<4>(0hd), idx_1)
when _T_144 :
node _T_145 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_13.io.enq.bits, _T_145
node _T_146 = eq(UInt<4>(0he), idx_1)
when _T_146 :
node _T_147 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_14.io.enq.bits, _T_147
node _T_148 = eq(UInt<4>(0hf), idx_1)
when _T_148 :
node _T_149 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_15.io.enq.bits, _T_149
node _T_150 = eq(UInt<5>(0h10), idx_1)
when _T_150 :
node _T_151 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_16.io.enq.bits, _T_151
node _T_152 = eq(UInt<5>(0h11), idx_1)
when _T_152 :
node _T_153 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_17.io.enq.bits, _T_153
node _T_154 = eq(UInt<5>(0h12), idx_1)
when _T_154 :
node _T_155 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_18.io.enq.bits, _T_155
node _T_156 = eq(UInt<5>(0h13), idx_1)
when _T_156 :
node _T_157 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_19.io.enq.bits, _T_157
node _T_158 = eq(UInt<5>(0h14), idx_1)
when _T_158 :
node _T_159 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_20.io.enq.bits, _T_159
node _T_160 = eq(UInt<5>(0h15), idx_1)
when _T_160 :
node _T_161 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_21.io.enq.bits, _T_161
node _T_162 = eq(UInt<5>(0h16), idx_1)
when _T_162 :
node _T_163 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_22.io.enq.bits, _T_163
node _T_164 = eq(UInt<5>(0h17), idx_1)
when _T_164 :
node _T_165 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_23.io.enq.bits, _T_165
node _T_166 = eq(UInt<5>(0h18), idx_1)
when _T_166 :
node _T_167 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_24.io.enq.bits, _T_167
node _T_168 = eq(UInt<5>(0h19), idx_1)
when _T_168 :
node _T_169 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_25.io.enq.bits, _T_169
node _T_170 = eq(UInt<5>(0h1a), idx_1)
when _T_170 :
node _T_171 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_26.io.enq.bits, _T_171
node _T_172 = eq(UInt<5>(0h1b), idx_1)
when _T_172 :
node _T_173 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_27.io.enq.bits, _T_173
node _T_174 = eq(UInt<5>(0h1c), idx_1)
when _T_174 :
node _T_175 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_28.io.enq.bits, _T_175
node _T_176 = eq(UInt<5>(0h1d), idx_1)
when _T_176 :
node _T_177 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_29.io.enq.bits, _T_177
node _T_178 = eq(UInt<5>(0h1e), idx_1)
when _T_178 :
node _T_179 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_30.io.enq.bits, _T_179
node _T_180 = eq(UInt<5>(0h1f), idx_1)
when _T_180 :
node _T_181 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_31.io.enq.bits, _T_181
node _idx_T_2 = add(write_start_index, UInt<2>(0h2))
node idx_2 = rem(_idx_T_2, UInt<6>(0h20))
node _T_182 = eq(UInt<1>(0h0), idx_2)
when _T_182 :
node _T_183 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8.io.enq.bits, _T_183
node _T_184 = eq(UInt<1>(0h1), idx_2)
when _T_184 :
node _T_185 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_1.io.enq.bits, _T_185
node _T_186 = eq(UInt<2>(0h2), idx_2)
when _T_186 :
node _T_187 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_2.io.enq.bits, _T_187
node _T_188 = eq(UInt<2>(0h3), idx_2)
when _T_188 :
node _T_189 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_3.io.enq.bits, _T_189
node _T_190 = eq(UInt<3>(0h4), idx_2)
when _T_190 :
node _T_191 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_4.io.enq.bits, _T_191
node _T_192 = eq(UInt<3>(0h5), idx_2)
when _T_192 :
node _T_193 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_5.io.enq.bits, _T_193
node _T_194 = eq(UInt<3>(0h6), idx_2)
when _T_194 :
node _T_195 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_6.io.enq.bits, _T_195
node _T_196 = eq(UInt<3>(0h7), idx_2)
when _T_196 :
node _T_197 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_7.io.enq.bits, _T_197
node _T_198 = eq(UInt<4>(0h8), idx_2)
when _T_198 :
node _T_199 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_8.io.enq.bits, _T_199
node _T_200 = eq(UInt<4>(0h9), idx_2)
when _T_200 :
node _T_201 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_9.io.enq.bits, _T_201
node _T_202 = eq(UInt<4>(0ha), idx_2)
when _T_202 :
node _T_203 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_10.io.enq.bits, _T_203
node _T_204 = eq(UInt<4>(0hb), idx_2)
when _T_204 :
node _T_205 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_11.io.enq.bits, _T_205
node _T_206 = eq(UInt<4>(0hc), idx_2)
when _T_206 :
node _T_207 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_12.io.enq.bits, _T_207
node _T_208 = eq(UInt<4>(0hd), idx_2)
when _T_208 :
node _T_209 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_13.io.enq.bits, _T_209
node _T_210 = eq(UInt<4>(0he), idx_2)
when _T_210 :
node _T_211 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_14.io.enq.bits, _T_211
node _T_212 = eq(UInt<4>(0hf), idx_2)
when _T_212 :
node _T_213 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_15.io.enq.bits, _T_213
node _T_214 = eq(UInt<5>(0h10), idx_2)
when _T_214 :
node _T_215 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_16.io.enq.bits, _T_215
node _T_216 = eq(UInt<5>(0h11), idx_2)
when _T_216 :
node _T_217 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_17.io.enq.bits, _T_217
node _T_218 = eq(UInt<5>(0h12), idx_2)
when _T_218 :
node _T_219 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_18.io.enq.bits, _T_219
node _T_220 = eq(UInt<5>(0h13), idx_2)
when _T_220 :
node _T_221 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_19.io.enq.bits, _T_221
node _T_222 = eq(UInt<5>(0h14), idx_2)
when _T_222 :
node _T_223 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_20.io.enq.bits, _T_223
node _T_224 = eq(UInt<5>(0h15), idx_2)
when _T_224 :
node _T_225 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_21.io.enq.bits, _T_225
node _T_226 = eq(UInt<5>(0h16), idx_2)
when _T_226 :
node _T_227 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_22.io.enq.bits, _T_227
node _T_228 = eq(UInt<5>(0h17), idx_2)
when _T_228 :
node _T_229 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_23.io.enq.bits, _T_229
node _T_230 = eq(UInt<5>(0h18), idx_2)
when _T_230 :
node _T_231 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_24.io.enq.bits, _T_231
node _T_232 = eq(UInt<5>(0h19), idx_2)
when _T_232 :
node _T_233 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_25.io.enq.bits, _T_233
node _T_234 = eq(UInt<5>(0h1a), idx_2)
when _T_234 :
node _T_235 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_26.io.enq.bits, _T_235
node _T_236 = eq(UInt<5>(0h1b), idx_2)
when _T_236 :
node _T_237 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_27.io.enq.bits, _T_237
node _T_238 = eq(UInt<5>(0h1c), idx_2)
when _T_238 :
node _T_239 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_28.io.enq.bits, _T_239
node _T_240 = eq(UInt<5>(0h1d), idx_2)
when _T_240 :
node _T_241 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_29.io.enq.bits, _T_241
node _T_242 = eq(UInt<5>(0h1e), idx_2)
when _T_242 :
node _T_243 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_30.io.enq.bits, _T_243
node _T_244 = eq(UInt<5>(0h1f), idx_2)
when _T_244 :
node _T_245 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_31.io.enq.bits, _T_245
node _idx_T_3 = add(write_start_index, UInt<2>(0h3))
node idx_3 = rem(_idx_T_3, UInt<6>(0h20))
node _T_246 = eq(UInt<1>(0h0), idx_3)
when _T_246 :
node _T_247 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8.io.enq.bits, _T_247
node _T_248 = eq(UInt<1>(0h1), idx_3)
when _T_248 :
node _T_249 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_1.io.enq.bits, _T_249
node _T_250 = eq(UInt<2>(0h2), idx_3)
when _T_250 :
node _T_251 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_2.io.enq.bits, _T_251
node _T_252 = eq(UInt<2>(0h3), idx_3)
when _T_252 :
node _T_253 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_3.io.enq.bits, _T_253
node _T_254 = eq(UInt<3>(0h4), idx_3)
when _T_254 :
node _T_255 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_4.io.enq.bits, _T_255
node _T_256 = eq(UInt<3>(0h5), idx_3)
when _T_256 :
node _T_257 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_5.io.enq.bits, _T_257
node _T_258 = eq(UInt<3>(0h6), idx_3)
when _T_258 :
node _T_259 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_6.io.enq.bits, _T_259
node _T_260 = eq(UInt<3>(0h7), idx_3)
when _T_260 :
node _T_261 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_7.io.enq.bits, _T_261
node _T_262 = eq(UInt<4>(0h8), idx_3)
when _T_262 :
node _T_263 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_8.io.enq.bits, _T_263
node _T_264 = eq(UInt<4>(0h9), idx_3)
when _T_264 :
node _T_265 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_9.io.enq.bits, _T_265
node _T_266 = eq(UInt<4>(0ha), idx_3)
when _T_266 :
node _T_267 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_10.io.enq.bits, _T_267
node _T_268 = eq(UInt<4>(0hb), idx_3)
when _T_268 :
node _T_269 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_11.io.enq.bits, _T_269
node _T_270 = eq(UInt<4>(0hc), idx_3)
when _T_270 :
node _T_271 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_12.io.enq.bits, _T_271
node _T_272 = eq(UInt<4>(0hd), idx_3)
when _T_272 :
node _T_273 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_13.io.enq.bits, _T_273
node _T_274 = eq(UInt<4>(0he), idx_3)
when _T_274 :
node _T_275 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_14.io.enq.bits, _T_275
node _T_276 = eq(UInt<4>(0hf), idx_3)
when _T_276 :
node _T_277 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_15.io.enq.bits, _T_277
node _T_278 = eq(UInt<5>(0h10), idx_3)
when _T_278 :
node _T_279 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_16.io.enq.bits, _T_279
node _T_280 = eq(UInt<5>(0h11), idx_3)
when _T_280 :
node _T_281 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_17.io.enq.bits, _T_281
node _T_282 = eq(UInt<5>(0h12), idx_3)
when _T_282 :
node _T_283 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_18.io.enq.bits, _T_283
node _T_284 = eq(UInt<5>(0h13), idx_3)
when _T_284 :
node _T_285 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_19.io.enq.bits, _T_285
node _T_286 = eq(UInt<5>(0h14), idx_3)
when _T_286 :
node _T_287 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_20.io.enq.bits, _T_287
node _T_288 = eq(UInt<5>(0h15), idx_3)
when _T_288 :
node _T_289 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_21.io.enq.bits, _T_289
node _T_290 = eq(UInt<5>(0h16), idx_3)
when _T_290 :
node _T_291 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_22.io.enq.bits, _T_291
node _T_292 = eq(UInt<5>(0h17), idx_3)
when _T_292 :
node _T_293 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_23.io.enq.bits, _T_293
node _T_294 = eq(UInt<5>(0h18), idx_3)
when _T_294 :
node _T_295 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_24.io.enq.bits, _T_295
node _T_296 = eq(UInt<5>(0h19), idx_3)
when _T_296 :
node _T_297 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_25.io.enq.bits, _T_297
node _T_298 = eq(UInt<5>(0h1a), idx_3)
when _T_298 :
node _T_299 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_26.io.enq.bits, _T_299
node _T_300 = eq(UInt<5>(0h1b), idx_3)
when _T_300 :
node _T_301 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_27.io.enq.bits, _T_301
node _T_302 = eq(UInt<5>(0h1c), idx_3)
when _T_302 :
node _T_303 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_28.io.enq.bits, _T_303
node _T_304 = eq(UInt<5>(0h1d), idx_3)
when _T_304 :
node _T_305 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_29.io.enq.bits, _T_305
node _T_306 = eq(UInt<5>(0h1e), idx_3)
when _T_306 :
node _T_307 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_30.io.enq.bits, _T_307
node _T_308 = eq(UInt<5>(0h1f), idx_3)
when _T_308 :
node _T_309 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_31.io.enq.bits, _T_309
node _idx_T_4 = add(write_start_index, UInt<3>(0h4))
node idx_4 = rem(_idx_T_4, UInt<6>(0h20))
node _T_310 = eq(UInt<1>(0h0), idx_4)
when _T_310 :
node _T_311 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8.io.enq.bits, _T_311
node _T_312 = eq(UInt<1>(0h1), idx_4)
when _T_312 :
node _T_313 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_1.io.enq.bits, _T_313
node _T_314 = eq(UInt<2>(0h2), idx_4)
when _T_314 :
node _T_315 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_2.io.enq.bits, _T_315
node _T_316 = eq(UInt<2>(0h3), idx_4)
when _T_316 :
node _T_317 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_3.io.enq.bits, _T_317
node _T_318 = eq(UInt<3>(0h4), idx_4)
when _T_318 :
node _T_319 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_4.io.enq.bits, _T_319
node _T_320 = eq(UInt<3>(0h5), idx_4)
when _T_320 :
node _T_321 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_5.io.enq.bits, _T_321
node _T_322 = eq(UInt<3>(0h6), idx_4)
when _T_322 :
node _T_323 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_6.io.enq.bits, _T_323
node _T_324 = eq(UInt<3>(0h7), idx_4)
when _T_324 :
node _T_325 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_7.io.enq.bits, _T_325
node _T_326 = eq(UInt<4>(0h8), idx_4)
when _T_326 :
node _T_327 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_8.io.enq.bits, _T_327
node _T_328 = eq(UInt<4>(0h9), idx_4)
when _T_328 :
node _T_329 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_9.io.enq.bits, _T_329
node _T_330 = eq(UInt<4>(0ha), idx_4)
when _T_330 :
node _T_331 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_10.io.enq.bits, _T_331
node _T_332 = eq(UInt<4>(0hb), idx_4)
when _T_332 :
node _T_333 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_11.io.enq.bits, _T_333
node _T_334 = eq(UInt<4>(0hc), idx_4)
when _T_334 :
node _T_335 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_12.io.enq.bits, _T_335
node _T_336 = eq(UInt<4>(0hd), idx_4)
when _T_336 :
node _T_337 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_13.io.enq.bits, _T_337
node _T_338 = eq(UInt<4>(0he), idx_4)
when _T_338 :
node _T_339 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_14.io.enq.bits, _T_339
node _T_340 = eq(UInt<4>(0hf), idx_4)
when _T_340 :
node _T_341 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_15.io.enq.bits, _T_341
node _T_342 = eq(UInt<5>(0h10), idx_4)
when _T_342 :
node _T_343 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_16.io.enq.bits, _T_343
node _T_344 = eq(UInt<5>(0h11), idx_4)
when _T_344 :
node _T_345 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_17.io.enq.bits, _T_345
node _T_346 = eq(UInt<5>(0h12), idx_4)
when _T_346 :
node _T_347 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_18.io.enq.bits, _T_347
node _T_348 = eq(UInt<5>(0h13), idx_4)
when _T_348 :
node _T_349 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_19.io.enq.bits, _T_349
node _T_350 = eq(UInt<5>(0h14), idx_4)
when _T_350 :
node _T_351 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_20.io.enq.bits, _T_351
node _T_352 = eq(UInt<5>(0h15), idx_4)
when _T_352 :
node _T_353 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_21.io.enq.bits, _T_353
node _T_354 = eq(UInt<5>(0h16), idx_4)
when _T_354 :
node _T_355 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_22.io.enq.bits, _T_355
node _T_356 = eq(UInt<5>(0h17), idx_4)
when _T_356 :
node _T_357 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_23.io.enq.bits, _T_357
node _T_358 = eq(UInt<5>(0h18), idx_4)
when _T_358 :
node _T_359 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_24.io.enq.bits, _T_359
node _T_360 = eq(UInt<5>(0h19), idx_4)
when _T_360 :
node _T_361 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_25.io.enq.bits, _T_361
node _T_362 = eq(UInt<5>(0h1a), idx_4)
when _T_362 :
node _T_363 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_26.io.enq.bits, _T_363
node _T_364 = eq(UInt<5>(0h1b), idx_4)
when _T_364 :
node _T_365 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_27.io.enq.bits, _T_365
node _T_366 = eq(UInt<5>(0h1c), idx_4)
when _T_366 :
node _T_367 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_28.io.enq.bits, _T_367
node _T_368 = eq(UInt<5>(0h1d), idx_4)
when _T_368 :
node _T_369 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_29.io.enq.bits, _T_369
node _T_370 = eq(UInt<5>(0h1e), idx_4)
when _T_370 :
node _T_371 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_30.io.enq.bits, _T_371
node _T_372 = eq(UInt<5>(0h1f), idx_4)
when _T_372 :
node _T_373 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_31.io.enq.bits, _T_373
node _idx_T_5 = add(write_start_index, UInt<3>(0h5))
node idx_5 = rem(_idx_T_5, UInt<6>(0h20))
node _T_374 = eq(UInt<1>(0h0), idx_5)
when _T_374 :
node _T_375 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8.io.enq.bits, _T_375
node _T_376 = eq(UInt<1>(0h1), idx_5)
when _T_376 :
node _T_377 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_1.io.enq.bits, _T_377
node _T_378 = eq(UInt<2>(0h2), idx_5)
when _T_378 :
node _T_379 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_2.io.enq.bits, _T_379
node _T_380 = eq(UInt<2>(0h3), idx_5)
when _T_380 :
node _T_381 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_3.io.enq.bits, _T_381
node _T_382 = eq(UInt<3>(0h4), idx_5)
when _T_382 :
node _T_383 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_4.io.enq.bits, _T_383
node _T_384 = eq(UInt<3>(0h5), idx_5)
when _T_384 :
node _T_385 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_5.io.enq.bits, _T_385
node _T_386 = eq(UInt<3>(0h6), idx_5)
when _T_386 :
node _T_387 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_6.io.enq.bits, _T_387
node _T_388 = eq(UInt<3>(0h7), idx_5)
when _T_388 :
node _T_389 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_7.io.enq.bits, _T_389
node _T_390 = eq(UInt<4>(0h8), idx_5)
when _T_390 :
node _T_391 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_8.io.enq.bits, _T_391
node _T_392 = eq(UInt<4>(0h9), idx_5)
when _T_392 :
node _T_393 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_9.io.enq.bits, _T_393
node _T_394 = eq(UInt<4>(0ha), idx_5)
when _T_394 :
node _T_395 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_10.io.enq.bits, _T_395
node _T_396 = eq(UInt<4>(0hb), idx_5)
when _T_396 :
node _T_397 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_11.io.enq.bits, _T_397
node _T_398 = eq(UInt<4>(0hc), idx_5)
when _T_398 :
node _T_399 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_12.io.enq.bits, _T_399
node _T_400 = eq(UInt<4>(0hd), idx_5)
when _T_400 :
node _T_401 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_13.io.enq.bits, _T_401
node _T_402 = eq(UInt<4>(0he), idx_5)
when _T_402 :
node _T_403 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_14.io.enq.bits, _T_403
node _T_404 = eq(UInt<4>(0hf), idx_5)
when _T_404 :
node _T_405 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_15.io.enq.bits, _T_405
node _T_406 = eq(UInt<5>(0h10), idx_5)
when _T_406 :
node _T_407 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_16.io.enq.bits, _T_407
node _T_408 = eq(UInt<5>(0h11), idx_5)
when _T_408 :
node _T_409 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_17.io.enq.bits, _T_409
node _T_410 = eq(UInt<5>(0h12), idx_5)
when _T_410 :
node _T_411 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_18.io.enq.bits, _T_411
node _T_412 = eq(UInt<5>(0h13), idx_5)
when _T_412 :
node _T_413 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_19.io.enq.bits, _T_413
node _T_414 = eq(UInt<5>(0h14), idx_5)
when _T_414 :
node _T_415 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_20.io.enq.bits, _T_415
node _T_416 = eq(UInt<5>(0h15), idx_5)
when _T_416 :
node _T_417 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_21.io.enq.bits, _T_417
node _T_418 = eq(UInt<5>(0h16), idx_5)
when _T_418 :
node _T_419 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_22.io.enq.bits, _T_419
node _T_420 = eq(UInt<5>(0h17), idx_5)
when _T_420 :
node _T_421 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_23.io.enq.bits, _T_421
node _T_422 = eq(UInt<5>(0h18), idx_5)
when _T_422 :
node _T_423 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_24.io.enq.bits, _T_423
node _T_424 = eq(UInt<5>(0h19), idx_5)
when _T_424 :
node _T_425 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_25.io.enq.bits, _T_425
node _T_426 = eq(UInt<5>(0h1a), idx_5)
when _T_426 :
node _T_427 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_26.io.enq.bits, _T_427
node _T_428 = eq(UInt<5>(0h1b), idx_5)
when _T_428 :
node _T_429 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_27.io.enq.bits, _T_429
node _T_430 = eq(UInt<5>(0h1c), idx_5)
when _T_430 :
node _T_431 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_28.io.enq.bits, _T_431
node _T_432 = eq(UInt<5>(0h1d), idx_5)
when _T_432 :
node _T_433 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_29.io.enq.bits, _T_433
node _T_434 = eq(UInt<5>(0h1e), idx_5)
when _T_434 :
node _T_435 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_30.io.enq.bits, _T_435
node _T_436 = eq(UInt<5>(0h1f), idx_5)
when _T_436 :
node _T_437 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_31.io.enq.bits, _T_437
node _idx_T_6 = add(write_start_index, UInt<3>(0h6))
node idx_6 = rem(_idx_T_6, UInt<6>(0h20))
node _T_438 = eq(UInt<1>(0h0), idx_6)
when _T_438 :
node _T_439 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8.io.enq.bits, _T_439
node _T_440 = eq(UInt<1>(0h1), idx_6)
when _T_440 :
node _T_441 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_1.io.enq.bits, _T_441
node _T_442 = eq(UInt<2>(0h2), idx_6)
when _T_442 :
node _T_443 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_2.io.enq.bits, _T_443
node _T_444 = eq(UInt<2>(0h3), idx_6)
when _T_444 :
node _T_445 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_3.io.enq.bits, _T_445
node _T_446 = eq(UInt<3>(0h4), idx_6)
when _T_446 :
node _T_447 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_4.io.enq.bits, _T_447
node _T_448 = eq(UInt<3>(0h5), idx_6)
when _T_448 :
node _T_449 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_5.io.enq.bits, _T_449
node _T_450 = eq(UInt<3>(0h6), idx_6)
when _T_450 :
node _T_451 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_6.io.enq.bits, _T_451
node _T_452 = eq(UInt<3>(0h7), idx_6)
when _T_452 :
node _T_453 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_7.io.enq.bits, _T_453
node _T_454 = eq(UInt<4>(0h8), idx_6)
when _T_454 :
node _T_455 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_8.io.enq.bits, _T_455
node _T_456 = eq(UInt<4>(0h9), idx_6)
when _T_456 :
node _T_457 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_9.io.enq.bits, _T_457
node _T_458 = eq(UInt<4>(0ha), idx_6)
when _T_458 :
node _T_459 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_10.io.enq.bits, _T_459
node _T_460 = eq(UInt<4>(0hb), idx_6)
when _T_460 :
node _T_461 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_11.io.enq.bits, _T_461
node _T_462 = eq(UInt<4>(0hc), idx_6)
when _T_462 :
node _T_463 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_12.io.enq.bits, _T_463
node _T_464 = eq(UInt<4>(0hd), idx_6)
when _T_464 :
node _T_465 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_13.io.enq.bits, _T_465
node _T_466 = eq(UInt<4>(0he), idx_6)
when _T_466 :
node _T_467 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_14.io.enq.bits, _T_467
node _T_468 = eq(UInt<4>(0hf), idx_6)
when _T_468 :
node _T_469 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_15.io.enq.bits, _T_469
node _T_470 = eq(UInt<5>(0h10), idx_6)
when _T_470 :
node _T_471 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_16.io.enq.bits, _T_471
node _T_472 = eq(UInt<5>(0h11), idx_6)
when _T_472 :
node _T_473 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_17.io.enq.bits, _T_473
node _T_474 = eq(UInt<5>(0h12), idx_6)
when _T_474 :
node _T_475 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_18.io.enq.bits, _T_475
node _T_476 = eq(UInt<5>(0h13), idx_6)
when _T_476 :
node _T_477 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_19.io.enq.bits, _T_477
node _T_478 = eq(UInt<5>(0h14), idx_6)
when _T_478 :
node _T_479 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_20.io.enq.bits, _T_479
node _T_480 = eq(UInt<5>(0h15), idx_6)
when _T_480 :
node _T_481 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_21.io.enq.bits, _T_481
node _T_482 = eq(UInt<5>(0h16), idx_6)
when _T_482 :
node _T_483 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_22.io.enq.bits, _T_483
node _T_484 = eq(UInt<5>(0h17), idx_6)
when _T_484 :
node _T_485 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_23.io.enq.bits, _T_485
node _T_486 = eq(UInt<5>(0h18), idx_6)
when _T_486 :
node _T_487 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_24.io.enq.bits, _T_487
node _T_488 = eq(UInt<5>(0h19), idx_6)
when _T_488 :
node _T_489 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_25.io.enq.bits, _T_489
node _T_490 = eq(UInt<5>(0h1a), idx_6)
when _T_490 :
node _T_491 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_26.io.enq.bits, _T_491
node _T_492 = eq(UInt<5>(0h1b), idx_6)
when _T_492 :
node _T_493 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_27.io.enq.bits, _T_493
node _T_494 = eq(UInt<5>(0h1c), idx_6)
when _T_494 :
node _T_495 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_28.io.enq.bits, _T_495
node _T_496 = eq(UInt<5>(0h1d), idx_6)
when _T_496 :
node _T_497 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_29.io.enq.bits, _T_497
node _T_498 = eq(UInt<5>(0h1e), idx_6)
when _T_498 :
node _T_499 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_30.io.enq.bits, _T_499
node _T_500 = eq(UInt<5>(0h1f), idx_6)
when _T_500 :
node _T_501 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_31.io.enq.bits, _T_501
node _idx_T_7 = add(write_start_index, UInt<3>(0h7))
node idx_7 = rem(_idx_T_7, UInt<6>(0h20))
node _T_502 = eq(UInt<1>(0h0), idx_7)
when _T_502 :
node _T_503 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8.io.enq.bits, _T_503
node _T_504 = eq(UInt<1>(0h1), idx_7)
when _T_504 :
node _T_505 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_1.io.enq.bits, _T_505
node _T_506 = eq(UInt<2>(0h2), idx_7)
when _T_506 :
node _T_507 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_2.io.enq.bits, _T_507
node _T_508 = eq(UInt<2>(0h3), idx_7)
when _T_508 :
node _T_509 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_3.io.enq.bits, _T_509
node _T_510 = eq(UInt<3>(0h4), idx_7)
when _T_510 :
node _T_511 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_4.io.enq.bits, _T_511
node _T_512 = eq(UInt<3>(0h5), idx_7)
when _T_512 :
node _T_513 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_5.io.enq.bits, _T_513
node _T_514 = eq(UInt<3>(0h6), idx_7)
when _T_514 :
node _T_515 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_6.io.enq.bits, _T_515
node _T_516 = eq(UInt<3>(0h7), idx_7)
when _T_516 :
node _T_517 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_7.io.enq.bits, _T_517
node _T_518 = eq(UInt<4>(0h8), idx_7)
when _T_518 :
node _T_519 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_8.io.enq.bits, _T_519
node _T_520 = eq(UInt<4>(0h9), idx_7)
when _T_520 :
node _T_521 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_9.io.enq.bits, _T_521
node _T_522 = eq(UInt<4>(0ha), idx_7)
when _T_522 :
node _T_523 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_10.io.enq.bits, _T_523
node _T_524 = eq(UInt<4>(0hb), idx_7)
when _T_524 :
node _T_525 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_11.io.enq.bits, _T_525
node _T_526 = eq(UInt<4>(0hc), idx_7)
when _T_526 :
node _T_527 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_12.io.enq.bits, _T_527
node _T_528 = eq(UInt<4>(0hd), idx_7)
when _T_528 :
node _T_529 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_13.io.enq.bits, _T_529
node _T_530 = eq(UInt<4>(0he), idx_7)
when _T_530 :
node _T_531 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_14.io.enq.bits, _T_531
node _T_532 = eq(UInt<4>(0hf), idx_7)
when _T_532 :
node _T_533 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_15.io.enq.bits, _T_533
node _T_534 = eq(UInt<5>(0h10), idx_7)
when _T_534 :
node _T_535 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_16.io.enq.bits, _T_535
node _T_536 = eq(UInt<5>(0h11), idx_7)
when _T_536 :
node _T_537 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_17.io.enq.bits, _T_537
node _T_538 = eq(UInt<5>(0h12), idx_7)
when _T_538 :
node _T_539 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_18.io.enq.bits, _T_539
node _T_540 = eq(UInt<5>(0h13), idx_7)
when _T_540 :
node _T_541 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_19.io.enq.bits, _T_541
node _T_542 = eq(UInt<5>(0h14), idx_7)
when _T_542 :
node _T_543 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_20.io.enq.bits, _T_543
node _T_544 = eq(UInt<5>(0h15), idx_7)
when _T_544 :
node _T_545 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_21.io.enq.bits, _T_545
node _T_546 = eq(UInt<5>(0h16), idx_7)
when _T_546 :
node _T_547 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_22.io.enq.bits, _T_547
node _T_548 = eq(UInt<5>(0h17), idx_7)
when _T_548 :
node _T_549 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_23.io.enq.bits, _T_549
node _T_550 = eq(UInt<5>(0h18), idx_7)
when _T_550 :
node _T_551 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_24.io.enq.bits, _T_551
node _T_552 = eq(UInt<5>(0h19), idx_7)
when _T_552 :
node _T_553 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_25.io.enq.bits, _T_553
node _T_554 = eq(UInt<5>(0h1a), idx_7)
when _T_554 :
node _T_555 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_26.io.enq.bits, _T_555
node _T_556 = eq(UInt<5>(0h1b), idx_7)
when _T_556 :
node _T_557 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_27.io.enq.bits, _T_557
node _T_558 = eq(UInt<5>(0h1c), idx_7)
when _T_558 :
node _T_559 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_28.io.enq.bits, _T_559
node _T_560 = eq(UInt<5>(0h1d), idx_7)
when _T_560 :
node _T_561 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_29.io.enq.bits, _T_561
node _T_562 = eq(UInt<5>(0h1e), idx_7)
when _T_562 :
node _T_563 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_30.io.enq.bits, _T_563
node _T_564 = eq(UInt<5>(0h1f), idx_7)
when _T_564 :
node _T_565 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_31.io.enq.bits, _T_565
node _idx_T_8 = add(write_start_index, UInt<4>(0h8))
node idx_8 = rem(_idx_T_8, UInt<6>(0h20))
node _T_566 = eq(UInt<1>(0h0), idx_8)
when _T_566 :
node _T_567 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8.io.enq.bits, _T_567
node _T_568 = eq(UInt<1>(0h1), idx_8)
when _T_568 :
node _T_569 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_1.io.enq.bits, _T_569
node _T_570 = eq(UInt<2>(0h2), idx_8)
when _T_570 :
node _T_571 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_2.io.enq.bits, _T_571
node _T_572 = eq(UInt<2>(0h3), idx_8)
when _T_572 :
node _T_573 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_3.io.enq.bits, _T_573
node _T_574 = eq(UInt<3>(0h4), idx_8)
when _T_574 :
node _T_575 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_4.io.enq.bits, _T_575
node _T_576 = eq(UInt<3>(0h5), idx_8)
when _T_576 :
node _T_577 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_5.io.enq.bits, _T_577
node _T_578 = eq(UInt<3>(0h6), idx_8)
when _T_578 :
node _T_579 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_6.io.enq.bits, _T_579
node _T_580 = eq(UInt<3>(0h7), idx_8)
when _T_580 :
node _T_581 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_7.io.enq.bits, _T_581
node _T_582 = eq(UInt<4>(0h8), idx_8)
when _T_582 :
node _T_583 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_8.io.enq.bits, _T_583
node _T_584 = eq(UInt<4>(0h9), idx_8)
when _T_584 :
node _T_585 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_9.io.enq.bits, _T_585
node _T_586 = eq(UInt<4>(0ha), idx_8)
when _T_586 :
node _T_587 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_10.io.enq.bits, _T_587
node _T_588 = eq(UInt<4>(0hb), idx_8)
when _T_588 :
node _T_589 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_11.io.enq.bits, _T_589
node _T_590 = eq(UInt<4>(0hc), idx_8)
when _T_590 :
node _T_591 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_12.io.enq.bits, _T_591
node _T_592 = eq(UInt<4>(0hd), idx_8)
when _T_592 :
node _T_593 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_13.io.enq.bits, _T_593
node _T_594 = eq(UInt<4>(0he), idx_8)
when _T_594 :
node _T_595 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_14.io.enq.bits, _T_595
node _T_596 = eq(UInt<4>(0hf), idx_8)
when _T_596 :
node _T_597 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_15.io.enq.bits, _T_597
node _T_598 = eq(UInt<5>(0h10), idx_8)
when _T_598 :
node _T_599 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_16.io.enq.bits, _T_599
node _T_600 = eq(UInt<5>(0h11), idx_8)
when _T_600 :
node _T_601 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_17.io.enq.bits, _T_601
node _T_602 = eq(UInt<5>(0h12), idx_8)
when _T_602 :
node _T_603 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_18.io.enq.bits, _T_603
node _T_604 = eq(UInt<5>(0h13), idx_8)
when _T_604 :
node _T_605 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_19.io.enq.bits, _T_605
node _T_606 = eq(UInt<5>(0h14), idx_8)
when _T_606 :
node _T_607 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_20.io.enq.bits, _T_607
node _T_608 = eq(UInt<5>(0h15), idx_8)
when _T_608 :
node _T_609 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_21.io.enq.bits, _T_609
node _T_610 = eq(UInt<5>(0h16), idx_8)
when _T_610 :
node _T_611 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_22.io.enq.bits, _T_611
node _T_612 = eq(UInt<5>(0h17), idx_8)
when _T_612 :
node _T_613 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_23.io.enq.bits, _T_613
node _T_614 = eq(UInt<5>(0h18), idx_8)
when _T_614 :
node _T_615 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_24.io.enq.bits, _T_615
node _T_616 = eq(UInt<5>(0h19), idx_8)
when _T_616 :
node _T_617 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_25.io.enq.bits, _T_617
node _T_618 = eq(UInt<5>(0h1a), idx_8)
when _T_618 :
node _T_619 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_26.io.enq.bits, _T_619
node _T_620 = eq(UInt<5>(0h1b), idx_8)
when _T_620 :
node _T_621 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_27.io.enq.bits, _T_621
node _T_622 = eq(UInt<5>(0h1c), idx_8)
when _T_622 :
node _T_623 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_28.io.enq.bits, _T_623
node _T_624 = eq(UInt<5>(0h1d), idx_8)
when _T_624 :
node _T_625 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_29.io.enq.bits, _T_625
node _T_626 = eq(UInt<5>(0h1e), idx_8)
when _T_626 :
node _T_627 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_30.io.enq.bits, _T_627
node _T_628 = eq(UInt<5>(0h1f), idx_8)
when _T_628 :
node _T_629 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_31.io.enq.bits, _T_629
node _idx_T_9 = add(write_start_index, UInt<4>(0h9))
node idx_9 = rem(_idx_T_9, UInt<6>(0h20))
node _T_630 = eq(UInt<1>(0h0), idx_9)
when _T_630 :
node _T_631 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8.io.enq.bits, _T_631
node _T_632 = eq(UInt<1>(0h1), idx_9)
when _T_632 :
node _T_633 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_1.io.enq.bits, _T_633
node _T_634 = eq(UInt<2>(0h2), idx_9)
when _T_634 :
node _T_635 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_2.io.enq.bits, _T_635
node _T_636 = eq(UInt<2>(0h3), idx_9)
when _T_636 :
node _T_637 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_3.io.enq.bits, _T_637
node _T_638 = eq(UInt<3>(0h4), idx_9)
when _T_638 :
node _T_639 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_4.io.enq.bits, _T_639
node _T_640 = eq(UInt<3>(0h5), idx_9)
when _T_640 :
node _T_641 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_5.io.enq.bits, _T_641
node _T_642 = eq(UInt<3>(0h6), idx_9)
when _T_642 :
node _T_643 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_6.io.enq.bits, _T_643
node _T_644 = eq(UInt<3>(0h7), idx_9)
when _T_644 :
node _T_645 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_7.io.enq.bits, _T_645
node _T_646 = eq(UInt<4>(0h8), idx_9)
when _T_646 :
node _T_647 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_8.io.enq.bits, _T_647
node _T_648 = eq(UInt<4>(0h9), idx_9)
when _T_648 :
node _T_649 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_9.io.enq.bits, _T_649
node _T_650 = eq(UInt<4>(0ha), idx_9)
when _T_650 :
node _T_651 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_10.io.enq.bits, _T_651
node _T_652 = eq(UInt<4>(0hb), idx_9)
when _T_652 :
node _T_653 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_11.io.enq.bits, _T_653
node _T_654 = eq(UInt<4>(0hc), idx_9)
when _T_654 :
node _T_655 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_12.io.enq.bits, _T_655
node _T_656 = eq(UInt<4>(0hd), idx_9)
when _T_656 :
node _T_657 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_13.io.enq.bits, _T_657
node _T_658 = eq(UInt<4>(0he), idx_9)
when _T_658 :
node _T_659 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_14.io.enq.bits, _T_659
node _T_660 = eq(UInt<4>(0hf), idx_9)
when _T_660 :
node _T_661 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_15.io.enq.bits, _T_661
node _T_662 = eq(UInt<5>(0h10), idx_9)
when _T_662 :
node _T_663 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_16.io.enq.bits, _T_663
node _T_664 = eq(UInt<5>(0h11), idx_9)
when _T_664 :
node _T_665 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_17.io.enq.bits, _T_665
node _T_666 = eq(UInt<5>(0h12), idx_9)
when _T_666 :
node _T_667 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_18.io.enq.bits, _T_667
node _T_668 = eq(UInt<5>(0h13), idx_9)
when _T_668 :
node _T_669 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_19.io.enq.bits, _T_669
node _T_670 = eq(UInt<5>(0h14), idx_9)
when _T_670 :
node _T_671 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_20.io.enq.bits, _T_671
node _T_672 = eq(UInt<5>(0h15), idx_9)
when _T_672 :
node _T_673 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_21.io.enq.bits, _T_673
node _T_674 = eq(UInt<5>(0h16), idx_9)
when _T_674 :
node _T_675 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_22.io.enq.bits, _T_675
node _T_676 = eq(UInt<5>(0h17), idx_9)
when _T_676 :
node _T_677 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_23.io.enq.bits, _T_677
node _T_678 = eq(UInt<5>(0h18), idx_9)
when _T_678 :
node _T_679 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_24.io.enq.bits, _T_679
node _T_680 = eq(UInt<5>(0h19), idx_9)
when _T_680 :
node _T_681 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_25.io.enq.bits, _T_681
node _T_682 = eq(UInt<5>(0h1a), idx_9)
when _T_682 :
node _T_683 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_26.io.enq.bits, _T_683
node _T_684 = eq(UInt<5>(0h1b), idx_9)
when _T_684 :
node _T_685 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_27.io.enq.bits, _T_685
node _T_686 = eq(UInt<5>(0h1c), idx_9)
when _T_686 :
node _T_687 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_28.io.enq.bits, _T_687
node _T_688 = eq(UInt<5>(0h1d), idx_9)
when _T_688 :
node _T_689 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_29.io.enq.bits, _T_689
node _T_690 = eq(UInt<5>(0h1e), idx_9)
when _T_690 :
node _T_691 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_30.io.enq.bits, _T_691
node _T_692 = eq(UInt<5>(0h1f), idx_9)
when _T_692 :
node _T_693 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_31.io.enq.bits, _T_693
node _idx_T_10 = add(write_start_index, UInt<4>(0ha))
node idx_10 = rem(_idx_T_10, UInt<6>(0h20))
node _T_694 = eq(UInt<1>(0h0), idx_10)
when _T_694 :
node _T_695 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8.io.enq.bits, _T_695
node _T_696 = eq(UInt<1>(0h1), idx_10)
when _T_696 :
node _T_697 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_1.io.enq.bits, _T_697
node _T_698 = eq(UInt<2>(0h2), idx_10)
when _T_698 :
node _T_699 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_2.io.enq.bits, _T_699
node _T_700 = eq(UInt<2>(0h3), idx_10)
when _T_700 :
node _T_701 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_3.io.enq.bits, _T_701
node _T_702 = eq(UInt<3>(0h4), idx_10)
when _T_702 :
node _T_703 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_4.io.enq.bits, _T_703
node _T_704 = eq(UInt<3>(0h5), idx_10)
when _T_704 :
node _T_705 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_5.io.enq.bits, _T_705
node _T_706 = eq(UInt<3>(0h6), idx_10)
when _T_706 :
node _T_707 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_6.io.enq.bits, _T_707
node _T_708 = eq(UInt<3>(0h7), idx_10)
when _T_708 :
node _T_709 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_7.io.enq.bits, _T_709
node _T_710 = eq(UInt<4>(0h8), idx_10)
when _T_710 :
node _T_711 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_8.io.enq.bits, _T_711
node _T_712 = eq(UInt<4>(0h9), idx_10)
when _T_712 :
node _T_713 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_9.io.enq.bits, _T_713
node _T_714 = eq(UInt<4>(0ha), idx_10)
when _T_714 :
node _T_715 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_10.io.enq.bits, _T_715
node _T_716 = eq(UInt<4>(0hb), idx_10)
when _T_716 :
node _T_717 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_11.io.enq.bits, _T_717
node _T_718 = eq(UInt<4>(0hc), idx_10)
when _T_718 :
node _T_719 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_12.io.enq.bits, _T_719
node _T_720 = eq(UInt<4>(0hd), idx_10)
when _T_720 :
node _T_721 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_13.io.enq.bits, _T_721
node _T_722 = eq(UInt<4>(0he), idx_10)
when _T_722 :
node _T_723 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_14.io.enq.bits, _T_723
node _T_724 = eq(UInt<4>(0hf), idx_10)
when _T_724 :
node _T_725 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_15.io.enq.bits, _T_725
node _T_726 = eq(UInt<5>(0h10), idx_10)
when _T_726 :
node _T_727 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_16.io.enq.bits, _T_727
node _T_728 = eq(UInt<5>(0h11), idx_10)
when _T_728 :
node _T_729 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_17.io.enq.bits, _T_729
node _T_730 = eq(UInt<5>(0h12), idx_10)
when _T_730 :
node _T_731 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_18.io.enq.bits, _T_731
node _T_732 = eq(UInt<5>(0h13), idx_10)
when _T_732 :
node _T_733 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_19.io.enq.bits, _T_733
node _T_734 = eq(UInt<5>(0h14), idx_10)
when _T_734 :
node _T_735 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_20.io.enq.bits, _T_735
node _T_736 = eq(UInt<5>(0h15), idx_10)
when _T_736 :
node _T_737 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_21.io.enq.bits, _T_737
node _T_738 = eq(UInt<5>(0h16), idx_10)
when _T_738 :
node _T_739 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_22.io.enq.bits, _T_739
node _T_740 = eq(UInt<5>(0h17), idx_10)
when _T_740 :
node _T_741 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_23.io.enq.bits, _T_741
node _T_742 = eq(UInt<5>(0h18), idx_10)
when _T_742 :
node _T_743 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_24.io.enq.bits, _T_743
node _T_744 = eq(UInt<5>(0h19), idx_10)
when _T_744 :
node _T_745 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_25.io.enq.bits, _T_745
node _T_746 = eq(UInt<5>(0h1a), idx_10)
when _T_746 :
node _T_747 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_26.io.enq.bits, _T_747
node _T_748 = eq(UInt<5>(0h1b), idx_10)
when _T_748 :
node _T_749 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_27.io.enq.bits, _T_749
node _T_750 = eq(UInt<5>(0h1c), idx_10)
when _T_750 :
node _T_751 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_28.io.enq.bits, _T_751
node _T_752 = eq(UInt<5>(0h1d), idx_10)
when _T_752 :
node _T_753 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_29.io.enq.bits, _T_753
node _T_754 = eq(UInt<5>(0h1e), idx_10)
when _T_754 :
node _T_755 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_30.io.enq.bits, _T_755
node _T_756 = eq(UInt<5>(0h1f), idx_10)
when _T_756 :
node _T_757 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_31.io.enq.bits, _T_757
node _idx_T_11 = add(write_start_index, UInt<4>(0hb))
node idx_11 = rem(_idx_T_11, UInt<6>(0h20))
node _T_758 = eq(UInt<1>(0h0), idx_11)
when _T_758 :
node _T_759 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8.io.enq.bits, _T_759
node _T_760 = eq(UInt<1>(0h1), idx_11)
when _T_760 :
node _T_761 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_1.io.enq.bits, _T_761
node _T_762 = eq(UInt<2>(0h2), idx_11)
when _T_762 :
node _T_763 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_2.io.enq.bits, _T_763
node _T_764 = eq(UInt<2>(0h3), idx_11)
when _T_764 :
node _T_765 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_3.io.enq.bits, _T_765
node _T_766 = eq(UInt<3>(0h4), idx_11)
when _T_766 :
node _T_767 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_4.io.enq.bits, _T_767
node _T_768 = eq(UInt<3>(0h5), idx_11)
when _T_768 :
node _T_769 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_5.io.enq.bits, _T_769
node _T_770 = eq(UInt<3>(0h6), idx_11)
when _T_770 :
node _T_771 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_6.io.enq.bits, _T_771
node _T_772 = eq(UInt<3>(0h7), idx_11)
when _T_772 :
node _T_773 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_7.io.enq.bits, _T_773
node _T_774 = eq(UInt<4>(0h8), idx_11)
when _T_774 :
node _T_775 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_8.io.enq.bits, _T_775
node _T_776 = eq(UInt<4>(0h9), idx_11)
when _T_776 :
node _T_777 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_9.io.enq.bits, _T_777
node _T_778 = eq(UInt<4>(0ha), idx_11)
when _T_778 :
node _T_779 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_10.io.enq.bits, _T_779
node _T_780 = eq(UInt<4>(0hb), idx_11)
when _T_780 :
node _T_781 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_11.io.enq.bits, _T_781
node _T_782 = eq(UInt<4>(0hc), idx_11)
when _T_782 :
node _T_783 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_12.io.enq.bits, _T_783
node _T_784 = eq(UInt<4>(0hd), idx_11)
when _T_784 :
node _T_785 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_13.io.enq.bits, _T_785
node _T_786 = eq(UInt<4>(0he), idx_11)
when _T_786 :
node _T_787 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_14.io.enq.bits, _T_787
node _T_788 = eq(UInt<4>(0hf), idx_11)
when _T_788 :
node _T_789 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_15.io.enq.bits, _T_789
node _T_790 = eq(UInt<5>(0h10), idx_11)
when _T_790 :
node _T_791 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_16.io.enq.bits, _T_791
node _T_792 = eq(UInt<5>(0h11), idx_11)
when _T_792 :
node _T_793 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_17.io.enq.bits, _T_793
node _T_794 = eq(UInt<5>(0h12), idx_11)
when _T_794 :
node _T_795 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_18.io.enq.bits, _T_795
node _T_796 = eq(UInt<5>(0h13), idx_11)
when _T_796 :
node _T_797 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_19.io.enq.bits, _T_797
node _T_798 = eq(UInt<5>(0h14), idx_11)
when _T_798 :
node _T_799 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_20.io.enq.bits, _T_799
node _T_800 = eq(UInt<5>(0h15), idx_11)
when _T_800 :
node _T_801 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_21.io.enq.bits, _T_801
node _T_802 = eq(UInt<5>(0h16), idx_11)
when _T_802 :
node _T_803 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_22.io.enq.bits, _T_803
node _T_804 = eq(UInt<5>(0h17), idx_11)
when _T_804 :
node _T_805 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_23.io.enq.bits, _T_805
node _T_806 = eq(UInt<5>(0h18), idx_11)
when _T_806 :
node _T_807 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_24.io.enq.bits, _T_807
node _T_808 = eq(UInt<5>(0h19), idx_11)
when _T_808 :
node _T_809 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_25.io.enq.bits, _T_809
node _T_810 = eq(UInt<5>(0h1a), idx_11)
when _T_810 :
node _T_811 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_26.io.enq.bits, _T_811
node _T_812 = eq(UInt<5>(0h1b), idx_11)
when _T_812 :
node _T_813 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_27.io.enq.bits, _T_813
node _T_814 = eq(UInt<5>(0h1c), idx_11)
when _T_814 :
node _T_815 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_28.io.enq.bits, _T_815
node _T_816 = eq(UInt<5>(0h1d), idx_11)
when _T_816 :
node _T_817 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_29.io.enq.bits, _T_817
node _T_818 = eq(UInt<5>(0h1e), idx_11)
when _T_818 :
node _T_819 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_30.io.enq.bits, _T_819
node _T_820 = eq(UInt<5>(0h1f), idx_11)
when _T_820 :
node _T_821 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_31.io.enq.bits, _T_821
node _idx_T_12 = add(write_start_index, UInt<4>(0hc))
node idx_12 = rem(_idx_T_12, UInt<6>(0h20))
node _T_822 = eq(UInt<1>(0h0), idx_12)
when _T_822 :
node _T_823 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8.io.enq.bits, _T_823
node _T_824 = eq(UInt<1>(0h1), idx_12)
when _T_824 :
node _T_825 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_1.io.enq.bits, _T_825
node _T_826 = eq(UInt<2>(0h2), idx_12)
when _T_826 :
node _T_827 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_2.io.enq.bits, _T_827
node _T_828 = eq(UInt<2>(0h3), idx_12)
when _T_828 :
node _T_829 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_3.io.enq.bits, _T_829
node _T_830 = eq(UInt<3>(0h4), idx_12)
when _T_830 :
node _T_831 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_4.io.enq.bits, _T_831
node _T_832 = eq(UInt<3>(0h5), idx_12)
when _T_832 :
node _T_833 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_5.io.enq.bits, _T_833
node _T_834 = eq(UInt<3>(0h6), idx_12)
when _T_834 :
node _T_835 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_6.io.enq.bits, _T_835
node _T_836 = eq(UInt<3>(0h7), idx_12)
when _T_836 :
node _T_837 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_7.io.enq.bits, _T_837
node _T_838 = eq(UInt<4>(0h8), idx_12)
when _T_838 :
node _T_839 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_8.io.enq.bits, _T_839
node _T_840 = eq(UInt<4>(0h9), idx_12)
when _T_840 :
node _T_841 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_9.io.enq.bits, _T_841
node _T_842 = eq(UInt<4>(0ha), idx_12)
when _T_842 :
node _T_843 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_10.io.enq.bits, _T_843
node _T_844 = eq(UInt<4>(0hb), idx_12)
when _T_844 :
node _T_845 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_11.io.enq.bits, _T_845
node _T_846 = eq(UInt<4>(0hc), idx_12)
when _T_846 :
node _T_847 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_12.io.enq.bits, _T_847
node _T_848 = eq(UInt<4>(0hd), idx_12)
when _T_848 :
node _T_849 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_13.io.enq.bits, _T_849
node _T_850 = eq(UInt<4>(0he), idx_12)
when _T_850 :
node _T_851 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_14.io.enq.bits, _T_851
node _T_852 = eq(UInt<4>(0hf), idx_12)
when _T_852 :
node _T_853 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_15.io.enq.bits, _T_853
node _T_854 = eq(UInt<5>(0h10), idx_12)
when _T_854 :
node _T_855 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_16.io.enq.bits, _T_855
node _T_856 = eq(UInt<5>(0h11), idx_12)
when _T_856 :
node _T_857 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_17.io.enq.bits, _T_857
node _T_858 = eq(UInt<5>(0h12), idx_12)
when _T_858 :
node _T_859 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_18.io.enq.bits, _T_859
node _T_860 = eq(UInt<5>(0h13), idx_12)
when _T_860 :
node _T_861 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_19.io.enq.bits, _T_861
node _T_862 = eq(UInt<5>(0h14), idx_12)
when _T_862 :
node _T_863 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_20.io.enq.bits, _T_863
node _T_864 = eq(UInt<5>(0h15), idx_12)
when _T_864 :
node _T_865 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_21.io.enq.bits, _T_865
node _T_866 = eq(UInt<5>(0h16), idx_12)
when _T_866 :
node _T_867 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_22.io.enq.bits, _T_867
node _T_868 = eq(UInt<5>(0h17), idx_12)
when _T_868 :
node _T_869 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_23.io.enq.bits, _T_869
node _T_870 = eq(UInt<5>(0h18), idx_12)
when _T_870 :
node _T_871 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_24.io.enq.bits, _T_871
node _T_872 = eq(UInt<5>(0h19), idx_12)
when _T_872 :
node _T_873 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_25.io.enq.bits, _T_873
node _T_874 = eq(UInt<5>(0h1a), idx_12)
when _T_874 :
node _T_875 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_26.io.enq.bits, _T_875
node _T_876 = eq(UInt<5>(0h1b), idx_12)
when _T_876 :
node _T_877 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_27.io.enq.bits, _T_877
node _T_878 = eq(UInt<5>(0h1c), idx_12)
when _T_878 :
node _T_879 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_28.io.enq.bits, _T_879
node _T_880 = eq(UInt<5>(0h1d), idx_12)
when _T_880 :
node _T_881 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_29.io.enq.bits, _T_881
node _T_882 = eq(UInt<5>(0h1e), idx_12)
when _T_882 :
node _T_883 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_30.io.enq.bits, _T_883
node _T_884 = eq(UInt<5>(0h1f), idx_12)
when _T_884 :
node _T_885 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_31.io.enq.bits, _T_885
node _idx_T_13 = add(write_start_index, UInt<4>(0hd))
node idx_13 = rem(_idx_T_13, UInt<6>(0h20))
node _T_886 = eq(UInt<1>(0h0), idx_13)
when _T_886 :
node _T_887 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8.io.enq.bits, _T_887
node _T_888 = eq(UInt<1>(0h1), idx_13)
when _T_888 :
node _T_889 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_1.io.enq.bits, _T_889
node _T_890 = eq(UInt<2>(0h2), idx_13)
when _T_890 :
node _T_891 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_2.io.enq.bits, _T_891
node _T_892 = eq(UInt<2>(0h3), idx_13)
when _T_892 :
node _T_893 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_3.io.enq.bits, _T_893
node _T_894 = eq(UInt<3>(0h4), idx_13)
when _T_894 :
node _T_895 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_4.io.enq.bits, _T_895
node _T_896 = eq(UInt<3>(0h5), idx_13)
when _T_896 :
node _T_897 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_5.io.enq.bits, _T_897
node _T_898 = eq(UInt<3>(0h6), idx_13)
when _T_898 :
node _T_899 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_6.io.enq.bits, _T_899
node _T_900 = eq(UInt<3>(0h7), idx_13)
when _T_900 :
node _T_901 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_7.io.enq.bits, _T_901
node _T_902 = eq(UInt<4>(0h8), idx_13)
when _T_902 :
node _T_903 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_8.io.enq.bits, _T_903
node _T_904 = eq(UInt<4>(0h9), idx_13)
when _T_904 :
node _T_905 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_9.io.enq.bits, _T_905
node _T_906 = eq(UInt<4>(0ha), idx_13)
when _T_906 :
node _T_907 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_10.io.enq.bits, _T_907
node _T_908 = eq(UInt<4>(0hb), idx_13)
when _T_908 :
node _T_909 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_11.io.enq.bits, _T_909
node _T_910 = eq(UInt<4>(0hc), idx_13)
when _T_910 :
node _T_911 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_12.io.enq.bits, _T_911
node _T_912 = eq(UInt<4>(0hd), idx_13)
when _T_912 :
node _T_913 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_13.io.enq.bits, _T_913
node _T_914 = eq(UInt<4>(0he), idx_13)
when _T_914 :
node _T_915 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_14.io.enq.bits, _T_915
node _T_916 = eq(UInt<4>(0hf), idx_13)
when _T_916 :
node _T_917 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_15.io.enq.bits, _T_917
node _T_918 = eq(UInt<5>(0h10), idx_13)
when _T_918 :
node _T_919 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_16.io.enq.bits, _T_919
node _T_920 = eq(UInt<5>(0h11), idx_13)
when _T_920 :
node _T_921 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_17.io.enq.bits, _T_921
node _T_922 = eq(UInt<5>(0h12), idx_13)
when _T_922 :
node _T_923 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_18.io.enq.bits, _T_923
node _T_924 = eq(UInt<5>(0h13), idx_13)
when _T_924 :
node _T_925 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_19.io.enq.bits, _T_925
node _T_926 = eq(UInt<5>(0h14), idx_13)
when _T_926 :
node _T_927 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_20.io.enq.bits, _T_927
node _T_928 = eq(UInt<5>(0h15), idx_13)
when _T_928 :
node _T_929 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_21.io.enq.bits, _T_929
node _T_930 = eq(UInt<5>(0h16), idx_13)
when _T_930 :
node _T_931 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_22.io.enq.bits, _T_931
node _T_932 = eq(UInt<5>(0h17), idx_13)
when _T_932 :
node _T_933 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_23.io.enq.bits, _T_933
node _T_934 = eq(UInt<5>(0h18), idx_13)
when _T_934 :
node _T_935 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_24.io.enq.bits, _T_935
node _T_936 = eq(UInt<5>(0h19), idx_13)
when _T_936 :
node _T_937 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_25.io.enq.bits, _T_937
node _T_938 = eq(UInt<5>(0h1a), idx_13)
when _T_938 :
node _T_939 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_26.io.enq.bits, _T_939
node _T_940 = eq(UInt<5>(0h1b), idx_13)
when _T_940 :
node _T_941 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_27.io.enq.bits, _T_941
node _T_942 = eq(UInt<5>(0h1c), idx_13)
when _T_942 :
node _T_943 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_28.io.enq.bits, _T_943
node _T_944 = eq(UInt<5>(0h1d), idx_13)
when _T_944 :
node _T_945 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_29.io.enq.bits, _T_945
node _T_946 = eq(UInt<5>(0h1e), idx_13)
when _T_946 :
node _T_947 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_30.io.enq.bits, _T_947
node _T_948 = eq(UInt<5>(0h1f), idx_13)
when _T_948 :
node _T_949 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_31.io.enq.bits, _T_949
node _idx_T_14 = add(write_start_index, UInt<4>(0he))
node idx_14 = rem(_idx_T_14, UInt<6>(0h20))
node _T_950 = eq(UInt<1>(0h0), idx_14)
when _T_950 :
node _T_951 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8.io.enq.bits, _T_951
node _T_952 = eq(UInt<1>(0h1), idx_14)
when _T_952 :
node _T_953 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_1.io.enq.bits, _T_953
node _T_954 = eq(UInt<2>(0h2), idx_14)
when _T_954 :
node _T_955 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_2.io.enq.bits, _T_955
node _T_956 = eq(UInt<2>(0h3), idx_14)
when _T_956 :
node _T_957 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_3.io.enq.bits, _T_957
node _T_958 = eq(UInt<3>(0h4), idx_14)
when _T_958 :
node _T_959 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_4.io.enq.bits, _T_959
node _T_960 = eq(UInt<3>(0h5), idx_14)
when _T_960 :
node _T_961 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_5.io.enq.bits, _T_961
node _T_962 = eq(UInt<3>(0h6), idx_14)
when _T_962 :
node _T_963 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_6.io.enq.bits, _T_963
node _T_964 = eq(UInt<3>(0h7), idx_14)
when _T_964 :
node _T_965 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_7.io.enq.bits, _T_965
node _T_966 = eq(UInt<4>(0h8), idx_14)
when _T_966 :
node _T_967 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_8.io.enq.bits, _T_967
node _T_968 = eq(UInt<4>(0h9), idx_14)
when _T_968 :
node _T_969 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_9.io.enq.bits, _T_969
node _T_970 = eq(UInt<4>(0ha), idx_14)
when _T_970 :
node _T_971 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_10.io.enq.bits, _T_971
node _T_972 = eq(UInt<4>(0hb), idx_14)
when _T_972 :
node _T_973 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_11.io.enq.bits, _T_973
node _T_974 = eq(UInt<4>(0hc), idx_14)
when _T_974 :
node _T_975 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_12.io.enq.bits, _T_975
node _T_976 = eq(UInt<4>(0hd), idx_14)
when _T_976 :
node _T_977 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_13.io.enq.bits, _T_977
node _T_978 = eq(UInt<4>(0he), idx_14)
when _T_978 :
node _T_979 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_14.io.enq.bits, _T_979
node _T_980 = eq(UInt<4>(0hf), idx_14)
when _T_980 :
node _T_981 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_15.io.enq.bits, _T_981
node _T_982 = eq(UInt<5>(0h10), idx_14)
when _T_982 :
node _T_983 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_16.io.enq.bits, _T_983
node _T_984 = eq(UInt<5>(0h11), idx_14)
when _T_984 :
node _T_985 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_17.io.enq.bits, _T_985
node _T_986 = eq(UInt<5>(0h12), idx_14)
when _T_986 :
node _T_987 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_18.io.enq.bits, _T_987
node _T_988 = eq(UInt<5>(0h13), idx_14)
when _T_988 :
node _T_989 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_19.io.enq.bits, _T_989
node _T_990 = eq(UInt<5>(0h14), idx_14)
when _T_990 :
node _T_991 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_20.io.enq.bits, _T_991
node _T_992 = eq(UInt<5>(0h15), idx_14)
when _T_992 :
node _T_993 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_21.io.enq.bits, _T_993
node _T_994 = eq(UInt<5>(0h16), idx_14)
when _T_994 :
node _T_995 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_22.io.enq.bits, _T_995
node _T_996 = eq(UInt<5>(0h17), idx_14)
when _T_996 :
node _T_997 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_23.io.enq.bits, _T_997
node _T_998 = eq(UInt<5>(0h18), idx_14)
when _T_998 :
node _T_999 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_24.io.enq.bits, _T_999
node _T_1000 = eq(UInt<5>(0h19), idx_14)
when _T_1000 :
node _T_1001 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_25.io.enq.bits, _T_1001
node _T_1002 = eq(UInt<5>(0h1a), idx_14)
when _T_1002 :
node _T_1003 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_26.io.enq.bits, _T_1003
node _T_1004 = eq(UInt<5>(0h1b), idx_14)
when _T_1004 :
node _T_1005 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_27.io.enq.bits, _T_1005
node _T_1006 = eq(UInt<5>(0h1c), idx_14)
when _T_1006 :
node _T_1007 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_28.io.enq.bits, _T_1007
node _T_1008 = eq(UInt<5>(0h1d), idx_14)
when _T_1008 :
node _T_1009 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_29.io.enq.bits, _T_1009
node _T_1010 = eq(UInt<5>(0h1e), idx_14)
when _T_1010 :
node _T_1011 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_30.io.enq.bits, _T_1011
node _T_1012 = eq(UInt<5>(0h1f), idx_14)
when _T_1012 :
node _T_1013 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_31.io.enq.bits, _T_1013
node _idx_T_15 = add(write_start_index, UInt<4>(0hf))
node idx_15 = rem(_idx_T_15, UInt<6>(0h20))
node _T_1014 = eq(UInt<1>(0h0), idx_15)
when _T_1014 :
node _T_1015 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8.io.enq.bits, _T_1015
node _T_1016 = eq(UInt<1>(0h1), idx_15)
when _T_1016 :
node _T_1017 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_1.io.enq.bits, _T_1017
node _T_1018 = eq(UInt<2>(0h2), idx_15)
when _T_1018 :
node _T_1019 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_2.io.enq.bits, _T_1019
node _T_1020 = eq(UInt<2>(0h3), idx_15)
when _T_1020 :
node _T_1021 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_3.io.enq.bits, _T_1021
node _T_1022 = eq(UInt<3>(0h4), idx_15)
when _T_1022 :
node _T_1023 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_4.io.enq.bits, _T_1023
node _T_1024 = eq(UInt<3>(0h5), idx_15)
when _T_1024 :
node _T_1025 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_5.io.enq.bits, _T_1025
node _T_1026 = eq(UInt<3>(0h6), idx_15)
when _T_1026 :
node _T_1027 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_6.io.enq.bits, _T_1027
node _T_1028 = eq(UInt<3>(0h7), idx_15)
when _T_1028 :
node _T_1029 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_7.io.enq.bits, _T_1029
node _T_1030 = eq(UInt<4>(0h8), idx_15)
when _T_1030 :
node _T_1031 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_8.io.enq.bits, _T_1031
node _T_1032 = eq(UInt<4>(0h9), idx_15)
when _T_1032 :
node _T_1033 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_9.io.enq.bits, _T_1033
node _T_1034 = eq(UInt<4>(0ha), idx_15)
when _T_1034 :
node _T_1035 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_10.io.enq.bits, _T_1035
node _T_1036 = eq(UInt<4>(0hb), idx_15)
when _T_1036 :
node _T_1037 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_11.io.enq.bits, _T_1037
node _T_1038 = eq(UInt<4>(0hc), idx_15)
when _T_1038 :
node _T_1039 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_12.io.enq.bits, _T_1039
node _T_1040 = eq(UInt<4>(0hd), idx_15)
when _T_1040 :
node _T_1041 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_13.io.enq.bits, _T_1041
node _T_1042 = eq(UInt<4>(0he), idx_15)
when _T_1042 :
node _T_1043 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_14.io.enq.bits, _T_1043
node _T_1044 = eq(UInt<4>(0hf), idx_15)
when _T_1044 :
node _T_1045 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_15.io.enq.bits, _T_1045
node _T_1046 = eq(UInt<5>(0h10), idx_15)
when _T_1046 :
node _T_1047 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_16.io.enq.bits, _T_1047
node _T_1048 = eq(UInt<5>(0h11), idx_15)
when _T_1048 :
node _T_1049 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_17.io.enq.bits, _T_1049
node _T_1050 = eq(UInt<5>(0h12), idx_15)
when _T_1050 :
node _T_1051 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_18.io.enq.bits, _T_1051
node _T_1052 = eq(UInt<5>(0h13), idx_15)
when _T_1052 :
node _T_1053 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_19.io.enq.bits, _T_1053
node _T_1054 = eq(UInt<5>(0h14), idx_15)
when _T_1054 :
node _T_1055 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_20.io.enq.bits, _T_1055
node _T_1056 = eq(UInt<5>(0h15), idx_15)
when _T_1056 :
node _T_1057 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_21.io.enq.bits, _T_1057
node _T_1058 = eq(UInt<5>(0h16), idx_15)
when _T_1058 :
node _T_1059 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_22.io.enq.bits, _T_1059
node _T_1060 = eq(UInt<5>(0h17), idx_15)
when _T_1060 :
node _T_1061 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_23.io.enq.bits, _T_1061
node _T_1062 = eq(UInt<5>(0h18), idx_15)
when _T_1062 :
node _T_1063 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_24.io.enq.bits, _T_1063
node _T_1064 = eq(UInt<5>(0h19), idx_15)
when _T_1064 :
node _T_1065 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_25.io.enq.bits, _T_1065
node _T_1066 = eq(UInt<5>(0h1a), idx_15)
when _T_1066 :
node _T_1067 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_26.io.enq.bits, _T_1067
node _T_1068 = eq(UInt<5>(0h1b), idx_15)
when _T_1068 :
node _T_1069 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_27.io.enq.bits, _T_1069
node _T_1070 = eq(UInt<5>(0h1c), idx_15)
when _T_1070 :
node _T_1071 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_28.io.enq.bits, _T_1071
node _T_1072 = eq(UInt<5>(0h1d), idx_15)
when _T_1072 :
node _T_1073 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_29.io.enq.bits, _T_1073
node _T_1074 = eq(UInt<5>(0h1e), idx_15)
when _T_1074 :
node _T_1075 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_30.io.enq.bits, _T_1075
node _T_1076 = eq(UInt<5>(0h1f), idx_15)
when _T_1076 :
node _T_1077 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_31.io.enq.bits, _T_1077
node _idx_T_16 = add(write_start_index, UInt<5>(0h10))
node idx_16 = rem(_idx_T_16, UInt<6>(0h20))
node _T_1078 = eq(UInt<1>(0h0), idx_16)
when _T_1078 :
node _T_1079 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8.io.enq.bits, _T_1079
node _T_1080 = eq(UInt<1>(0h1), idx_16)
when _T_1080 :
node _T_1081 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_1.io.enq.bits, _T_1081
node _T_1082 = eq(UInt<2>(0h2), idx_16)
when _T_1082 :
node _T_1083 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_2.io.enq.bits, _T_1083
node _T_1084 = eq(UInt<2>(0h3), idx_16)
when _T_1084 :
node _T_1085 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_3.io.enq.bits, _T_1085
node _T_1086 = eq(UInt<3>(0h4), idx_16)
when _T_1086 :
node _T_1087 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_4.io.enq.bits, _T_1087
node _T_1088 = eq(UInt<3>(0h5), idx_16)
when _T_1088 :
node _T_1089 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_5.io.enq.bits, _T_1089
node _T_1090 = eq(UInt<3>(0h6), idx_16)
when _T_1090 :
node _T_1091 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_6.io.enq.bits, _T_1091
node _T_1092 = eq(UInt<3>(0h7), idx_16)
when _T_1092 :
node _T_1093 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_7.io.enq.bits, _T_1093
node _T_1094 = eq(UInt<4>(0h8), idx_16)
when _T_1094 :
node _T_1095 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_8.io.enq.bits, _T_1095
node _T_1096 = eq(UInt<4>(0h9), idx_16)
when _T_1096 :
node _T_1097 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_9.io.enq.bits, _T_1097
node _T_1098 = eq(UInt<4>(0ha), idx_16)
when _T_1098 :
node _T_1099 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_10.io.enq.bits, _T_1099
node _T_1100 = eq(UInt<4>(0hb), idx_16)
when _T_1100 :
node _T_1101 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_11.io.enq.bits, _T_1101
node _T_1102 = eq(UInt<4>(0hc), idx_16)
when _T_1102 :
node _T_1103 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_12.io.enq.bits, _T_1103
node _T_1104 = eq(UInt<4>(0hd), idx_16)
when _T_1104 :
node _T_1105 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_13.io.enq.bits, _T_1105
node _T_1106 = eq(UInt<4>(0he), idx_16)
when _T_1106 :
node _T_1107 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_14.io.enq.bits, _T_1107
node _T_1108 = eq(UInt<4>(0hf), idx_16)
when _T_1108 :
node _T_1109 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_15.io.enq.bits, _T_1109
node _T_1110 = eq(UInt<5>(0h10), idx_16)
when _T_1110 :
node _T_1111 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_16.io.enq.bits, _T_1111
node _T_1112 = eq(UInt<5>(0h11), idx_16)
when _T_1112 :
node _T_1113 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_17.io.enq.bits, _T_1113
node _T_1114 = eq(UInt<5>(0h12), idx_16)
when _T_1114 :
node _T_1115 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_18.io.enq.bits, _T_1115
node _T_1116 = eq(UInt<5>(0h13), idx_16)
when _T_1116 :
node _T_1117 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_19.io.enq.bits, _T_1117
node _T_1118 = eq(UInt<5>(0h14), idx_16)
when _T_1118 :
node _T_1119 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_20.io.enq.bits, _T_1119
node _T_1120 = eq(UInt<5>(0h15), idx_16)
when _T_1120 :
node _T_1121 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_21.io.enq.bits, _T_1121
node _T_1122 = eq(UInt<5>(0h16), idx_16)
when _T_1122 :
node _T_1123 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_22.io.enq.bits, _T_1123
node _T_1124 = eq(UInt<5>(0h17), idx_16)
when _T_1124 :
node _T_1125 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_23.io.enq.bits, _T_1125
node _T_1126 = eq(UInt<5>(0h18), idx_16)
when _T_1126 :
node _T_1127 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_24.io.enq.bits, _T_1127
node _T_1128 = eq(UInt<5>(0h19), idx_16)
when _T_1128 :
node _T_1129 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_25.io.enq.bits, _T_1129
node _T_1130 = eq(UInt<5>(0h1a), idx_16)
when _T_1130 :
node _T_1131 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_26.io.enq.bits, _T_1131
node _T_1132 = eq(UInt<5>(0h1b), idx_16)
when _T_1132 :
node _T_1133 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_27.io.enq.bits, _T_1133
node _T_1134 = eq(UInt<5>(0h1c), idx_16)
when _T_1134 :
node _T_1135 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_28.io.enq.bits, _T_1135
node _T_1136 = eq(UInt<5>(0h1d), idx_16)
when _T_1136 :
node _T_1137 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_29.io.enq.bits, _T_1137
node _T_1138 = eq(UInt<5>(0h1e), idx_16)
when _T_1138 :
node _T_1139 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_30.io.enq.bits, _T_1139
node _T_1140 = eq(UInt<5>(0h1f), idx_16)
when _T_1140 :
node _T_1141 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_31.io.enq.bits, _T_1141
node _idx_T_17 = add(write_start_index, UInt<5>(0h11))
node idx_17 = rem(_idx_T_17, UInt<6>(0h20))
node _T_1142 = eq(UInt<1>(0h0), idx_17)
when _T_1142 :
node _T_1143 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8.io.enq.bits, _T_1143
node _T_1144 = eq(UInt<1>(0h1), idx_17)
when _T_1144 :
node _T_1145 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_1.io.enq.bits, _T_1145
node _T_1146 = eq(UInt<2>(0h2), idx_17)
when _T_1146 :
node _T_1147 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_2.io.enq.bits, _T_1147
node _T_1148 = eq(UInt<2>(0h3), idx_17)
when _T_1148 :
node _T_1149 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_3.io.enq.bits, _T_1149
node _T_1150 = eq(UInt<3>(0h4), idx_17)
when _T_1150 :
node _T_1151 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_4.io.enq.bits, _T_1151
node _T_1152 = eq(UInt<3>(0h5), idx_17)
when _T_1152 :
node _T_1153 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_5.io.enq.bits, _T_1153
node _T_1154 = eq(UInt<3>(0h6), idx_17)
when _T_1154 :
node _T_1155 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_6.io.enq.bits, _T_1155
node _T_1156 = eq(UInt<3>(0h7), idx_17)
when _T_1156 :
node _T_1157 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_7.io.enq.bits, _T_1157
node _T_1158 = eq(UInt<4>(0h8), idx_17)
when _T_1158 :
node _T_1159 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_8.io.enq.bits, _T_1159
node _T_1160 = eq(UInt<4>(0h9), idx_17)
when _T_1160 :
node _T_1161 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_9.io.enq.bits, _T_1161
node _T_1162 = eq(UInt<4>(0ha), idx_17)
when _T_1162 :
node _T_1163 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_10.io.enq.bits, _T_1163
node _T_1164 = eq(UInt<4>(0hb), idx_17)
when _T_1164 :
node _T_1165 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_11.io.enq.bits, _T_1165
node _T_1166 = eq(UInt<4>(0hc), idx_17)
when _T_1166 :
node _T_1167 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_12.io.enq.bits, _T_1167
node _T_1168 = eq(UInt<4>(0hd), idx_17)
when _T_1168 :
node _T_1169 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_13.io.enq.bits, _T_1169
node _T_1170 = eq(UInt<4>(0he), idx_17)
when _T_1170 :
node _T_1171 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_14.io.enq.bits, _T_1171
node _T_1172 = eq(UInt<4>(0hf), idx_17)
when _T_1172 :
node _T_1173 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_15.io.enq.bits, _T_1173
node _T_1174 = eq(UInt<5>(0h10), idx_17)
when _T_1174 :
node _T_1175 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_16.io.enq.bits, _T_1175
node _T_1176 = eq(UInt<5>(0h11), idx_17)
when _T_1176 :
node _T_1177 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_17.io.enq.bits, _T_1177
node _T_1178 = eq(UInt<5>(0h12), idx_17)
when _T_1178 :
node _T_1179 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_18.io.enq.bits, _T_1179
node _T_1180 = eq(UInt<5>(0h13), idx_17)
when _T_1180 :
node _T_1181 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_19.io.enq.bits, _T_1181
node _T_1182 = eq(UInt<5>(0h14), idx_17)
when _T_1182 :
node _T_1183 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_20.io.enq.bits, _T_1183
node _T_1184 = eq(UInt<5>(0h15), idx_17)
when _T_1184 :
node _T_1185 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_21.io.enq.bits, _T_1185
node _T_1186 = eq(UInt<5>(0h16), idx_17)
when _T_1186 :
node _T_1187 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_22.io.enq.bits, _T_1187
node _T_1188 = eq(UInt<5>(0h17), idx_17)
when _T_1188 :
node _T_1189 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_23.io.enq.bits, _T_1189
node _T_1190 = eq(UInt<5>(0h18), idx_17)
when _T_1190 :
node _T_1191 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_24.io.enq.bits, _T_1191
node _T_1192 = eq(UInt<5>(0h19), idx_17)
when _T_1192 :
node _T_1193 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_25.io.enq.bits, _T_1193
node _T_1194 = eq(UInt<5>(0h1a), idx_17)
when _T_1194 :
node _T_1195 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_26.io.enq.bits, _T_1195
node _T_1196 = eq(UInt<5>(0h1b), idx_17)
when _T_1196 :
node _T_1197 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_27.io.enq.bits, _T_1197
node _T_1198 = eq(UInt<5>(0h1c), idx_17)
when _T_1198 :
node _T_1199 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_28.io.enq.bits, _T_1199
node _T_1200 = eq(UInt<5>(0h1d), idx_17)
when _T_1200 :
node _T_1201 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_29.io.enq.bits, _T_1201
node _T_1202 = eq(UInt<5>(0h1e), idx_17)
when _T_1202 :
node _T_1203 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_30.io.enq.bits, _T_1203
node _T_1204 = eq(UInt<5>(0h1f), idx_17)
when _T_1204 :
node _T_1205 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_31.io.enq.bits, _T_1205
node _idx_T_18 = add(write_start_index, UInt<5>(0h12))
node idx_18 = rem(_idx_T_18, UInt<6>(0h20))
node _T_1206 = eq(UInt<1>(0h0), idx_18)
when _T_1206 :
node _T_1207 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8.io.enq.bits, _T_1207
node _T_1208 = eq(UInt<1>(0h1), idx_18)
when _T_1208 :
node _T_1209 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_1.io.enq.bits, _T_1209
node _T_1210 = eq(UInt<2>(0h2), idx_18)
when _T_1210 :
node _T_1211 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_2.io.enq.bits, _T_1211
node _T_1212 = eq(UInt<2>(0h3), idx_18)
when _T_1212 :
node _T_1213 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_3.io.enq.bits, _T_1213
node _T_1214 = eq(UInt<3>(0h4), idx_18)
when _T_1214 :
node _T_1215 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_4.io.enq.bits, _T_1215
node _T_1216 = eq(UInt<3>(0h5), idx_18)
when _T_1216 :
node _T_1217 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_5.io.enq.bits, _T_1217
node _T_1218 = eq(UInt<3>(0h6), idx_18)
when _T_1218 :
node _T_1219 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_6.io.enq.bits, _T_1219
node _T_1220 = eq(UInt<3>(0h7), idx_18)
when _T_1220 :
node _T_1221 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_7.io.enq.bits, _T_1221
node _T_1222 = eq(UInt<4>(0h8), idx_18)
when _T_1222 :
node _T_1223 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_8.io.enq.bits, _T_1223
node _T_1224 = eq(UInt<4>(0h9), idx_18)
when _T_1224 :
node _T_1225 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_9.io.enq.bits, _T_1225
node _T_1226 = eq(UInt<4>(0ha), idx_18)
when _T_1226 :
node _T_1227 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_10.io.enq.bits, _T_1227
node _T_1228 = eq(UInt<4>(0hb), idx_18)
when _T_1228 :
node _T_1229 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_11.io.enq.bits, _T_1229
node _T_1230 = eq(UInt<4>(0hc), idx_18)
when _T_1230 :
node _T_1231 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_12.io.enq.bits, _T_1231
node _T_1232 = eq(UInt<4>(0hd), idx_18)
when _T_1232 :
node _T_1233 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_13.io.enq.bits, _T_1233
node _T_1234 = eq(UInt<4>(0he), idx_18)
when _T_1234 :
node _T_1235 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_14.io.enq.bits, _T_1235
node _T_1236 = eq(UInt<4>(0hf), idx_18)
when _T_1236 :
node _T_1237 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_15.io.enq.bits, _T_1237
node _T_1238 = eq(UInt<5>(0h10), idx_18)
when _T_1238 :
node _T_1239 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_16.io.enq.bits, _T_1239
node _T_1240 = eq(UInt<5>(0h11), idx_18)
when _T_1240 :
node _T_1241 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_17.io.enq.bits, _T_1241
node _T_1242 = eq(UInt<5>(0h12), idx_18)
when _T_1242 :
node _T_1243 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_18.io.enq.bits, _T_1243
node _T_1244 = eq(UInt<5>(0h13), idx_18)
when _T_1244 :
node _T_1245 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_19.io.enq.bits, _T_1245
node _T_1246 = eq(UInt<5>(0h14), idx_18)
when _T_1246 :
node _T_1247 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_20.io.enq.bits, _T_1247
node _T_1248 = eq(UInt<5>(0h15), idx_18)
when _T_1248 :
node _T_1249 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_21.io.enq.bits, _T_1249
node _T_1250 = eq(UInt<5>(0h16), idx_18)
when _T_1250 :
node _T_1251 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_22.io.enq.bits, _T_1251
node _T_1252 = eq(UInt<5>(0h17), idx_18)
when _T_1252 :
node _T_1253 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_23.io.enq.bits, _T_1253
node _T_1254 = eq(UInt<5>(0h18), idx_18)
when _T_1254 :
node _T_1255 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_24.io.enq.bits, _T_1255
node _T_1256 = eq(UInt<5>(0h19), idx_18)
when _T_1256 :
node _T_1257 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_25.io.enq.bits, _T_1257
node _T_1258 = eq(UInt<5>(0h1a), idx_18)
when _T_1258 :
node _T_1259 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_26.io.enq.bits, _T_1259
node _T_1260 = eq(UInt<5>(0h1b), idx_18)
when _T_1260 :
node _T_1261 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_27.io.enq.bits, _T_1261
node _T_1262 = eq(UInt<5>(0h1c), idx_18)
when _T_1262 :
node _T_1263 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_28.io.enq.bits, _T_1263
node _T_1264 = eq(UInt<5>(0h1d), idx_18)
when _T_1264 :
node _T_1265 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_29.io.enq.bits, _T_1265
node _T_1266 = eq(UInt<5>(0h1e), idx_18)
when _T_1266 :
node _T_1267 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_30.io.enq.bits, _T_1267
node _T_1268 = eq(UInt<5>(0h1f), idx_18)
when _T_1268 :
node _T_1269 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_31.io.enq.bits, _T_1269
node _idx_T_19 = add(write_start_index, UInt<5>(0h13))
node idx_19 = rem(_idx_T_19, UInt<6>(0h20))
node _T_1270 = eq(UInt<1>(0h0), idx_19)
when _T_1270 :
node _T_1271 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8.io.enq.bits, _T_1271
node _T_1272 = eq(UInt<1>(0h1), idx_19)
when _T_1272 :
node _T_1273 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_1.io.enq.bits, _T_1273
node _T_1274 = eq(UInt<2>(0h2), idx_19)
when _T_1274 :
node _T_1275 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_2.io.enq.bits, _T_1275
node _T_1276 = eq(UInt<2>(0h3), idx_19)
when _T_1276 :
node _T_1277 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_3.io.enq.bits, _T_1277
node _T_1278 = eq(UInt<3>(0h4), idx_19)
when _T_1278 :
node _T_1279 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_4.io.enq.bits, _T_1279
node _T_1280 = eq(UInt<3>(0h5), idx_19)
when _T_1280 :
node _T_1281 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_5.io.enq.bits, _T_1281
node _T_1282 = eq(UInt<3>(0h6), idx_19)
when _T_1282 :
node _T_1283 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_6.io.enq.bits, _T_1283
node _T_1284 = eq(UInt<3>(0h7), idx_19)
when _T_1284 :
node _T_1285 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_7.io.enq.bits, _T_1285
node _T_1286 = eq(UInt<4>(0h8), idx_19)
when _T_1286 :
node _T_1287 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_8.io.enq.bits, _T_1287
node _T_1288 = eq(UInt<4>(0h9), idx_19)
when _T_1288 :
node _T_1289 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_9.io.enq.bits, _T_1289
node _T_1290 = eq(UInt<4>(0ha), idx_19)
when _T_1290 :
node _T_1291 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_10.io.enq.bits, _T_1291
node _T_1292 = eq(UInt<4>(0hb), idx_19)
when _T_1292 :
node _T_1293 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_11.io.enq.bits, _T_1293
node _T_1294 = eq(UInt<4>(0hc), idx_19)
when _T_1294 :
node _T_1295 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_12.io.enq.bits, _T_1295
node _T_1296 = eq(UInt<4>(0hd), idx_19)
when _T_1296 :
node _T_1297 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_13.io.enq.bits, _T_1297
node _T_1298 = eq(UInt<4>(0he), idx_19)
when _T_1298 :
node _T_1299 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_14.io.enq.bits, _T_1299
node _T_1300 = eq(UInt<4>(0hf), idx_19)
when _T_1300 :
node _T_1301 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_15.io.enq.bits, _T_1301
node _T_1302 = eq(UInt<5>(0h10), idx_19)
when _T_1302 :
node _T_1303 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_16.io.enq.bits, _T_1303
node _T_1304 = eq(UInt<5>(0h11), idx_19)
when _T_1304 :
node _T_1305 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_17.io.enq.bits, _T_1305
node _T_1306 = eq(UInt<5>(0h12), idx_19)
when _T_1306 :
node _T_1307 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_18.io.enq.bits, _T_1307
node _T_1308 = eq(UInt<5>(0h13), idx_19)
when _T_1308 :
node _T_1309 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_19.io.enq.bits, _T_1309
node _T_1310 = eq(UInt<5>(0h14), idx_19)
when _T_1310 :
node _T_1311 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_20.io.enq.bits, _T_1311
node _T_1312 = eq(UInt<5>(0h15), idx_19)
when _T_1312 :
node _T_1313 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_21.io.enq.bits, _T_1313
node _T_1314 = eq(UInt<5>(0h16), idx_19)
when _T_1314 :
node _T_1315 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_22.io.enq.bits, _T_1315
node _T_1316 = eq(UInt<5>(0h17), idx_19)
when _T_1316 :
node _T_1317 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_23.io.enq.bits, _T_1317
node _T_1318 = eq(UInt<5>(0h18), idx_19)
when _T_1318 :
node _T_1319 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_24.io.enq.bits, _T_1319
node _T_1320 = eq(UInt<5>(0h19), idx_19)
when _T_1320 :
node _T_1321 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_25.io.enq.bits, _T_1321
node _T_1322 = eq(UInt<5>(0h1a), idx_19)
when _T_1322 :
node _T_1323 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_26.io.enq.bits, _T_1323
node _T_1324 = eq(UInt<5>(0h1b), idx_19)
when _T_1324 :
node _T_1325 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_27.io.enq.bits, _T_1325
node _T_1326 = eq(UInt<5>(0h1c), idx_19)
when _T_1326 :
node _T_1327 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_28.io.enq.bits, _T_1327
node _T_1328 = eq(UInt<5>(0h1d), idx_19)
when _T_1328 :
node _T_1329 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_29.io.enq.bits, _T_1329
node _T_1330 = eq(UInt<5>(0h1e), idx_19)
when _T_1330 :
node _T_1331 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_30.io.enq.bits, _T_1331
node _T_1332 = eq(UInt<5>(0h1f), idx_19)
when _T_1332 :
node _T_1333 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_31.io.enq.bits, _T_1333
node _idx_T_20 = add(write_start_index, UInt<5>(0h14))
node idx_20 = rem(_idx_T_20, UInt<6>(0h20))
node _T_1334 = eq(UInt<1>(0h0), idx_20)
when _T_1334 :
node _T_1335 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8.io.enq.bits, _T_1335
node _T_1336 = eq(UInt<1>(0h1), idx_20)
when _T_1336 :
node _T_1337 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_1.io.enq.bits, _T_1337
node _T_1338 = eq(UInt<2>(0h2), idx_20)
when _T_1338 :
node _T_1339 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_2.io.enq.bits, _T_1339
node _T_1340 = eq(UInt<2>(0h3), idx_20)
when _T_1340 :
node _T_1341 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_3.io.enq.bits, _T_1341
node _T_1342 = eq(UInt<3>(0h4), idx_20)
when _T_1342 :
node _T_1343 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_4.io.enq.bits, _T_1343
node _T_1344 = eq(UInt<3>(0h5), idx_20)
when _T_1344 :
node _T_1345 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_5.io.enq.bits, _T_1345
node _T_1346 = eq(UInt<3>(0h6), idx_20)
when _T_1346 :
node _T_1347 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_6.io.enq.bits, _T_1347
node _T_1348 = eq(UInt<3>(0h7), idx_20)
when _T_1348 :
node _T_1349 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_7.io.enq.bits, _T_1349
node _T_1350 = eq(UInt<4>(0h8), idx_20)
when _T_1350 :
node _T_1351 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_8.io.enq.bits, _T_1351
node _T_1352 = eq(UInt<4>(0h9), idx_20)
when _T_1352 :
node _T_1353 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_9.io.enq.bits, _T_1353
node _T_1354 = eq(UInt<4>(0ha), idx_20)
when _T_1354 :
node _T_1355 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_10.io.enq.bits, _T_1355
node _T_1356 = eq(UInt<4>(0hb), idx_20)
when _T_1356 :
node _T_1357 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_11.io.enq.bits, _T_1357
node _T_1358 = eq(UInt<4>(0hc), idx_20)
when _T_1358 :
node _T_1359 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_12.io.enq.bits, _T_1359
node _T_1360 = eq(UInt<4>(0hd), idx_20)
when _T_1360 :
node _T_1361 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_13.io.enq.bits, _T_1361
node _T_1362 = eq(UInt<4>(0he), idx_20)
when _T_1362 :
node _T_1363 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_14.io.enq.bits, _T_1363
node _T_1364 = eq(UInt<4>(0hf), idx_20)
when _T_1364 :
node _T_1365 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_15.io.enq.bits, _T_1365
node _T_1366 = eq(UInt<5>(0h10), idx_20)
when _T_1366 :
node _T_1367 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_16.io.enq.bits, _T_1367
node _T_1368 = eq(UInt<5>(0h11), idx_20)
when _T_1368 :
node _T_1369 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_17.io.enq.bits, _T_1369
node _T_1370 = eq(UInt<5>(0h12), idx_20)
when _T_1370 :
node _T_1371 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_18.io.enq.bits, _T_1371
node _T_1372 = eq(UInt<5>(0h13), idx_20)
when _T_1372 :
node _T_1373 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_19.io.enq.bits, _T_1373
node _T_1374 = eq(UInt<5>(0h14), idx_20)
when _T_1374 :
node _T_1375 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_20.io.enq.bits, _T_1375
node _T_1376 = eq(UInt<5>(0h15), idx_20)
when _T_1376 :
node _T_1377 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_21.io.enq.bits, _T_1377
node _T_1378 = eq(UInt<5>(0h16), idx_20)
when _T_1378 :
node _T_1379 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_22.io.enq.bits, _T_1379
node _T_1380 = eq(UInt<5>(0h17), idx_20)
when _T_1380 :
node _T_1381 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_23.io.enq.bits, _T_1381
node _T_1382 = eq(UInt<5>(0h18), idx_20)
when _T_1382 :
node _T_1383 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_24.io.enq.bits, _T_1383
node _T_1384 = eq(UInt<5>(0h19), idx_20)
when _T_1384 :
node _T_1385 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_25.io.enq.bits, _T_1385
node _T_1386 = eq(UInt<5>(0h1a), idx_20)
when _T_1386 :
node _T_1387 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_26.io.enq.bits, _T_1387
node _T_1388 = eq(UInt<5>(0h1b), idx_20)
when _T_1388 :
node _T_1389 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_27.io.enq.bits, _T_1389
node _T_1390 = eq(UInt<5>(0h1c), idx_20)
when _T_1390 :
node _T_1391 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_28.io.enq.bits, _T_1391
node _T_1392 = eq(UInt<5>(0h1d), idx_20)
when _T_1392 :
node _T_1393 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_29.io.enq.bits, _T_1393
node _T_1394 = eq(UInt<5>(0h1e), idx_20)
when _T_1394 :
node _T_1395 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_30.io.enq.bits, _T_1395
node _T_1396 = eq(UInt<5>(0h1f), idx_20)
when _T_1396 :
node _T_1397 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_31.io.enq.bits, _T_1397
node _idx_T_21 = add(write_start_index, UInt<5>(0h15))
node idx_21 = rem(_idx_T_21, UInt<6>(0h20))
node _T_1398 = eq(UInt<1>(0h0), idx_21)
when _T_1398 :
node _T_1399 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8.io.enq.bits, _T_1399
node _T_1400 = eq(UInt<1>(0h1), idx_21)
when _T_1400 :
node _T_1401 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_1.io.enq.bits, _T_1401
node _T_1402 = eq(UInt<2>(0h2), idx_21)
when _T_1402 :
node _T_1403 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_2.io.enq.bits, _T_1403
node _T_1404 = eq(UInt<2>(0h3), idx_21)
when _T_1404 :
node _T_1405 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_3.io.enq.bits, _T_1405
node _T_1406 = eq(UInt<3>(0h4), idx_21)
when _T_1406 :
node _T_1407 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_4.io.enq.bits, _T_1407
node _T_1408 = eq(UInt<3>(0h5), idx_21)
when _T_1408 :
node _T_1409 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_5.io.enq.bits, _T_1409
node _T_1410 = eq(UInt<3>(0h6), idx_21)
when _T_1410 :
node _T_1411 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_6.io.enq.bits, _T_1411
node _T_1412 = eq(UInt<3>(0h7), idx_21)
when _T_1412 :
node _T_1413 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_7.io.enq.bits, _T_1413
node _T_1414 = eq(UInt<4>(0h8), idx_21)
when _T_1414 :
node _T_1415 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_8.io.enq.bits, _T_1415
node _T_1416 = eq(UInt<4>(0h9), idx_21)
when _T_1416 :
node _T_1417 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_9.io.enq.bits, _T_1417
node _T_1418 = eq(UInt<4>(0ha), idx_21)
when _T_1418 :
node _T_1419 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_10.io.enq.bits, _T_1419
node _T_1420 = eq(UInt<4>(0hb), idx_21)
when _T_1420 :
node _T_1421 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_11.io.enq.bits, _T_1421
node _T_1422 = eq(UInt<4>(0hc), idx_21)
when _T_1422 :
node _T_1423 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_12.io.enq.bits, _T_1423
node _T_1424 = eq(UInt<4>(0hd), idx_21)
when _T_1424 :
node _T_1425 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_13.io.enq.bits, _T_1425
node _T_1426 = eq(UInt<4>(0he), idx_21)
when _T_1426 :
node _T_1427 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_14.io.enq.bits, _T_1427
node _T_1428 = eq(UInt<4>(0hf), idx_21)
when _T_1428 :
node _T_1429 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_15.io.enq.bits, _T_1429
node _T_1430 = eq(UInt<5>(0h10), idx_21)
when _T_1430 :
node _T_1431 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_16.io.enq.bits, _T_1431
node _T_1432 = eq(UInt<5>(0h11), idx_21)
when _T_1432 :
node _T_1433 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_17.io.enq.bits, _T_1433
node _T_1434 = eq(UInt<5>(0h12), idx_21)
when _T_1434 :
node _T_1435 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_18.io.enq.bits, _T_1435
node _T_1436 = eq(UInt<5>(0h13), idx_21)
when _T_1436 :
node _T_1437 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_19.io.enq.bits, _T_1437
node _T_1438 = eq(UInt<5>(0h14), idx_21)
when _T_1438 :
node _T_1439 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_20.io.enq.bits, _T_1439
node _T_1440 = eq(UInt<5>(0h15), idx_21)
when _T_1440 :
node _T_1441 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_21.io.enq.bits, _T_1441
node _T_1442 = eq(UInt<5>(0h16), idx_21)
when _T_1442 :
node _T_1443 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_22.io.enq.bits, _T_1443
node _T_1444 = eq(UInt<5>(0h17), idx_21)
when _T_1444 :
node _T_1445 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_23.io.enq.bits, _T_1445
node _T_1446 = eq(UInt<5>(0h18), idx_21)
when _T_1446 :
node _T_1447 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_24.io.enq.bits, _T_1447
node _T_1448 = eq(UInt<5>(0h19), idx_21)
when _T_1448 :
node _T_1449 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_25.io.enq.bits, _T_1449
node _T_1450 = eq(UInt<5>(0h1a), idx_21)
when _T_1450 :
node _T_1451 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_26.io.enq.bits, _T_1451
node _T_1452 = eq(UInt<5>(0h1b), idx_21)
when _T_1452 :
node _T_1453 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_27.io.enq.bits, _T_1453
node _T_1454 = eq(UInt<5>(0h1c), idx_21)
when _T_1454 :
node _T_1455 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_28.io.enq.bits, _T_1455
node _T_1456 = eq(UInt<5>(0h1d), idx_21)
when _T_1456 :
node _T_1457 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_29.io.enq.bits, _T_1457
node _T_1458 = eq(UInt<5>(0h1e), idx_21)
when _T_1458 :
node _T_1459 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_30.io.enq.bits, _T_1459
node _T_1460 = eq(UInt<5>(0h1f), idx_21)
when _T_1460 :
node _T_1461 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_31.io.enq.bits, _T_1461
node _idx_T_22 = add(write_start_index, UInt<5>(0h16))
node idx_22 = rem(_idx_T_22, UInt<6>(0h20))
node _T_1462 = eq(UInt<1>(0h0), idx_22)
when _T_1462 :
node _T_1463 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8.io.enq.bits, _T_1463
node _T_1464 = eq(UInt<1>(0h1), idx_22)
when _T_1464 :
node _T_1465 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_1.io.enq.bits, _T_1465
node _T_1466 = eq(UInt<2>(0h2), idx_22)
when _T_1466 :
node _T_1467 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_2.io.enq.bits, _T_1467
node _T_1468 = eq(UInt<2>(0h3), idx_22)
when _T_1468 :
node _T_1469 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_3.io.enq.bits, _T_1469
node _T_1470 = eq(UInt<3>(0h4), idx_22)
when _T_1470 :
node _T_1471 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_4.io.enq.bits, _T_1471
node _T_1472 = eq(UInt<3>(0h5), idx_22)
when _T_1472 :
node _T_1473 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_5.io.enq.bits, _T_1473
node _T_1474 = eq(UInt<3>(0h6), idx_22)
when _T_1474 :
node _T_1475 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_6.io.enq.bits, _T_1475
node _T_1476 = eq(UInt<3>(0h7), idx_22)
when _T_1476 :
node _T_1477 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_7.io.enq.bits, _T_1477
node _T_1478 = eq(UInt<4>(0h8), idx_22)
when _T_1478 :
node _T_1479 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_8.io.enq.bits, _T_1479
node _T_1480 = eq(UInt<4>(0h9), idx_22)
when _T_1480 :
node _T_1481 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_9.io.enq.bits, _T_1481
node _T_1482 = eq(UInt<4>(0ha), idx_22)
when _T_1482 :
node _T_1483 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_10.io.enq.bits, _T_1483
node _T_1484 = eq(UInt<4>(0hb), idx_22)
when _T_1484 :
node _T_1485 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_11.io.enq.bits, _T_1485
node _T_1486 = eq(UInt<4>(0hc), idx_22)
when _T_1486 :
node _T_1487 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_12.io.enq.bits, _T_1487
node _T_1488 = eq(UInt<4>(0hd), idx_22)
when _T_1488 :
node _T_1489 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_13.io.enq.bits, _T_1489
node _T_1490 = eq(UInt<4>(0he), idx_22)
when _T_1490 :
node _T_1491 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_14.io.enq.bits, _T_1491
node _T_1492 = eq(UInt<4>(0hf), idx_22)
when _T_1492 :
node _T_1493 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_15.io.enq.bits, _T_1493
node _T_1494 = eq(UInt<5>(0h10), idx_22)
when _T_1494 :
node _T_1495 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_16.io.enq.bits, _T_1495
node _T_1496 = eq(UInt<5>(0h11), idx_22)
when _T_1496 :
node _T_1497 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_17.io.enq.bits, _T_1497
node _T_1498 = eq(UInt<5>(0h12), idx_22)
when _T_1498 :
node _T_1499 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_18.io.enq.bits, _T_1499
node _T_1500 = eq(UInt<5>(0h13), idx_22)
when _T_1500 :
node _T_1501 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_19.io.enq.bits, _T_1501
node _T_1502 = eq(UInt<5>(0h14), idx_22)
when _T_1502 :
node _T_1503 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_20.io.enq.bits, _T_1503
node _T_1504 = eq(UInt<5>(0h15), idx_22)
when _T_1504 :
node _T_1505 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_21.io.enq.bits, _T_1505
node _T_1506 = eq(UInt<5>(0h16), idx_22)
when _T_1506 :
node _T_1507 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_22.io.enq.bits, _T_1507
node _T_1508 = eq(UInt<5>(0h17), idx_22)
when _T_1508 :
node _T_1509 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_23.io.enq.bits, _T_1509
node _T_1510 = eq(UInt<5>(0h18), idx_22)
when _T_1510 :
node _T_1511 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_24.io.enq.bits, _T_1511
node _T_1512 = eq(UInt<5>(0h19), idx_22)
when _T_1512 :
node _T_1513 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_25.io.enq.bits, _T_1513
node _T_1514 = eq(UInt<5>(0h1a), idx_22)
when _T_1514 :
node _T_1515 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_26.io.enq.bits, _T_1515
node _T_1516 = eq(UInt<5>(0h1b), idx_22)
when _T_1516 :
node _T_1517 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_27.io.enq.bits, _T_1517
node _T_1518 = eq(UInt<5>(0h1c), idx_22)
when _T_1518 :
node _T_1519 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_28.io.enq.bits, _T_1519
node _T_1520 = eq(UInt<5>(0h1d), idx_22)
when _T_1520 :
node _T_1521 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_29.io.enq.bits, _T_1521
node _T_1522 = eq(UInt<5>(0h1e), idx_22)
when _T_1522 :
node _T_1523 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_30.io.enq.bits, _T_1523
node _T_1524 = eq(UInt<5>(0h1f), idx_22)
when _T_1524 :
node _T_1525 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_31.io.enq.bits, _T_1525
node _idx_T_23 = add(write_start_index, UInt<5>(0h17))
node idx_23 = rem(_idx_T_23, UInt<6>(0h20))
node _T_1526 = eq(UInt<1>(0h0), idx_23)
when _T_1526 :
node _T_1527 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8.io.enq.bits, _T_1527
node _T_1528 = eq(UInt<1>(0h1), idx_23)
when _T_1528 :
node _T_1529 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_1.io.enq.bits, _T_1529
node _T_1530 = eq(UInt<2>(0h2), idx_23)
when _T_1530 :
node _T_1531 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_2.io.enq.bits, _T_1531
node _T_1532 = eq(UInt<2>(0h3), idx_23)
when _T_1532 :
node _T_1533 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_3.io.enq.bits, _T_1533
node _T_1534 = eq(UInt<3>(0h4), idx_23)
when _T_1534 :
node _T_1535 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_4.io.enq.bits, _T_1535
node _T_1536 = eq(UInt<3>(0h5), idx_23)
when _T_1536 :
node _T_1537 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_5.io.enq.bits, _T_1537
node _T_1538 = eq(UInt<3>(0h6), idx_23)
when _T_1538 :
node _T_1539 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_6.io.enq.bits, _T_1539
node _T_1540 = eq(UInt<3>(0h7), idx_23)
when _T_1540 :
node _T_1541 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_7.io.enq.bits, _T_1541
node _T_1542 = eq(UInt<4>(0h8), idx_23)
when _T_1542 :
node _T_1543 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_8.io.enq.bits, _T_1543
node _T_1544 = eq(UInt<4>(0h9), idx_23)
when _T_1544 :
node _T_1545 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_9.io.enq.bits, _T_1545
node _T_1546 = eq(UInt<4>(0ha), idx_23)
when _T_1546 :
node _T_1547 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_10.io.enq.bits, _T_1547
node _T_1548 = eq(UInt<4>(0hb), idx_23)
when _T_1548 :
node _T_1549 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_11.io.enq.bits, _T_1549
node _T_1550 = eq(UInt<4>(0hc), idx_23)
when _T_1550 :
node _T_1551 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_12.io.enq.bits, _T_1551
node _T_1552 = eq(UInt<4>(0hd), idx_23)
when _T_1552 :
node _T_1553 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_13.io.enq.bits, _T_1553
node _T_1554 = eq(UInt<4>(0he), idx_23)
when _T_1554 :
node _T_1555 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_14.io.enq.bits, _T_1555
node _T_1556 = eq(UInt<4>(0hf), idx_23)
when _T_1556 :
node _T_1557 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_15.io.enq.bits, _T_1557
node _T_1558 = eq(UInt<5>(0h10), idx_23)
when _T_1558 :
node _T_1559 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_16.io.enq.bits, _T_1559
node _T_1560 = eq(UInt<5>(0h11), idx_23)
when _T_1560 :
node _T_1561 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_17.io.enq.bits, _T_1561
node _T_1562 = eq(UInt<5>(0h12), idx_23)
when _T_1562 :
node _T_1563 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_18.io.enq.bits, _T_1563
node _T_1564 = eq(UInt<5>(0h13), idx_23)
when _T_1564 :
node _T_1565 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_19.io.enq.bits, _T_1565
node _T_1566 = eq(UInt<5>(0h14), idx_23)
when _T_1566 :
node _T_1567 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_20.io.enq.bits, _T_1567
node _T_1568 = eq(UInt<5>(0h15), idx_23)
when _T_1568 :
node _T_1569 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_21.io.enq.bits, _T_1569
node _T_1570 = eq(UInt<5>(0h16), idx_23)
when _T_1570 :
node _T_1571 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_22.io.enq.bits, _T_1571
node _T_1572 = eq(UInt<5>(0h17), idx_23)
when _T_1572 :
node _T_1573 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_23.io.enq.bits, _T_1573
node _T_1574 = eq(UInt<5>(0h18), idx_23)
when _T_1574 :
node _T_1575 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_24.io.enq.bits, _T_1575
node _T_1576 = eq(UInt<5>(0h19), idx_23)
when _T_1576 :
node _T_1577 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_25.io.enq.bits, _T_1577
node _T_1578 = eq(UInt<5>(0h1a), idx_23)
when _T_1578 :
node _T_1579 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_26.io.enq.bits, _T_1579
node _T_1580 = eq(UInt<5>(0h1b), idx_23)
when _T_1580 :
node _T_1581 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_27.io.enq.bits, _T_1581
node _T_1582 = eq(UInt<5>(0h1c), idx_23)
when _T_1582 :
node _T_1583 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_28.io.enq.bits, _T_1583
node _T_1584 = eq(UInt<5>(0h1d), idx_23)
when _T_1584 :
node _T_1585 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_29.io.enq.bits, _T_1585
node _T_1586 = eq(UInt<5>(0h1e), idx_23)
when _T_1586 :
node _T_1587 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_30.io.enq.bits, _T_1587
node _T_1588 = eq(UInt<5>(0h1f), idx_23)
when _T_1588 :
node _T_1589 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_31.io.enq.bits, _T_1589
node _idx_T_24 = add(write_start_index, UInt<5>(0h18))
node idx_24 = rem(_idx_T_24, UInt<6>(0h20))
node _T_1590 = eq(UInt<1>(0h0), idx_24)
when _T_1590 :
node _T_1591 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8.io.enq.bits, _T_1591
node _T_1592 = eq(UInt<1>(0h1), idx_24)
when _T_1592 :
node _T_1593 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_1.io.enq.bits, _T_1593
node _T_1594 = eq(UInt<2>(0h2), idx_24)
when _T_1594 :
node _T_1595 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_2.io.enq.bits, _T_1595
node _T_1596 = eq(UInt<2>(0h3), idx_24)
when _T_1596 :
node _T_1597 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_3.io.enq.bits, _T_1597
node _T_1598 = eq(UInt<3>(0h4), idx_24)
when _T_1598 :
node _T_1599 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_4.io.enq.bits, _T_1599
node _T_1600 = eq(UInt<3>(0h5), idx_24)
when _T_1600 :
node _T_1601 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_5.io.enq.bits, _T_1601
node _T_1602 = eq(UInt<3>(0h6), idx_24)
when _T_1602 :
node _T_1603 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_6.io.enq.bits, _T_1603
node _T_1604 = eq(UInt<3>(0h7), idx_24)
when _T_1604 :
node _T_1605 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_7.io.enq.bits, _T_1605
node _T_1606 = eq(UInt<4>(0h8), idx_24)
when _T_1606 :
node _T_1607 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_8.io.enq.bits, _T_1607
node _T_1608 = eq(UInt<4>(0h9), idx_24)
when _T_1608 :
node _T_1609 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_9.io.enq.bits, _T_1609
node _T_1610 = eq(UInt<4>(0ha), idx_24)
when _T_1610 :
node _T_1611 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_10.io.enq.bits, _T_1611
node _T_1612 = eq(UInt<4>(0hb), idx_24)
when _T_1612 :
node _T_1613 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_11.io.enq.bits, _T_1613
node _T_1614 = eq(UInt<4>(0hc), idx_24)
when _T_1614 :
node _T_1615 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_12.io.enq.bits, _T_1615
node _T_1616 = eq(UInt<4>(0hd), idx_24)
when _T_1616 :
node _T_1617 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_13.io.enq.bits, _T_1617
node _T_1618 = eq(UInt<4>(0he), idx_24)
when _T_1618 :
node _T_1619 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_14.io.enq.bits, _T_1619
node _T_1620 = eq(UInt<4>(0hf), idx_24)
when _T_1620 :
node _T_1621 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_15.io.enq.bits, _T_1621
node _T_1622 = eq(UInt<5>(0h10), idx_24)
when _T_1622 :
node _T_1623 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_16.io.enq.bits, _T_1623
node _T_1624 = eq(UInt<5>(0h11), idx_24)
when _T_1624 :
node _T_1625 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_17.io.enq.bits, _T_1625
node _T_1626 = eq(UInt<5>(0h12), idx_24)
when _T_1626 :
node _T_1627 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_18.io.enq.bits, _T_1627
node _T_1628 = eq(UInt<5>(0h13), idx_24)
when _T_1628 :
node _T_1629 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_19.io.enq.bits, _T_1629
node _T_1630 = eq(UInt<5>(0h14), idx_24)
when _T_1630 :
node _T_1631 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_20.io.enq.bits, _T_1631
node _T_1632 = eq(UInt<5>(0h15), idx_24)
when _T_1632 :
node _T_1633 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_21.io.enq.bits, _T_1633
node _T_1634 = eq(UInt<5>(0h16), idx_24)
when _T_1634 :
node _T_1635 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_22.io.enq.bits, _T_1635
node _T_1636 = eq(UInt<5>(0h17), idx_24)
when _T_1636 :
node _T_1637 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_23.io.enq.bits, _T_1637
node _T_1638 = eq(UInt<5>(0h18), idx_24)
when _T_1638 :
node _T_1639 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_24.io.enq.bits, _T_1639
node _T_1640 = eq(UInt<5>(0h19), idx_24)
when _T_1640 :
node _T_1641 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_25.io.enq.bits, _T_1641
node _T_1642 = eq(UInt<5>(0h1a), idx_24)
when _T_1642 :
node _T_1643 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_26.io.enq.bits, _T_1643
node _T_1644 = eq(UInt<5>(0h1b), idx_24)
when _T_1644 :
node _T_1645 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_27.io.enq.bits, _T_1645
node _T_1646 = eq(UInt<5>(0h1c), idx_24)
when _T_1646 :
node _T_1647 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_28.io.enq.bits, _T_1647
node _T_1648 = eq(UInt<5>(0h1d), idx_24)
when _T_1648 :
node _T_1649 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_29.io.enq.bits, _T_1649
node _T_1650 = eq(UInt<5>(0h1e), idx_24)
when _T_1650 :
node _T_1651 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_30.io.enq.bits, _T_1651
node _T_1652 = eq(UInt<5>(0h1f), idx_24)
when _T_1652 :
node _T_1653 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_31.io.enq.bits, _T_1653
node _idx_T_25 = add(write_start_index, UInt<5>(0h19))
node idx_25 = rem(_idx_T_25, UInt<6>(0h20))
node _T_1654 = eq(UInt<1>(0h0), idx_25)
when _T_1654 :
node _T_1655 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8.io.enq.bits, _T_1655
node _T_1656 = eq(UInt<1>(0h1), idx_25)
when _T_1656 :
node _T_1657 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_1.io.enq.bits, _T_1657
node _T_1658 = eq(UInt<2>(0h2), idx_25)
when _T_1658 :
node _T_1659 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_2.io.enq.bits, _T_1659
node _T_1660 = eq(UInt<2>(0h3), idx_25)
when _T_1660 :
node _T_1661 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_3.io.enq.bits, _T_1661
node _T_1662 = eq(UInt<3>(0h4), idx_25)
when _T_1662 :
node _T_1663 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_4.io.enq.bits, _T_1663
node _T_1664 = eq(UInt<3>(0h5), idx_25)
when _T_1664 :
node _T_1665 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_5.io.enq.bits, _T_1665
node _T_1666 = eq(UInt<3>(0h6), idx_25)
when _T_1666 :
node _T_1667 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_6.io.enq.bits, _T_1667
node _T_1668 = eq(UInt<3>(0h7), idx_25)
when _T_1668 :
node _T_1669 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_7.io.enq.bits, _T_1669
node _T_1670 = eq(UInt<4>(0h8), idx_25)
when _T_1670 :
node _T_1671 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_8.io.enq.bits, _T_1671
node _T_1672 = eq(UInt<4>(0h9), idx_25)
when _T_1672 :
node _T_1673 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_9.io.enq.bits, _T_1673
node _T_1674 = eq(UInt<4>(0ha), idx_25)
when _T_1674 :
node _T_1675 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_10.io.enq.bits, _T_1675
node _T_1676 = eq(UInt<4>(0hb), idx_25)
when _T_1676 :
node _T_1677 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_11.io.enq.bits, _T_1677
node _T_1678 = eq(UInt<4>(0hc), idx_25)
when _T_1678 :
node _T_1679 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_12.io.enq.bits, _T_1679
node _T_1680 = eq(UInt<4>(0hd), idx_25)
when _T_1680 :
node _T_1681 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_13.io.enq.bits, _T_1681
node _T_1682 = eq(UInt<4>(0he), idx_25)
when _T_1682 :
node _T_1683 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_14.io.enq.bits, _T_1683
node _T_1684 = eq(UInt<4>(0hf), idx_25)
when _T_1684 :
node _T_1685 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_15.io.enq.bits, _T_1685
node _T_1686 = eq(UInt<5>(0h10), idx_25)
when _T_1686 :
node _T_1687 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_16.io.enq.bits, _T_1687
node _T_1688 = eq(UInt<5>(0h11), idx_25)
when _T_1688 :
node _T_1689 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_17.io.enq.bits, _T_1689
node _T_1690 = eq(UInt<5>(0h12), idx_25)
when _T_1690 :
node _T_1691 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_18.io.enq.bits, _T_1691
node _T_1692 = eq(UInt<5>(0h13), idx_25)
when _T_1692 :
node _T_1693 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_19.io.enq.bits, _T_1693
node _T_1694 = eq(UInt<5>(0h14), idx_25)
when _T_1694 :
node _T_1695 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_20.io.enq.bits, _T_1695
node _T_1696 = eq(UInt<5>(0h15), idx_25)
when _T_1696 :
node _T_1697 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_21.io.enq.bits, _T_1697
node _T_1698 = eq(UInt<5>(0h16), idx_25)
when _T_1698 :
node _T_1699 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_22.io.enq.bits, _T_1699
node _T_1700 = eq(UInt<5>(0h17), idx_25)
when _T_1700 :
node _T_1701 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_23.io.enq.bits, _T_1701
node _T_1702 = eq(UInt<5>(0h18), idx_25)
when _T_1702 :
node _T_1703 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_24.io.enq.bits, _T_1703
node _T_1704 = eq(UInt<5>(0h19), idx_25)
when _T_1704 :
node _T_1705 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_25.io.enq.bits, _T_1705
node _T_1706 = eq(UInt<5>(0h1a), idx_25)
when _T_1706 :
node _T_1707 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_26.io.enq.bits, _T_1707
node _T_1708 = eq(UInt<5>(0h1b), idx_25)
when _T_1708 :
node _T_1709 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_27.io.enq.bits, _T_1709
node _T_1710 = eq(UInt<5>(0h1c), idx_25)
when _T_1710 :
node _T_1711 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_28.io.enq.bits, _T_1711
node _T_1712 = eq(UInt<5>(0h1d), idx_25)
when _T_1712 :
node _T_1713 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_29.io.enq.bits, _T_1713
node _T_1714 = eq(UInt<5>(0h1e), idx_25)
when _T_1714 :
node _T_1715 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_30.io.enq.bits, _T_1715
node _T_1716 = eq(UInt<5>(0h1f), idx_25)
when _T_1716 :
node _T_1717 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_31.io.enq.bits, _T_1717
node _idx_T_26 = add(write_start_index, UInt<5>(0h1a))
node idx_26 = rem(_idx_T_26, UInt<6>(0h20))
node _T_1718 = eq(UInt<1>(0h0), idx_26)
when _T_1718 :
node _T_1719 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8.io.enq.bits, _T_1719
node _T_1720 = eq(UInt<1>(0h1), idx_26)
when _T_1720 :
node _T_1721 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_1.io.enq.bits, _T_1721
node _T_1722 = eq(UInt<2>(0h2), idx_26)
when _T_1722 :
node _T_1723 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_2.io.enq.bits, _T_1723
node _T_1724 = eq(UInt<2>(0h3), idx_26)
when _T_1724 :
node _T_1725 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_3.io.enq.bits, _T_1725
node _T_1726 = eq(UInt<3>(0h4), idx_26)
when _T_1726 :
node _T_1727 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_4.io.enq.bits, _T_1727
node _T_1728 = eq(UInt<3>(0h5), idx_26)
when _T_1728 :
node _T_1729 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_5.io.enq.bits, _T_1729
node _T_1730 = eq(UInt<3>(0h6), idx_26)
when _T_1730 :
node _T_1731 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_6.io.enq.bits, _T_1731
node _T_1732 = eq(UInt<3>(0h7), idx_26)
when _T_1732 :
node _T_1733 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_7.io.enq.bits, _T_1733
node _T_1734 = eq(UInt<4>(0h8), idx_26)
when _T_1734 :
node _T_1735 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_8.io.enq.bits, _T_1735
node _T_1736 = eq(UInt<4>(0h9), idx_26)
when _T_1736 :
node _T_1737 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_9.io.enq.bits, _T_1737
node _T_1738 = eq(UInt<4>(0ha), idx_26)
when _T_1738 :
node _T_1739 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_10.io.enq.bits, _T_1739
node _T_1740 = eq(UInt<4>(0hb), idx_26)
when _T_1740 :
node _T_1741 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_11.io.enq.bits, _T_1741
node _T_1742 = eq(UInt<4>(0hc), idx_26)
when _T_1742 :
node _T_1743 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_12.io.enq.bits, _T_1743
node _T_1744 = eq(UInt<4>(0hd), idx_26)
when _T_1744 :
node _T_1745 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_13.io.enq.bits, _T_1745
node _T_1746 = eq(UInt<4>(0he), idx_26)
when _T_1746 :
node _T_1747 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_14.io.enq.bits, _T_1747
node _T_1748 = eq(UInt<4>(0hf), idx_26)
when _T_1748 :
node _T_1749 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_15.io.enq.bits, _T_1749
node _T_1750 = eq(UInt<5>(0h10), idx_26)
when _T_1750 :
node _T_1751 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_16.io.enq.bits, _T_1751
node _T_1752 = eq(UInt<5>(0h11), idx_26)
when _T_1752 :
node _T_1753 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_17.io.enq.bits, _T_1753
node _T_1754 = eq(UInt<5>(0h12), idx_26)
when _T_1754 :
node _T_1755 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_18.io.enq.bits, _T_1755
node _T_1756 = eq(UInt<5>(0h13), idx_26)
when _T_1756 :
node _T_1757 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_19.io.enq.bits, _T_1757
node _T_1758 = eq(UInt<5>(0h14), idx_26)
when _T_1758 :
node _T_1759 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_20.io.enq.bits, _T_1759
node _T_1760 = eq(UInt<5>(0h15), idx_26)
when _T_1760 :
node _T_1761 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_21.io.enq.bits, _T_1761
node _T_1762 = eq(UInt<5>(0h16), idx_26)
when _T_1762 :
node _T_1763 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_22.io.enq.bits, _T_1763
node _T_1764 = eq(UInt<5>(0h17), idx_26)
when _T_1764 :
node _T_1765 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_23.io.enq.bits, _T_1765
node _T_1766 = eq(UInt<5>(0h18), idx_26)
when _T_1766 :
node _T_1767 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_24.io.enq.bits, _T_1767
node _T_1768 = eq(UInt<5>(0h19), idx_26)
when _T_1768 :
node _T_1769 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_25.io.enq.bits, _T_1769
node _T_1770 = eq(UInt<5>(0h1a), idx_26)
when _T_1770 :
node _T_1771 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_26.io.enq.bits, _T_1771
node _T_1772 = eq(UInt<5>(0h1b), idx_26)
when _T_1772 :
node _T_1773 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_27.io.enq.bits, _T_1773
node _T_1774 = eq(UInt<5>(0h1c), idx_26)
when _T_1774 :
node _T_1775 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_28.io.enq.bits, _T_1775
node _T_1776 = eq(UInt<5>(0h1d), idx_26)
when _T_1776 :
node _T_1777 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_29.io.enq.bits, _T_1777
node _T_1778 = eq(UInt<5>(0h1e), idx_26)
when _T_1778 :
node _T_1779 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_30.io.enq.bits, _T_1779
node _T_1780 = eq(UInt<5>(0h1f), idx_26)
when _T_1780 :
node _T_1781 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_31.io.enq.bits, _T_1781
node _idx_T_27 = add(write_start_index, UInt<5>(0h1b))
node idx_27 = rem(_idx_T_27, UInt<6>(0h20))
node _T_1782 = eq(UInt<1>(0h0), idx_27)
when _T_1782 :
node _T_1783 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8.io.enq.bits, _T_1783
node _T_1784 = eq(UInt<1>(0h1), idx_27)
when _T_1784 :
node _T_1785 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_1.io.enq.bits, _T_1785
node _T_1786 = eq(UInt<2>(0h2), idx_27)
when _T_1786 :
node _T_1787 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_2.io.enq.bits, _T_1787
node _T_1788 = eq(UInt<2>(0h3), idx_27)
when _T_1788 :
node _T_1789 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_3.io.enq.bits, _T_1789
node _T_1790 = eq(UInt<3>(0h4), idx_27)
when _T_1790 :
node _T_1791 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_4.io.enq.bits, _T_1791
node _T_1792 = eq(UInt<3>(0h5), idx_27)
when _T_1792 :
node _T_1793 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_5.io.enq.bits, _T_1793
node _T_1794 = eq(UInt<3>(0h6), idx_27)
when _T_1794 :
node _T_1795 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_6.io.enq.bits, _T_1795
node _T_1796 = eq(UInt<3>(0h7), idx_27)
when _T_1796 :
node _T_1797 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_7.io.enq.bits, _T_1797
node _T_1798 = eq(UInt<4>(0h8), idx_27)
when _T_1798 :
node _T_1799 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_8.io.enq.bits, _T_1799
node _T_1800 = eq(UInt<4>(0h9), idx_27)
when _T_1800 :
node _T_1801 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_9.io.enq.bits, _T_1801
node _T_1802 = eq(UInt<4>(0ha), idx_27)
when _T_1802 :
node _T_1803 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_10.io.enq.bits, _T_1803
node _T_1804 = eq(UInt<4>(0hb), idx_27)
when _T_1804 :
node _T_1805 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_11.io.enq.bits, _T_1805
node _T_1806 = eq(UInt<4>(0hc), idx_27)
when _T_1806 :
node _T_1807 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_12.io.enq.bits, _T_1807
node _T_1808 = eq(UInt<4>(0hd), idx_27)
when _T_1808 :
node _T_1809 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_13.io.enq.bits, _T_1809
node _T_1810 = eq(UInt<4>(0he), idx_27)
when _T_1810 :
node _T_1811 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_14.io.enq.bits, _T_1811
node _T_1812 = eq(UInt<4>(0hf), idx_27)
when _T_1812 :
node _T_1813 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_15.io.enq.bits, _T_1813
node _T_1814 = eq(UInt<5>(0h10), idx_27)
when _T_1814 :
node _T_1815 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_16.io.enq.bits, _T_1815
node _T_1816 = eq(UInt<5>(0h11), idx_27)
when _T_1816 :
node _T_1817 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_17.io.enq.bits, _T_1817
node _T_1818 = eq(UInt<5>(0h12), idx_27)
when _T_1818 :
node _T_1819 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_18.io.enq.bits, _T_1819
node _T_1820 = eq(UInt<5>(0h13), idx_27)
when _T_1820 :
node _T_1821 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_19.io.enq.bits, _T_1821
node _T_1822 = eq(UInt<5>(0h14), idx_27)
when _T_1822 :
node _T_1823 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_20.io.enq.bits, _T_1823
node _T_1824 = eq(UInt<5>(0h15), idx_27)
when _T_1824 :
node _T_1825 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_21.io.enq.bits, _T_1825
node _T_1826 = eq(UInt<5>(0h16), idx_27)
when _T_1826 :
node _T_1827 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_22.io.enq.bits, _T_1827
node _T_1828 = eq(UInt<5>(0h17), idx_27)
when _T_1828 :
node _T_1829 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_23.io.enq.bits, _T_1829
node _T_1830 = eq(UInt<5>(0h18), idx_27)
when _T_1830 :
node _T_1831 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_24.io.enq.bits, _T_1831
node _T_1832 = eq(UInt<5>(0h19), idx_27)
when _T_1832 :
node _T_1833 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_25.io.enq.bits, _T_1833
node _T_1834 = eq(UInt<5>(0h1a), idx_27)
when _T_1834 :
node _T_1835 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_26.io.enq.bits, _T_1835
node _T_1836 = eq(UInt<5>(0h1b), idx_27)
when _T_1836 :
node _T_1837 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_27.io.enq.bits, _T_1837
node _T_1838 = eq(UInt<5>(0h1c), idx_27)
when _T_1838 :
node _T_1839 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_28.io.enq.bits, _T_1839
node _T_1840 = eq(UInt<5>(0h1d), idx_27)
when _T_1840 :
node _T_1841 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_29.io.enq.bits, _T_1841
node _T_1842 = eq(UInt<5>(0h1e), idx_27)
when _T_1842 :
node _T_1843 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_30.io.enq.bits, _T_1843
node _T_1844 = eq(UInt<5>(0h1f), idx_27)
when _T_1844 :
node _T_1845 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_31.io.enq.bits, _T_1845
node _idx_T_28 = add(write_start_index, UInt<5>(0h1c))
node idx_28 = rem(_idx_T_28, UInt<6>(0h20))
node _T_1846 = eq(UInt<1>(0h0), idx_28)
when _T_1846 :
node _T_1847 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8.io.enq.bits, _T_1847
node _T_1848 = eq(UInt<1>(0h1), idx_28)
when _T_1848 :
node _T_1849 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_1.io.enq.bits, _T_1849
node _T_1850 = eq(UInt<2>(0h2), idx_28)
when _T_1850 :
node _T_1851 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_2.io.enq.bits, _T_1851
node _T_1852 = eq(UInt<2>(0h3), idx_28)
when _T_1852 :
node _T_1853 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_3.io.enq.bits, _T_1853
node _T_1854 = eq(UInt<3>(0h4), idx_28)
when _T_1854 :
node _T_1855 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_4.io.enq.bits, _T_1855
node _T_1856 = eq(UInt<3>(0h5), idx_28)
when _T_1856 :
node _T_1857 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_5.io.enq.bits, _T_1857
node _T_1858 = eq(UInt<3>(0h6), idx_28)
when _T_1858 :
node _T_1859 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_6.io.enq.bits, _T_1859
node _T_1860 = eq(UInt<3>(0h7), idx_28)
when _T_1860 :
node _T_1861 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_7.io.enq.bits, _T_1861
node _T_1862 = eq(UInt<4>(0h8), idx_28)
when _T_1862 :
node _T_1863 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_8.io.enq.bits, _T_1863
node _T_1864 = eq(UInt<4>(0h9), idx_28)
when _T_1864 :
node _T_1865 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_9.io.enq.bits, _T_1865
node _T_1866 = eq(UInt<4>(0ha), idx_28)
when _T_1866 :
node _T_1867 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_10.io.enq.bits, _T_1867
node _T_1868 = eq(UInt<4>(0hb), idx_28)
when _T_1868 :
node _T_1869 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_11.io.enq.bits, _T_1869
node _T_1870 = eq(UInt<4>(0hc), idx_28)
when _T_1870 :
node _T_1871 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_12.io.enq.bits, _T_1871
node _T_1872 = eq(UInt<4>(0hd), idx_28)
when _T_1872 :
node _T_1873 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_13.io.enq.bits, _T_1873
node _T_1874 = eq(UInt<4>(0he), idx_28)
when _T_1874 :
node _T_1875 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_14.io.enq.bits, _T_1875
node _T_1876 = eq(UInt<4>(0hf), idx_28)
when _T_1876 :
node _T_1877 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_15.io.enq.bits, _T_1877
node _T_1878 = eq(UInt<5>(0h10), idx_28)
when _T_1878 :
node _T_1879 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_16.io.enq.bits, _T_1879
node _T_1880 = eq(UInt<5>(0h11), idx_28)
when _T_1880 :
node _T_1881 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_17.io.enq.bits, _T_1881
node _T_1882 = eq(UInt<5>(0h12), idx_28)
when _T_1882 :
node _T_1883 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_18.io.enq.bits, _T_1883
node _T_1884 = eq(UInt<5>(0h13), idx_28)
when _T_1884 :
node _T_1885 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_19.io.enq.bits, _T_1885
node _T_1886 = eq(UInt<5>(0h14), idx_28)
when _T_1886 :
node _T_1887 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_20.io.enq.bits, _T_1887
node _T_1888 = eq(UInt<5>(0h15), idx_28)
when _T_1888 :
node _T_1889 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_21.io.enq.bits, _T_1889
node _T_1890 = eq(UInt<5>(0h16), idx_28)
when _T_1890 :
node _T_1891 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_22.io.enq.bits, _T_1891
node _T_1892 = eq(UInt<5>(0h17), idx_28)
when _T_1892 :
node _T_1893 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_23.io.enq.bits, _T_1893
node _T_1894 = eq(UInt<5>(0h18), idx_28)
when _T_1894 :
node _T_1895 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_24.io.enq.bits, _T_1895
node _T_1896 = eq(UInt<5>(0h19), idx_28)
when _T_1896 :
node _T_1897 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_25.io.enq.bits, _T_1897
node _T_1898 = eq(UInt<5>(0h1a), idx_28)
when _T_1898 :
node _T_1899 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_26.io.enq.bits, _T_1899
node _T_1900 = eq(UInt<5>(0h1b), idx_28)
when _T_1900 :
node _T_1901 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_27.io.enq.bits, _T_1901
node _T_1902 = eq(UInt<5>(0h1c), idx_28)
when _T_1902 :
node _T_1903 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_28.io.enq.bits, _T_1903
node _T_1904 = eq(UInt<5>(0h1d), idx_28)
when _T_1904 :
node _T_1905 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_29.io.enq.bits, _T_1905
node _T_1906 = eq(UInt<5>(0h1e), idx_28)
when _T_1906 :
node _T_1907 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_30.io.enq.bits, _T_1907
node _T_1908 = eq(UInt<5>(0h1f), idx_28)
when _T_1908 :
node _T_1909 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_31.io.enq.bits, _T_1909
node _idx_T_29 = add(write_start_index, UInt<5>(0h1d))
node idx_29 = rem(_idx_T_29, UInt<6>(0h20))
node _T_1910 = eq(UInt<1>(0h0), idx_29)
when _T_1910 :
node _T_1911 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8.io.enq.bits, _T_1911
node _T_1912 = eq(UInt<1>(0h1), idx_29)
when _T_1912 :
node _T_1913 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_1.io.enq.bits, _T_1913
node _T_1914 = eq(UInt<2>(0h2), idx_29)
when _T_1914 :
node _T_1915 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_2.io.enq.bits, _T_1915
node _T_1916 = eq(UInt<2>(0h3), idx_29)
when _T_1916 :
node _T_1917 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_3.io.enq.bits, _T_1917
node _T_1918 = eq(UInt<3>(0h4), idx_29)
when _T_1918 :
node _T_1919 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_4.io.enq.bits, _T_1919
node _T_1920 = eq(UInt<3>(0h5), idx_29)
when _T_1920 :
node _T_1921 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_5.io.enq.bits, _T_1921
node _T_1922 = eq(UInt<3>(0h6), idx_29)
when _T_1922 :
node _T_1923 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_6.io.enq.bits, _T_1923
node _T_1924 = eq(UInt<3>(0h7), idx_29)
when _T_1924 :
node _T_1925 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_7.io.enq.bits, _T_1925
node _T_1926 = eq(UInt<4>(0h8), idx_29)
when _T_1926 :
node _T_1927 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_8.io.enq.bits, _T_1927
node _T_1928 = eq(UInt<4>(0h9), idx_29)
when _T_1928 :
node _T_1929 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_9.io.enq.bits, _T_1929
node _T_1930 = eq(UInt<4>(0ha), idx_29)
when _T_1930 :
node _T_1931 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_10.io.enq.bits, _T_1931
node _T_1932 = eq(UInt<4>(0hb), idx_29)
when _T_1932 :
node _T_1933 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_11.io.enq.bits, _T_1933
node _T_1934 = eq(UInt<4>(0hc), idx_29)
when _T_1934 :
node _T_1935 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_12.io.enq.bits, _T_1935
node _T_1936 = eq(UInt<4>(0hd), idx_29)
when _T_1936 :
node _T_1937 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_13.io.enq.bits, _T_1937
node _T_1938 = eq(UInt<4>(0he), idx_29)
when _T_1938 :
node _T_1939 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_14.io.enq.bits, _T_1939
node _T_1940 = eq(UInt<4>(0hf), idx_29)
when _T_1940 :
node _T_1941 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_15.io.enq.bits, _T_1941
node _T_1942 = eq(UInt<5>(0h10), idx_29)
when _T_1942 :
node _T_1943 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_16.io.enq.bits, _T_1943
node _T_1944 = eq(UInt<5>(0h11), idx_29)
when _T_1944 :
node _T_1945 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_17.io.enq.bits, _T_1945
node _T_1946 = eq(UInt<5>(0h12), idx_29)
when _T_1946 :
node _T_1947 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_18.io.enq.bits, _T_1947
node _T_1948 = eq(UInt<5>(0h13), idx_29)
when _T_1948 :
node _T_1949 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_19.io.enq.bits, _T_1949
node _T_1950 = eq(UInt<5>(0h14), idx_29)
when _T_1950 :
node _T_1951 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_20.io.enq.bits, _T_1951
node _T_1952 = eq(UInt<5>(0h15), idx_29)
when _T_1952 :
node _T_1953 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_21.io.enq.bits, _T_1953
node _T_1954 = eq(UInt<5>(0h16), idx_29)
when _T_1954 :
node _T_1955 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_22.io.enq.bits, _T_1955
node _T_1956 = eq(UInt<5>(0h17), idx_29)
when _T_1956 :
node _T_1957 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_23.io.enq.bits, _T_1957
node _T_1958 = eq(UInt<5>(0h18), idx_29)
when _T_1958 :
node _T_1959 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_24.io.enq.bits, _T_1959
node _T_1960 = eq(UInt<5>(0h19), idx_29)
when _T_1960 :
node _T_1961 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_25.io.enq.bits, _T_1961
node _T_1962 = eq(UInt<5>(0h1a), idx_29)
when _T_1962 :
node _T_1963 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_26.io.enq.bits, _T_1963
node _T_1964 = eq(UInt<5>(0h1b), idx_29)
when _T_1964 :
node _T_1965 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_27.io.enq.bits, _T_1965
node _T_1966 = eq(UInt<5>(0h1c), idx_29)
when _T_1966 :
node _T_1967 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_28.io.enq.bits, _T_1967
node _T_1968 = eq(UInt<5>(0h1d), idx_29)
when _T_1968 :
node _T_1969 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_29.io.enq.bits, _T_1969
node _T_1970 = eq(UInt<5>(0h1e), idx_29)
when _T_1970 :
node _T_1971 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_30.io.enq.bits, _T_1971
node _T_1972 = eq(UInt<5>(0h1f), idx_29)
when _T_1972 :
node _T_1973 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_31.io.enq.bits, _T_1973
node _idx_T_30 = add(write_start_index, UInt<5>(0h1e))
node idx_30 = rem(_idx_T_30, UInt<6>(0h20))
node _T_1974 = eq(UInt<1>(0h0), idx_30)
when _T_1974 :
node _T_1975 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8.io.enq.bits, _T_1975
node _T_1976 = eq(UInt<1>(0h1), idx_30)
when _T_1976 :
node _T_1977 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_1.io.enq.bits, _T_1977
node _T_1978 = eq(UInt<2>(0h2), idx_30)
when _T_1978 :
node _T_1979 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_2.io.enq.bits, _T_1979
node _T_1980 = eq(UInt<2>(0h3), idx_30)
when _T_1980 :
node _T_1981 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_3.io.enq.bits, _T_1981
node _T_1982 = eq(UInt<3>(0h4), idx_30)
when _T_1982 :
node _T_1983 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_4.io.enq.bits, _T_1983
node _T_1984 = eq(UInt<3>(0h5), idx_30)
when _T_1984 :
node _T_1985 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_5.io.enq.bits, _T_1985
node _T_1986 = eq(UInt<3>(0h6), idx_30)
when _T_1986 :
node _T_1987 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_6.io.enq.bits, _T_1987
node _T_1988 = eq(UInt<3>(0h7), idx_30)
when _T_1988 :
node _T_1989 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_7.io.enq.bits, _T_1989
node _T_1990 = eq(UInt<4>(0h8), idx_30)
when _T_1990 :
node _T_1991 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_8.io.enq.bits, _T_1991
node _T_1992 = eq(UInt<4>(0h9), idx_30)
when _T_1992 :
node _T_1993 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_9.io.enq.bits, _T_1993
node _T_1994 = eq(UInt<4>(0ha), idx_30)
when _T_1994 :
node _T_1995 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_10.io.enq.bits, _T_1995
node _T_1996 = eq(UInt<4>(0hb), idx_30)
when _T_1996 :
node _T_1997 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_11.io.enq.bits, _T_1997
node _T_1998 = eq(UInt<4>(0hc), idx_30)
when _T_1998 :
node _T_1999 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_12.io.enq.bits, _T_1999
node _T_2000 = eq(UInt<4>(0hd), idx_30)
when _T_2000 :
node _T_2001 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_13.io.enq.bits, _T_2001
node _T_2002 = eq(UInt<4>(0he), idx_30)
when _T_2002 :
node _T_2003 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_14.io.enq.bits, _T_2003
node _T_2004 = eq(UInt<4>(0hf), idx_30)
when _T_2004 :
node _T_2005 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_15.io.enq.bits, _T_2005
node _T_2006 = eq(UInt<5>(0h10), idx_30)
when _T_2006 :
node _T_2007 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_16.io.enq.bits, _T_2007
node _T_2008 = eq(UInt<5>(0h11), idx_30)
when _T_2008 :
node _T_2009 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_17.io.enq.bits, _T_2009
node _T_2010 = eq(UInt<5>(0h12), idx_30)
when _T_2010 :
node _T_2011 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_18.io.enq.bits, _T_2011
node _T_2012 = eq(UInt<5>(0h13), idx_30)
when _T_2012 :
node _T_2013 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_19.io.enq.bits, _T_2013
node _T_2014 = eq(UInt<5>(0h14), idx_30)
when _T_2014 :
node _T_2015 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_20.io.enq.bits, _T_2015
node _T_2016 = eq(UInt<5>(0h15), idx_30)
when _T_2016 :
node _T_2017 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_21.io.enq.bits, _T_2017
node _T_2018 = eq(UInt<5>(0h16), idx_30)
when _T_2018 :
node _T_2019 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_22.io.enq.bits, _T_2019
node _T_2020 = eq(UInt<5>(0h17), idx_30)
when _T_2020 :
node _T_2021 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_23.io.enq.bits, _T_2021
node _T_2022 = eq(UInt<5>(0h18), idx_30)
when _T_2022 :
node _T_2023 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_24.io.enq.bits, _T_2023
node _T_2024 = eq(UInt<5>(0h19), idx_30)
when _T_2024 :
node _T_2025 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_25.io.enq.bits, _T_2025
node _T_2026 = eq(UInt<5>(0h1a), idx_30)
when _T_2026 :
node _T_2027 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_26.io.enq.bits, _T_2027
node _T_2028 = eq(UInt<5>(0h1b), idx_30)
when _T_2028 :
node _T_2029 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_27.io.enq.bits, _T_2029
node _T_2030 = eq(UInt<5>(0h1c), idx_30)
when _T_2030 :
node _T_2031 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_28.io.enq.bits, _T_2031
node _T_2032 = eq(UInt<5>(0h1d), idx_30)
when _T_2032 :
node _T_2033 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_29.io.enq.bits, _T_2033
node _T_2034 = eq(UInt<5>(0h1e), idx_30)
when _T_2034 :
node _T_2035 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_30.io.enq.bits, _T_2035
node _T_2036 = eq(UInt<5>(0h1f), idx_30)
when _T_2036 :
node _T_2037 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_31.io.enq.bits, _T_2037
node _idx_T_31 = add(write_start_index, UInt<5>(0h1f))
node idx_31 = rem(_idx_T_31, UInt<6>(0h20))
node _T_2038 = eq(UInt<1>(0h0), idx_31)
when _T_2038 :
node _T_2039 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8.io.enq.bits, _T_2039
node _T_2040 = eq(UInt<1>(0h1), idx_31)
when _T_2040 :
node _T_2041 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_1.io.enq.bits, _T_2041
node _T_2042 = eq(UInt<2>(0h2), idx_31)
when _T_2042 :
node _T_2043 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_2.io.enq.bits, _T_2043
node _T_2044 = eq(UInt<2>(0h3), idx_31)
when _T_2044 :
node _T_2045 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_3.io.enq.bits, _T_2045
node _T_2046 = eq(UInt<3>(0h4), idx_31)
when _T_2046 :
node _T_2047 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_4.io.enq.bits, _T_2047
node _T_2048 = eq(UInt<3>(0h5), idx_31)
when _T_2048 :
node _T_2049 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_5.io.enq.bits, _T_2049
node _T_2050 = eq(UInt<3>(0h6), idx_31)
when _T_2050 :
node _T_2051 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_6.io.enq.bits, _T_2051
node _T_2052 = eq(UInt<3>(0h7), idx_31)
when _T_2052 :
node _T_2053 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_7.io.enq.bits, _T_2053
node _T_2054 = eq(UInt<4>(0h8), idx_31)
when _T_2054 :
node _T_2055 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_8.io.enq.bits, _T_2055
node _T_2056 = eq(UInt<4>(0h9), idx_31)
when _T_2056 :
node _T_2057 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_9.io.enq.bits, _T_2057
node _T_2058 = eq(UInt<4>(0ha), idx_31)
when _T_2058 :
node _T_2059 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_10.io.enq.bits, _T_2059
node _T_2060 = eq(UInt<4>(0hb), idx_31)
when _T_2060 :
node _T_2061 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_11.io.enq.bits, _T_2061
node _T_2062 = eq(UInt<4>(0hc), idx_31)
when _T_2062 :
node _T_2063 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_12.io.enq.bits, _T_2063
node _T_2064 = eq(UInt<4>(0hd), idx_31)
when _T_2064 :
node _T_2065 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_13.io.enq.bits, _T_2065
node _T_2066 = eq(UInt<4>(0he), idx_31)
when _T_2066 :
node _T_2067 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_14.io.enq.bits, _T_2067
node _T_2068 = eq(UInt<4>(0hf), idx_31)
when _T_2068 :
node _T_2069 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_15.io.enq.bits, _T_2069
node _T_2070 = eq(UInt<5>(0h10), idx_31)
when _T_2070 :
node _T_2071 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_16.io.enq.bits, _T_2071
node _T_2072 = eq(UInt<5>(0h11), idx_31)
when _T_2072 :
node _T_2073 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_17.io.enq.bits, _T_2073
node _T_2074 = eq(UInt<5>(0h12), idx_31)
when _T_2074 :
node _T_2075 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_18.io.enq.bits, _T_2075
node _T_2076 = eq(UInt<5>(0h13), idx_31)
when _T_2076 :
node _T_2077 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_19.io.enq.bits, _T_2077
node _T_2078 = eq(UInt<5>(0h14), idx_31)
when _T_2078 :
node _T_2079 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_20.io.enq.bits, _T_2079
node _T_2080 = eq(UInt<5>(0h15), idx_31)
when _T_2080 :
node _T_2081 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_21.io.enq.bits, _T_2081
node _T_2082 = eq(UInt<5>(0h16), idx_31)
when _T_2082 :
node _T_2083 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_22.io.enq.bits, _T_2083
node _T_2084 = eq(UInt<5>(0h17), idx_31)
when _T_2084 :
node _T_2085 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_23.io.enq.bits, _T_2085
node _T_2086 = eq(UInt<5>(0h18), idx_31)
when _T_2086 :
node _T_2087 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_24.io.enq.bits, _T_2087
node _T_2088 = eq(UInt<5>(0h19), idx_31)
when _T_2088 :
node _T_2089 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_25.io.enq.bits, _T_2089
node _T_2090 = eq(UInt<5>(0h1a), idx_31)
when _T_2090 :
node _T_2091 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_26.io.enq.bits, _T_2091
node _T_2092 = eq(UInt<5>(0h1b), idx_31)
when _T_2092 :
node _T_2093 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_27.io.enq.bits, _T_2093
node _T_2094 = eq(UInt<5>(0h1c), idx_31)
when _T_2094 :
node _T_2095 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_28.io.enq.bits, _T_2095
node _T_2096 = eq(UInt<5>(0h1d), idx_31)
when _T_2096 :
node _T_2097 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_29.io.enq.bits, _T_2097
node _T_2098 = eq(UInt<5>(0h1e), idx_31)
when _T_2098 :
node _T_2099 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_30.io.enq.bits, _T_2099
node _T_2100 = eq(UInt<5>(0h1f), idx_31)
when _T_2100 :
node _T_2101 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_31.io.enq.bits, _T_2101
node _len_to_write_T = sub(load_info_queue.io.deq.bits.end_byte, load_info_queue.io.deq.bits.start_byte)
node _len_to_write_T_1 = tail(_len_to_write_T, 1)
node len_to_write = add(_len_to_write_T_1, UInt<1>(0h1))
node wrap_len_index_wide = add(write_start_index, len_to_write)
node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20))
node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20))
when load_info_queue.io.deq.valid :
regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1))
node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1)
connect loginfo_cycles_11, _loginfo_cycles_T_23
node _T_2102 = asUInt(reset)
node _T_2103 = eq(_T_2102, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22
node _T_2104 = asUInt(reset)
node _T_2105 = eq(_T_2104, UInt<1>(0h0))
when _T_2105 :
printf(clock, UInt<1>(0h1), "memloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) : printf_23
node _all_queues_ready_T = and(Queue64_UInt8.io.enq.ready, Queue64_UInt8_1.io.enq.ready)
node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue64_UInt8_2.io.enq.ready)
node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue64_UInt8_3.io.enq.ready)
node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue64_UInt8_4.io.enq.ready)
node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue64_UInt8_5.io.enq.ready)
node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue64_UInt8_6.io.enq.ready)
node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue64_UInt8_7.io.enq.ready)
node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue64_UInt8_8.io.enq.ready)
node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue64_UInt8_9.io.enq.ready)
node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue64_UInt8_10.io.enq.ready)
node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue64_UInt8_11.io.enq.ready)
node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue64_UInt8_12.io.enq.ready)
node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue64_UInt8_13.io.enq.ready)
node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue64_UInt8_14.io.enq.ready)
node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue64_UInt8_15.io.enq.ready)
node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue64_UInt8_16.io.enq.ready)
node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue64_UInt8_17.io.enq.ready)
node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue64_UInt8_18.io.enq.ready)
node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue64_UInt8_19.io.enq.ready)
node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue64_UInt8_20.io.enq.ready)
node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue64_UInt8_21.io.enq.ready)
node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue64_UInt8_22.io.enq.ready)
node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue64_UInt8_23.io.enq.ready)
node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue64_UInt8_24.io.enq.ready)
node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue64_UInt8_25.io.enq.ready)
node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue64_UInt8_26.io.enq.ready)
node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue64_UInt8_27.io.enq.ready)
node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue64_UInt8_28.io.enq.ready)
node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue64_UInt8_29.io.enq.ready)
node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue64_UInt8_30.io.enq.ready)
node all_queues_ready = and(_all_queues_ready_T_29, Queue64_UInt8_31.io.enq.ready)
node _load_info_queue_io_deq_ready_T = and(io.l2helperUser.resp.valid, all_queues_ready)
connect load_info_queue.io.deq.ready, _load_info_queue_io_deq_ready_T
node _io_l2helperUser_resp_ready_T = and(load_info_queue.io.deq.valid, all_queues_ready)
connect io.l2helperUser.resp.ready, _io_l2helperUser_resp_ready_T
node _resp_fire_allqueues_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node resp_fire_allqueues = and(_resp_fire_allqueues_T, all_queues_ready)
when resp_fire_allqueues :
connect write_start_index, wrap_len_index_end
node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1)
node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4)
node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5)
node _T_2106 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2107 = and(_T_2106, use_this_queue)
node _T_2108 = and(_T_2107, all_queues_ready)
connect Queue64_UInt8.io.enq.valid, _T_2108
node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7)
node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10)
node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11)
node _T_2109 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2110 = and(_T_2109, use_this_queue_1)
node _T_2111 = and(_T_2110, all_queues_ready)
connect Queue64_UInt8_1.io.enq.valid, _T_2111
node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13)
node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16)
node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17)
node _T_2112 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2113 = and(_T_2112, use_this_queue_2)
node _T_2114 = and(_T_2113, all_queues_ready)
connect Queue64_UInt8_2.io.enq.valid, _T_2114
node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19)
node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22)
node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23)
node _T_2115 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2116 = and(_T_2115, use_this_queue_3)
node _T_2117 = and(_T_2116, all_queues_ready)
connect Queue64_UInt8_3.io.enq.valid, _T_2117
node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25)
node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28)
node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29)
node _T_2118 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2119 = and(_T_2118, use_this_queue_4)
node _T_2120 = and(_T_2119, all_queues_ready)
connect Queue64_UInt8_4.io.enq.valid, _T_2120
node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31)
node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34)
node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35)
node _T_2121 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2122 = and(_T_2121, use_this_queue_5)
node _T_2123 = and(_T_2122, all_queues_ready)
connect Queue64_UInt8_5.io.enq.valid, _T_2123
node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37)
node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40)
node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41)
node _T_2124 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2125 = and(_T_2124, use_this_queue_6)
node _T_2126 = and(_T_2125, all_queues_ready)
connect Queue64_UInt8_6.io.enq.valid, _T_2126
node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43)
node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46)
node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47)
node _T_2127 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2128 = and(_T_2127, use_this_queue_7)
node _T_2129 = and(_T_2128, all_queues_ready)
connect Queue64_UInt8_7.io.enq.valid, _T_2129
node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49)
node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52)
node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53)
node _T_2130 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2131 = and(_T_2130, use_this_queue_8)
node _T_2132 = and(_T_2131, all_queues_ready)
connect Queue64_UInt8_8.io.enq.valid, _T_2132
node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55)
node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58)
node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59)
node _T_2133 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2134 = and(_T_2133, use_this_queue_9)
node _T_2135 = and(_T_2134, all_queues_ready)
connect Queue64_UInt8_9.io.enq.valid, _T_2135
node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61)
node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64)
node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65)
node _T_2136 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2137 = and(_T_2136, use_this_queue_10)
node _T_2138 = and(_T_2137, all_queues_ready)
connect Queue64_UInt8_10.io.enq.valid, _T_2138
node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67)
node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70)
node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71)
node _T_2139 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2140 = and(_T_2139, use_this_queue_11)
node _T_2141 = and(_T_2140, all_queues_ready)
connect Queue64_UInt8_11.io.enq.valid, _T_2141
node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73)
node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76)
node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77)
node _T_2142 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2143 = and(_T_2142, use_this_queue_12)
node _T_2144 = and(_T_2143, all_queues_ready)
connect Queue64_UInt8_12.io.enq.valid, _T_2144
node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79)
node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82)
node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83)
node _T_2145 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2146 = and(_T_2145, use_this_queue_13)
node _T_2147 = and(_T_2146, all_queues_ready)
connect Queue64_UInt8_13.io.enq.valid, _T_2147
node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85)
node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88)
node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89)
node _T_2148 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2149 = and(_T_2148, use_this_queue_14)
node _T_2150 = and(_T_2149, all_queues_ready)
connect Queue64_UInt8_14.io.enq.valid, _T_2150
node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91)
node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94)
node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95)
node _T_2151 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2152 = and(_T_2151, use_this_queue_15)
node _T_2153 = and(_T_2152, all_queues_ready)
connect Queue64_UInt8_15.io.enq.valid, _T_2153
node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97)
node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100)
node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101)
node _T_2154 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2155 = and(_T_2154, use_this_queue_16)
node _T_2156 = and(_T_2155, all_queues_ready)
connect Queue64_UInt8_16.io.enq.valid, _T_2156
node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103)
node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106)
node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107)
node _T_2157 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2158 = and(_T_2157, use_this_queue_17)
node _T_2159 = and(_T_2158, all_queues_ready)
connect Queue64_UInt8_17.io.enq.valid, _T_2159
node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109)
node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112)
node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113)
node _T_2160 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2161 = and(_T_2160, use_this_queue_18)
node _T_2162 = and(_T_2161, all_queues_ready)
connect Queue64_UInt8_18.io.enq.valid, _T_2162
node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115)
node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118)
node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119)
node _T_2163 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2164 = and(_T_2163, use_this_queue_19)
node _T_2165 = and(_T_2164, all_queues_ready)
connect Queue64_UInt8_19.io.enq.valid, _T_2165
node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121)
node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124)
node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125)
node _T_2166 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2167 = and(_T_2166, use_this_queue_20)
node _T_2168 = and(_T_2167, all_queues_ready)
connect Queue64_UInt8_20.io.enq.valid, _T_2168
node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127)
node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130)
node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131)
node _T_2169 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2170 = and(_T_2169, use_this_queue_21)
node _T_2171 = and(_T_2170, all_queues_ready)
connect Queue64_UInt8_21.io.enq.valid, _T_2171
node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133)
node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136)
node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137)
node _T_2172 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2173 = and(_T_2172, use_this_queue_22)
node _T_2174 = and(_T_2173, all_queues_ready)
connect Queue64_UInt8_22.io.enq.valid, _T_2174
node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139)
node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142)
node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143)
node _T_2175 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2176 = and(_T_2175, use_this_queue_23)
node _T_2177 = and(_T_2176, all_queues_ready)
connect Queue64_UInt8_23.io.enq.valid, _T_2177
node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145)
node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148)
node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149)
node _T_2178 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2179 = and(_T_2178, use_this_queue_24)
node _T_2180 = and(_T_2179, all_queues_ready)
connect Queue64_UInt8_24.io.enq.valid, _T_2180
node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151)
node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154)
node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155)
node _T_2181 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2182 = and(_T_2181, use_this_queue_25)
node _T_2183 = and(_T_2182, all_queues_ready)
connect Queue64_UInt8_25.io.enq.valid, _T_2183
node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157)
node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160)
node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161)
node _T_2184 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2185 = and(_T_2184, use_this_queue_26)
node _T_2186 = and(_T_2185, all_queues_ready)
connect Queue64_UInt8_26.io.enq.valid, _T_2186
node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163)
node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166)
node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167)
node _T_2187 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2188 = and(_T_2187, use_this_queue_27)
node _T_2189 = and(_T_2188, all_queues_ready)
connect Queue64_UInt8_27.io.enq.valid, _T_2189
node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169)
node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172)
node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173)
node _T_2190 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2191 = and(_T_2190, use_this_queue_28)
node _T_2192 = and(_T_2191, all_queues_ready)
connect Queue64_UInt8_28.io.enq.valid, _T_2192
node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175)
node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178)
node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179)
node _T_2193 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2194 = and(_T_2193, use_this_queue_29)
node _T_2195 = and(_T_2194, all_queues_ready)
connect Queue64_UInt8_29.io.enq.valid, _T_2195
node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181)
node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184)
node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185)
node _T_2196 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2197 = and(_T_2196, use_this_queue_30)
node _T_2198 = and(_T_2197, all_queues_ready)
connect Queue64_UInt8_30.io.enq.valid, _T_2198
node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187)
node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190)
node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191)
node _T_2199 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2200 = and(_T_2199, use_this_queue_31)
node _T_2201 = and(_T_2200, all_queues_ready)
connect Queue64_UInt8_31.io.enq.valid, _T_2201
when Queue64_UInt8.io.deq.valid :
regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1))
node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1)
connect loginfo_cycles_12, _loginfo_cycles_T_25
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24
node _T_2204 = asUInt(reset)
node _T_2205 = eq(_T_2204, UInt<1>(0h0))
when _T_2205 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h0), Queue64_UInt8.io.deq.bits) : printf_25
when Queue64_UInt8_1.io.deq.valid :
regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1))
node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1)
connect loginfo_cycles_13, _loginfo_cycles_T_27
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h1), Queue64_UInt8_1.io.deq.bits) : printf_27
when Queue64_UInt8_2.io.deq.valid :
regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1))
node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1)
connect loginfo_cycles_14, _loginfo_cycles_T_29
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28
node _T_2212 = asUInt(reset)
node _T_2213 = eq(_T_2212, UInt<1>(0h0))
when _T_2213 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h2), Queue64_UInt8_2.io.deq.bits) : printf_29
when Queue64_UInt8_3.io.deq.valid :
regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1))
node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1)
connect loginfo_cycles_15, _loginfo_cycles_T_31
node _T_2214 = asUInt(reset)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30
node _T_2216 = asUInt(reset)
node _T_2217 = eq(_T_2216, UInt<1>(0h0))
when _T_2217 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h3), Queue64_UInt8_3.io.deq.bits) : printf_31
when Queue64_UInt8_4.io.deq.valid :
regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1))
node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1)
connect loginfo_cycles_16, _loginfo_cycles_T_33
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32
node _T_2220 = asUInt(reset)
node _T_2221 = eq(_T_2220, UInt<1>(0h0))
when _T_2221 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h4), Queue64_UInt8_4.io.deq.bits) : printf_33
when Queue64_UInt8_5.io.deq.valid :
regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1))
node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1)
connect loginfo_cycles_17, _loginfo_cycles_T_35
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h5), Queue64_UInt8_5.io.deq.bits) : printf_35
when Queue64_UInt8_6.io.deq.valid :
regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1))
node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1)
connect loginfo_cycles_18, _loginfo_cycles_T_37
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36
node _T_2228 = asUInt(reset)
node _T_2229 = eq(_T_2228, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h6), Queue64_UInt8_6.io.deq.bits) : printf_37
when Queue64_UInt8_7.io.deq.valid :
regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1))
node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1)
connect loginfo_cycles_19, _loginfo_cycles_T_39
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38
node _T_2232 = asUInt(reset)
node _T_2233 = eq(_T_2232, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h7), Queue64_UInt8_7.io.deq.bits) : printf_39
when Queue64_UInt8_8.io.deq.valid :
regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1))
node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1)
connect loginfo_cycles_20, _loginfo_cycles_T_41
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40
node _T_2236 = asUInt(reset)
node _T_2237 = eq(_T_2236, UInt<1>(0h0))
when _T_2237 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h8), Queue64_UInt8_8.io.deq.bits) : printf_41
when Queue64_UInt8_9.io.deq.valid :
regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1))
node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1)
connect loginfo_cycles_21, _loginfo_cycles_T_43
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42
node _T_2240 = asUInt(reset)
node _T_2241 = eq(_T_2240, UInt<1>(0h0))
when _T_2241 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h9), Queue64_UInt8_9.io.deq.bits) : printf_43
when Queue64_UInt8_10.io.deq.valid :
regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1))
node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1)
connect loginfo_cycles_22, _loginfo_cycles_T_45
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44
node _T_2244 = asUInt(reset)
node _T_2245 = eq(_T_2244, UInt<1>(0h0))
when _T_2245 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0ha), Queue64_UInt8_10.io.deq.bits) : printf_45
when Queue64_UInt8_11.io.deq.valid :
regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1))
node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1)
connect loginfo_cycles_23, _loginfo_cycles_T_47
node _T_2246 = asUInt(reset)
node _T_2247 = eq(_T_2246, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46
node _T_2248 = asUInt(reset)
node _T_2249 = eq(_T_2248, UInt<1>(0h0))
when _T_2249 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hb), Queue64_UInt8_11.io.deq.bits) : printf_47
when Queue64_UInt8_12.io.deq.valid :
regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1))
node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1)
connect loginfo_cycles_24, _loginfo_cycles_T_49
node _T_2250 = asUInt(reset)
node _T_2251 = eq(_T_2250, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48
node _T_2252 = asUInt(reset)
node _T_2253 = eq(_T_2252, UInt<1>(0h0))
when _T_2253 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hc), Queue64_UInt8_12.io.deq.bits) : printf_49
when Queue64_UInt8_13.io.deq.valid :
regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1))
node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1)
connect loginfo_cycles_25, _loginfo_cycles_T_51
node _T_2254 = asUInt(reset)
node _T_2255 = eq(_T_2254, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hd), Queue64_UInt8_13.io.deq.bits) : printf_51
when Queue64_UInt8_14.io.deq.valid :
regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1))
node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1)
connect loginfo_cycles_26, _loginfo_cycles_T_53
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52
node _T_2260 = asUInt(reset)
node _T_2261 = eq(_T_2260, UInt<1>(0h0))
when _T_2261 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0he), Queue64_UInt8_14.io.deq.bits) : printf_53
when Queue64_UInt8_15.io.deq.valid :
regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1))
node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1)
connect loginfo_cycles_27, _loginfo_cycles_T_55
node _T_2262 = asUInt(reset)
node _T_2263 = eq(_T_2262, UInt<1>(0h0))
when _T_2263 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54
node _T_2264 = asUInt(reset)
node _T_2265 = eq(_T_2264, UInt<1>(0h0))
when _T_2265 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hf), Queue64_UInt8_15.io.deq.bits) : printf_55
when Queue64_UInt8_16.io.deq.valid :
regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1))
node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1)
connect loginfo_cycles_28, _loginfo_cycles_T_57
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56
node _T_2268 = asUInt(reset)
node _T_2269 = eq(_T_2268, UInt<1>(0h0))
when _T_2269 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h10), Queue64_UInt8_16.io.deq.bits) : printf_57
when Queue64_UInt8_17.io.deq.valid :
regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1))
node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1)
connect loginfo_cycles_29, _loginfo_cycles_T_59
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h11), Queue64_UInt8_17.io.deq.bits) : printf_59
when Queue64_UInt8_18.io.deq.valid :
regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1))
node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1)
connect loginfo_cycles_30, _loginfo_cycles_T_61
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h12), Queue64_UInt8_18.io.deq.bits) : printf_61
when Queue64_UInt8_19.io.deq.valid :
regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1))
node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1)
connect loginfo_cycles_31, _loginfo_cycles_T_63
node _T_2278 = asUInt(reset)
node _T_2279 = eq(_T_2278, UInt<1>(0h0))
when _T_2279 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62
node _T_2280 = asUInt(reset)
node _T_2281 = eq(_T_2280, UInt<1>(0h0))
when _T_2281 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h13), Queue64_UInt8_19.io.deq.bits) : printf_63
when Queue64_UInt8_20.io.deq.valid :
regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1))
node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1)
connect loginfo_cycles_32, _loginfo_cycles_T_65
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h14), Queue64_UInt8_20.io.deq.bits) : printf_65
when Queue64_UInt8_21.io.deq.valid :
regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1))
node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1)
connect loginfo_cycles_33, _loginfo_cycles_T_67
node _T_2286 = asUInt(reset)
node _T_2287 = eq(_T_2286, UInt<1>(0h0))
when _T_2287 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h15), Queue64_UInt8_21.io.deq.bits) : printf_67
when Queue64_UInt8_22.io.deq.valid :
regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1))
node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1)
connect loginfo_cycles_34, _loginfo_cycles_T_69
node _T_2290 = asUInt(reset)
node _T_2291 = eq(_T_2290, UInt<1>(0h0))
when _T_2291 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h16), Queue64_UInt8_22.io.deq.bits) : printf_69
when Queue64_UInt8_23.io.deq.valid :
regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1))
node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1)
connect loginfo_cycles_35, _loginfo_cycles_T_71
node _T_2294 = asUInt(reset)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
when _T_2295 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h17), Queue64_UInt8_23.io.deq.bits) : printf_71
when Queue64_UInt8_24.io.deq.valid :
regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1))
node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1)
connect loginfo_cycles_36, _loginfo_cycles_T_73
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h18), Queue64_UInt8_24.io.deq.bits) : printf_73
when Queue64_UInt8_25.io.deq.valid :
regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1))
node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1)
connect loginfo_cycles_37, _loginfo_cycles_T_75
node _T_2302 = asUInt(reset)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
when _T_2303 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h19), Queue64_UInt8_25.io.deq.bits) : printf_75
when Queue64_UInt8_26.io.deq.valid :
regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1))
node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1)
connect loginfo_cycles_38, _loginfo_cycles_T_77
node _T_2306 = asUInt(reset)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
when _T_2307 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_76
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1a), Queue64_UInt8_26.io.deq.bits) : printf_77
when Queue64_UInt8_27.io.deq.valid :
regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1))
node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1)
connect loginfo_cycles_39, _loginfo_cycles_T_79
node _T_2310 = asUInt(reset)
node _T_2311 = eq(_T_2310, UInt<1>(0h0))
when _T_2311 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_78
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1b), Queue64_UInt8_27.io.deq.bits) : printf_79
when Queue64_UInt8_28.io.deq.valid :
regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1))
node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1)
connect loginfo_cycles_40, _loginfo_cycles_T_81
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_80
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1c), Queue64_UInt8_28.io.deq.bits) : printf_81
when Queue64_UInt8_29.io.deq.valid :
regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1))
node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1)
connect loginfo_cycles_41, _loginfo_cycles_T_83
node _T_2318 = asUInt(reset)
node _T_2319 = eq(_T_2318, UInt<1>(0h0))
when _T_2319 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_82
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1d), Queue64_UInt8_29.io.deq.bits) : printf_83
when Queue64_UInt8_30.io.deq.valid :
regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1))
node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1)
connect loginfo_cycles_42, _loginfo_cycles_T_85
node _T_2322 = asUInt(reset)
node _T_2323 = eq(_T_2322, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_84
node _T_2324 = asUInt(reset)
node _T_2325 = eq(_T_2324, UInt<1>(0h0))
when _T_2325 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1e), Queue64_UInt8_30.io.deq.bits) : printf_85
when Queue64_UInt8_31.io.deq.valid :
regreset loginfo_cycles_43 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_86 = add(loginfo_cycles_43, UInt<1>(0h1))
node _loginfo_cycles_T_87 = tail(_loginfo_cycles_T_86, 1)
connect loginfo_cycles_43, _loginfo_cycles_T_87
node _T_2326 = asUInt(reset)
node _T_2327 = eq(_T_2326, UInt<1>(0h0))
when _T_2327 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_43) : printf_86
node _T_2328 = asUInt(reset)
node _T_2329 = eq(_T_2328, UInt<1>(0h0))
when _T_2329 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1f), Queue64_UInt8_31.io.deq.bits) : printf_87
regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
regreset len_already_consumed : UInt<64>, clock, reset, UInt<64>(0h0)
wire remapVecData : UInt<8>[32]
wire remapVecValids : UInt<1>[32]
wire remapVecReadys : UInt<1>[32]
connect remapVecData[0], UInt<1>(0h0)
connect remapVecValids[0], UInt<1>(0h0)
connect Queue64_UInt8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[1], UInt<1>(0h0)
connect remapVecValids[1], UInt<1>(0h0)
connect Queue64_UInt8_1.io.deq.ready, UInt<1>(0h0)
connect remapVecData[2], UInt<1>(0h0)
connect remapVecValids[2], UInt<1>(0h0)
connect Queue64_UInt8_2.io.deq.ready, UInt<1>(0h0)
connect remapVecData[3], UInt<1>(0h0)
connect remapVecValids[3], UInt<1>(0h0)
connect Queue64_UInt8_3.io.deq.ready, UInt<1>(0h0)
connect remapVecData[4], UInt<1>(0h0)
connect remapVecValids[4], UInt<1>(0h0)
connect Queue64_UInt8_4.io.deq.ready, UInt<1>(0h0)
connect remapVecData[5], UInt<1>(0h0)
connect remapVecValids[5], UInt<1>(0h0)
connect Queue64_UInt8_5.io.deq.ready, UInt<1>(0h0)
connect remapVecData[6], UInt<1>(0h0)
connect remapVecValids[6], UInt<1>(0h0)
connect Queue64_UInt8_6.io.deq.ready, UInt<1>(0h0)
connect remapVecData[7], UInt<1>(0h0)
connect remapVecValids[7], UInt<1>(0h0)
connect Queue64_UInt8_7.io.deq.ready, UInt<1>(0h0)
connect remapVecData[8], UInt<1>(0h0)
connect remapVecValids[8], UInt<1>(0h0)
connect Queue64_UInt8_8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[9], UInt<1>(0h0)
connect remapVecValids[9], UInt<1>(0h0)
connect Queue64_UInt8_9.io.deq.ready, UInt<1>(0h0)
connect remapVecData[10], UInt<1>(0h0)
connect remapVecValids[10], UInt<1>(0h0)
connect Queue64_UInt8_10.io.deq.ready, UInt<1>(0h0)
connect remapVecData[11], UInt<1>(0h0)
connect remapVecValids[11], UInt<1>(0h0)
connect Queue64_UInt8_11.io.deq.ready, UInt<1>(0h0)
connect remapVecData[12], UInt<1>(0h0)
connect remapVecValids[12], UInt<1>(0h0)
connect Queue64_UInt8_12.io.deq.ready, UInt<1>(0h0)
connect remapVecData[13], UInt<1>(0h0)
connect remapVecValids[13], UInt<1>(0h0)
connect Queue64_UInt8_13.io.deq.ready, UInt<1>(0h0)
connect remapVecData[14], UInt<1>(0h0)
connect remapVecValids[14], UInt<1>(0h0)
connect Queue64_UInt8_14.io.deq.ready, UInt<1>(0h0)
connect remapVecData[15], UInt<1>(0h0)
connect remapVecValids[15], UInt<1>(0h0)
connect Queue64_UInt8_15.io.deq.ready, UInt<1>(0h0)
connect remapVecData[16], UInt<1>(0h0)
connect remapVecValids[16], UInt<1>(0h0)
connect Queue64_UInt8_16.io.deq.ready, UInt<1>(0h0)
connect remapVecData[17], UInt<1>(0h0)
connect remapVecValids[17], UInt<1>(0h0)
connect Queue64_UInt8_17.io.deq.ready, UInt<1>(0h0)
connect remapVecData[18], UInt<1>(0h0)
connect remapVecValids[18], UInt<1>(0h0)
connect Queue64_UInt8_18.io.deq.ready, UInt<1>(0h0)
connect remapVecData[19], UInt<1>(0h0)
connect remapVecValids[19], UInt<1>(0h0)
connect Queue64_UInt8_19.io.deq.ready, UInt<1>(0h0)
connect remapVecData[20], UInt<1>(0h0)
connect remapVecValids[20], UInt<1>(0h0)
connect Queue64_UInt8_20.io.deq.ready, UInt<1>(0h0)
connect remapVecData[21], UInt<1>(0h0)
connect remapVecValids[21], UInt<1>(0h0)
connect Queue64_UInt8_21.io.deq.ready, UInt<1>(0h0)
connect remapVecData[22], UInt<1>(0h0)
connect remapVecValids[22], UInt<1>(0h0)
connect Queue64_UInt8_22.io.deq.ready, UInt<1>(0h0)
connect remapVecData[23], UInt<1>(0h0)
connect remapVecValids[23], UInt<1>(0h0)
connect Queue64_UInt8_23.io.deq.ready, UInt<1>(0h0)
connect remapVecData[24], UInt<1>(0h0)
connect remapVecValids[24], UInt<1>(0h0)
connect Queue64_UInt8_24.io.deq.ready, UInt<1>(0h0)
connect remapVecData[25], UInt<1>(0h0)
connect remapVecValids[25], UInt<1>(0h0)
connect Queue64_UInt8_25.io.deq.ready, UInt<1>(0h0)
connect remapVecData[26], UInt<1>(0h0)
connect remapVecValids[26], UInt<1>(0h0)
connect Queue64_UInt8_26.io.deq.ready, UInt<1>(0h0)
connect remapVecData[27], UInt<1>(0h0)
connect remapVecValids[27], UInt<1>(0h0)
connect Queue64_UInt8_27.io.deq.ready, UInt<1>(0h0)
connect remapVecData[28], UInt<1>(0h0)
connect remapVecValids[28], UInt<1>(0h0)
connect Queue64_UInt8_28.io.deq.ready, UInt<1>(0h0)
connect remapVecData[29], UInt<1>(0h0)
connect remapVecValids[29], UInt<1>(0h0)
connect Queue64_UInt8_29.io.deq.ready, UInt<1>(0h0)
connect remapVecData[30], UInt<1>(0h0)
connect remapVecValids[30], UInt<1>(0h0)
connect Queue64_UInt8_30.io.deq.ready, UInt<1>(0h0)
connect remapVecData[31], UInt<1>(0h0)
connect remapVecValids[31], UInt<1>(0h0)
connect Queue64_UInt8_31.io.deq.ready, UInt<1>(0h0)
node _remapindex_T = add(UInt<1>(0h0), read_start_index)
node remapindex = rem(_remapindex_T, UInt<6>(0h20))
node _T_2330 = eq(UInt<1>(0h0), remapindex)
when _T_2330 :
connect remapVecData[0], Queue64_UInt8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[0]
node _T_2331 = eq(UInt<1>(0h1), remapindex)
when _T_2331 :
connect remapVecData[0], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[0]
node _T_2332 = eq(UInt<2>(0h2), remapindex)
when _T_2332 :
connect remapVecData[0], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[0]
node _T_2333 = eq(UInt<2>(0h3), remapindex)
when _T_2333 :
connect remapVecData[0], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[0]
node _T_2334 = eq(UInt<3>(0h4), remapindex)
when _T_2334 :
connect remapVecData[0], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[0]
node _T_2335 = eq(UInt<3>(0h5), remapindex)
when _T_2335 :
connect remapVecData[0], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[0]
node _T_2336 = eq(UInt<3>(0h6), remapindex)
when _T_2336 :
connect remapVecData[0], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[0]
node _T_2337 = eq(UInt<3>(0h7), remapindex)
when _T_2337 :
connect remapVecData[0], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[0]
node _T_2338 = eq(UInt<4>(0h8), remapindex)
when _T_2338 :
connect remapVecData[0], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[0]
node _T_2339 = eq(UInt<4>(0h9), remapindex)
when _T_2339 :
connect remapVecData[0], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[0]
node _T_2340 = eq(UInt<4>(0ha), remapindex)
when _T_2340 :
connect remapVecData[0], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[0]
node _T_2341 = eq(UInt<4>(0hb), remapindex)
when _T_2341 :
connect remapVecData[0], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[0]
node _T_2342 = eq(UInt<4>(0hc), remapindex)
when _T_2342 :
connect remapVecData[0], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[0]
node _T_2343 = eq(UInt<4>(0hd), remapindex)
when _T_2343 :
connect remapVecData[0], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[0]
node _T_2344 = eq(UInt<4>(0he), remapindex)
when _T_2344 :
connect remapVecData[0], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[0]
node _T_2345 = eq(UInt<4>(0hf), remapindex)
when _T_2345 :
connect remapVecData[0], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[0]
node _T_2346 = eq(UInt<5>(0h10), remapindex)
when _T_2346 :
connect remapVecData[0], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[0]
node _T_2347 = eq(UInt<5>(0h11), remapindex)
when _T_2347 :
connect remapVecData[0], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[0]
node _T_2348 = eq(UInt<5>(0h12), remapindex)
when _T_2348 :
connect remapVecData[0], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[0]
node _T_2349 = eq(UInt<5>(0h13), remapindex)
when _T_2349 :
connect remapVecData[0], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[0]
node _T_2350 = eq(UInt<5>(0h14), remapindex)
when _T_2350 :
connect remapVecData[0], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[0]
node _T_2351 = eq(UInt<5>(0h15), remapindex)
when _T_2351 :
connect remapVecData[0], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[0]
node _T_2352 = eq(UInt<5>(0h16), remapindex)
when _T_2352 :
connect remapVecData[0], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[0]
node _T_2353 = eq(UInt<5>(0h17), remapindex)
when _T_2353 :
connect remapVecData[0], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[0]
node _T_2354 = eq(UInt<5>(0h18), remapindex)
when _T_2354 :
connect remapVecData[0], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[0]
node _T_2355 = eq(UInt<5>(0h19), remapindex)
when _T_2355 :
connect remapVecData[0], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[0]
node _T_2356 = eq(UInt<5>(0h1a), remapindex)
when _T_2356 :
connect remapVecData[0], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[0]
node _T_2357 = eq(UInt<5>(0h1b), remapindex)
when _T_2357 :
connect remapVecData[0], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[0]
node _T_2358 = eq(UInt<5>(0h1c), remapindex)
when _T_2358 :
connect remapVecData[0], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[0]
node _T_2359 = eq(UInt<5>(0h1d), remapindex)
when _T_2359 :
connect remapVecData[0], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[0]
node _T_2360 = eq(UInt<5>(0h1e), remapindex)
when _T_2360 :
connect remapVecData[0], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[0]
node _T_2361 = eq(UInt<5>(0h1f), remapindex)
when _T_2361 :
connect remapVecData[0], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[0]
node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index)
node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20))
node _T_2362 = eq(UInt<1>(0h0), remapindex_1)
when _T_2362 :
connect remapVecData[1], Queue64_UInt8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[1]
node _T_2363 = eq(UInt<1>(0h1), remapindex_1)
when _T_2363 :
connect remapVecData[1], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[1]
node _T_2364 = eq(UInt<2>(0h2), remapindex_1)
when _T_2364 :
connect remapVecData[1], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[1]
node _T_2365 = eq(UInt<2>(0h3), remapindex_1)
when _T_2365 :
connect remapVecData[1], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[1]
node _T_2366 = eq(UInt<3>(0h4), remapindex_1)
when _T_2366 :
connect remapVecData[1], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[1]
node _T_2367 = eq(UInt<3>(0h5), remapindex_1)
when _T_2367 :
connect remapVecData[1], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[1]
node _T_2368 = eq(UInt<3>(0h6), remapindex_1)
when _T_2368 :
connect remapVecData[1], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[1]
node _T_2369 = eq(UInt<3>(0h7), remapindex_1)
when _T_2369 :
connect remapVecData[1], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[1]
node _T_2370 = eq(UInt<4>(0h8), remapindex_1)
when _T_2370 :
connect remapVecData[1], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[1]
node _T_2371 = eq(UInt<4>(0h9), remapindex_1)
when _T_2371 :
connect remapVecData[1], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[1]
node _T_2372 = eq(UInt<4>(0ha), remapindex_1)
when _T_2372 :
connect remapVecData[1], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[1]
node _T_2373 = eq(UInt<4>(0hb), remapindex_1)
when _T_2373 :
connect remapVecData[1], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[1]
node _T_2374 = eq(UInt<4>(0hc), remapindex_1)
when _T_2374 :
connect remapVecData[1], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[1]
node _T_2375 = eq(UInt<4>(0hd), remapindex_1)
when _T_2375 :
connect remapVecData[1], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[1]
node _T_2376 = eq(UInt<4>(0he), remapindex_1)
when _T_2376 :
connect remapVecData[1], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[1]
node _T_2377 = eq(UInt<4>(0hf), remapindex_1)
when _T_2377 :
connect remapVecData[1], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[1]
node _T_2378 = eq(UInt<5>(0h10), remapindex_1)
when _T_2378 :
connect remapVecData[1], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[1]
node _T_2379 = eq(UInt<5>(0h11), remapindex_1)
when _T_2379 :
connect remapVecData[1], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[1]
node _T_2380 = eq(UInt<5>(0h12), remapindex_1)
when _T_2380 :
connect remapVecData[1], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[1]
node _T_2381 = eq(UInt<5>(0h13), remapindex_1)
when _T_2381 :
connect remapVecData[1], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[1]
node _T_2382 = eq(UInt<5>(0h14), remapindex_1)
when _T_2382 :
connect remapVecData[1], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[1]
node _T_2383 = eq(UInt<5>(0h15), remapindex_1)
when _T_2383 :
connect remapVecData[1], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[1]
node _T_2384 = eq(UInt<5>(0h16), remapindex_1)
when _T_2384 :
connect remapVecData[1], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[1]
node _T_2385 = eq(UInt<5>(0h17), remapindex_1)
when _T_2385 :
connect remapVecData[1], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[1]
node _T_2386 = eq(UInt<5>(0h18), remapindex_1)
when _T_2386 :
connect remapVecData[1], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[1]
node _T_2387 = eq(UInt<5>(0h19), remapindex_1)
when _T_2387 :
connect remapVecData[1], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[1]
node _T_2388 = eq(UInt<5>(0h1a), remapindex_1)
when _T_2388 :
connect remapVecData[1], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[1]
node _T_2389 = eq(UInt<5>(0h1b), remapindex_1)
when _T_2389 :
connect remapVecData[1], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[1]
node _T_2390 = eq(UInt<5>(0h1c), remapindex_1)
when _T_2390 :
connect remapVecData[1], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[1]
node _T_2391 = eq(UInt<5>(0h1d), remapindex_1)
when _T_2391 :
connect remapVecData[1], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[1]
node _T_2392 = eq(UInt<5>(0h1e), remapindex_1)
when _T_2392 :
connect remapVecData[1], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[1]
node _T_2393 = eq(UInt<5>(0h1f), remapindex_1)
when _T_2393 :
connect remapVecData[1], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[1]
node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index)
node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20))
node _T_2394 = eq(UInt<1>(0h0), remapindex_2)
when _T_2394 :
connect remapVecData[2], Queue64_UInt8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[2]
node _T_2395 = eq(UInt<1>(0h1), remapindex_2)
when _T_2395 :
connect remapVecData[2], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[2]
node _T_2396 = eq(UInt<2>(0h2), remapindex_2)
when _T_2396 :
connect remapVecData[2], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[2]
node _T_2397 = eq(UInt<2>(0h3), remapindex_2)
when _T_2397 :
connect remapVecData[2], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[2]
node _T_2398 = eq(UInt<3>(0h4), remapindex_2)
when _T_2398 :
connect remapVecData[2], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[2]
node _T_2399 = eq(UInt<3>(0h5), remapindex_2)
when _T_2399 :
connect remapVecData[2], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[2]
node _T_2400 = eq(UInt<3>(0h6), remapindex_2)
when _T_2400 :
connect remapVecData[2], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[2]
node _T_2401 = eq(UInt<3>(0h7), remapindex_2)
when _T_2401 :
connect remapVecData[2], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[2]
node _T_2402 = eq(UInt<4>(0h8), remapindex_2)
when _T_2402 :
connect remapVecData[2], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[2]
node _T_2403 = eq(UInt<4>(0h9), remapindex_2)
when _T_2403 :
connect remapVecData[2], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[2]
node _T_2404 = eq(UInt<4>(0ha), remapindex_2)
when _T_2404 :
connect remapVecData[2], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[2]
node _T_2405 = eq(UInt<4>(0hb), remapindex_2)
when _T_2405 :
connect remapVecData[2], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[2]
node _T_2406 = eq(UInt<4>(0hc), remapindex_2)
when _T_2406 :
connect remapVecData[2], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[2]
node _T_2407 = eq(UInt<4>(0hd), remapindex_2)
when _T_2407 :
connect remapVecData[2], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[2]
node _T_2408 = eq(UInt<4>(0he), remapindex_2)
when _T_2408 :
connect remapVecData[2], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[2]
node _T_2409 = eq(UInt<4>(0hf), remapindex_2)
when _T_2409 :
connect remapVecData[2], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[2]
node _T_2410 = eq(UInt<5>(0h10), remapindex_2)
when _T_2410 :
connect remapVecData[2], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[2]
node _T_2411 = eq(UInt<5>(0h11), remapindex_2)
when _T_2411 :
connect remapVecData[2], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[2]
node _T_2412 = eq(UInt<5>(0h12), remapindex_2)
when _T_2412 :
connect remapVecData[2], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[2]
node _T_2413 = eq(UInt<5>(0h13), remapindex_2)
when _T_2413 :
connect remapVecData[2], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[2]
node _T_2414 = eq(UInt<5>(0h14), remapindex_2)
when _T_2414 :
connect remapVecData[2], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[2]
node _T_2415 = eq(UInt<5>(0h15), remapindex_2)
when _T_2415 :
connect remapVecData[2], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[2]
node _T_2416 = eq(UInt<5>(0h16), remapindex_2)
when _T_2416 :
connect remapVecData[2], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[2]
node _T_2417 = eq(UInt<5>(0h17), remapindex_2)
when _T_2417 :
connect remapVecData[2], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[2]
node _T_2418 = eq(UInt<5>(0h18), remapindex_2)
when _T_2418 :
connect remapVecData[2], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[2]
node _T_2419 = eq(UInt<5>(0h19), remapindex_2)
when _T_2419 :
connect remapVecData[2], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[2]
node _T_2420 = eq(UInt<5>(0h1a), remapindex_2)
when _T_2420 :
connect remapVecData[2], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[2]
node _T_2421 = eq(UInt<5>(0h1b), remapindex_2)
when _T_2421 :
connect remapVecData[2], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[2]
node _T_2422 = eq(UInt<5>(0h1c), remapindex_2)
when _T_2422 :
connect remapVecData[2], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[2]
node _T_2423 = eq(UInt<5>(0h1d), remapindex_2)
when _T_2423 :
connect remapVecData[2], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[2]
node _T_2424 = eq(UInt<5>(0h1e), remapindex_2)
when _T_2424 :
connect remapVecData[2], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[2]
node _T_2425 = eq(UInt<5>(0h1f), remapindex_2)
when _T_2425 :
connect remapVecData[2], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[2]
node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index)
node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20))
node _T_2426 = eq(UInt<1>(0h0), remapindex_3)
when _T_2426 :
connect remapVecData[3], Queue64_UInt8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[3]
node _T_2427 = eq(UInt<1>(0h1), remapindex_3)
when _T_2427 :
connect remapVecData[3], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[3]
node _T_2428 = eq(UInt<2>(0h2), remapindex_3)
when _T_2428 :
connect remapVecData[3], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[3]
node _T_2429 = eq(UInt<2>(0h3), remapindex_3)
when _T_2429 :
connect remapVecData[3], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[3]
node _T_2430 = eq(UInt<3>(0h4), remapindex_3)
when _T_2430 :
connect remapVecData[3], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[3]
node _T_2431 = eq(UInt<3>(0h5), remapindex_3)
when _T_2431 :
connect remapVecData[3], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[3]
node _T_2432 = eq(UInt<3>(0h6), remapindex_3)
when _T_2432 :
connect remapVecData[3], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[3]
node _T_2433 = eq(UInt<3>(0h7), remapindex_3)
when _T_2433 :
connect remapVecData[3], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[3]
node _T_2434 = eq(UInt<4>(0h8), remapindex_3)
when _T_2434 :
connect remapVecData[3], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[3]
node _T_2435 = eq(UInt<4>(0h9), remapindex_3)
when _T_2435 :
connect remapVecData[3], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[3]
node _T_2436 = eq(UInt<4>(0ha), remapindex_3)
when _T_2436 :
connect remapVecData[3], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[3]
node _T_2437 = eq(UInt<4>(0hb), remapindex_3)
when _T_2437 :
connect remapVecData[3], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[3]
node _T_2438 = eq(UInt<4>(0hc), remapindex_3)
when _T_2438 :
connect remapVecData[3], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[3]
node _T_2439 = eq(UInt<4>(0hd), remapindex_3)
when _T_2439 :
connect remapVecData[3], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[3]
node _T_2440 = eq(UInt<4>(0he), remapindex_3)
when _T_2440 :
connect remapVecData[3], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[3]
node _T_2441 = eq(UInt<4>(0hf), remapindex_3)
when _T_2441 :
connect remapVecData[3], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[3]
node _T_2442 = eq(UInt<5>(0h10), remapindex_3)
when _T_2442 :
connect remapVecData[3], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[3]
node _T_2443 = eq(UInt<5>(0h11), remapindex_3)
when _T_2443 :
connect remapVecData[3], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[3]
node _T_2444 = eq(UInt<5>(0h12), remapindex_3)
when _T_2444 :
connect remapVecData[3], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[3]
node _T_2445 = eq(UInt<5>(0h13), remapindex_3)
when _T_2445 :
connect remapVecData[3], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[3]
node _T_2446 = eq(UInt<5>(0h14), remapindex_3)
when _T_2446 :
connect remapVecData[3], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[3]
node _T_2447 = eq(UInt<5>(0h15), remapindex_3)
when _T_2447 :
connect remapVecData[3], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[3]
node _T_2448 = eq(UInt<5>(0h16), remapindex_3)
when _T_2448 :
connect remapVecData[3], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[3]
node _T_2449 = eq(UInt<5>(0h17), remapindex_3)
when _T_2449 :
connect remapVecData[3], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[3]
node _T_2450 = eq(UInt<5>(0h18), remapindex_3)
when _T_2450 :
connect remapVecData[3], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[3]
node _T_2451 = eq(UInt<5>(0h19), remapindex_3)
when _T_2451 :
connect remapVecData[3], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[3]
node _T_2452 = eq(UInt<5>(0h1a), remapindex_3)
when _T_2452 :
connect remapVecData[3], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[3]
node _T_2453 = eq(UInt<5>(0h1b), remapindex_3)
when _T_2453 :
connect remapVecData[3], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[3]
node _T_2454 = eq(UInt<5>(0h1c), remapindex_3)
when _T_2454 :
connect remapVecData[3], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[3]
node _T_2455 = eq(UInt<5>(0h1d), remapindex_3)
when _T_2455 :
connect remapVecData[3], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[3]
node _T_2456 = eq(UInt<5>(0h1e), remapindex_3)
when _T_2456 :
connect remapVecData[3], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[3]
node _T_2457 = eq(UInt<5>(0h1f), remapindex_3)
when _T_2457 :
connect remapVecData[3], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[3]
node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index)
node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20))
node _T_2458 = eq(UInt<1>(0h0), remapindex_4)
when _T_2458 :
connect remapVecData[4], Queue64_UInt8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[4]
node _T_2459 = eq(UInt<1>(0h1), remapindex_4)
when _T_2459 :
connect remapVecData[4], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[4]
node _T_2460 = eq(UInt<2>(0h2), remapindex_4)
when _T_2460 :
connect remapVecData[4], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[4]
node _T_2461 = eq(UInt<2>(0h3), remapindex_4)
when _T_2461 :
connect remapVecData[4], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[4]
node _T_2462 = eq(UInt<3>(0h4), remapindex_4)
when _T_2462 :
connect remapVecData[4], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[4]
node _T_2463 = eq(UInt<3>(0h5), remapindex_4)
when _T_2463 :
connect remapVecData[4], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[4]
node _T_2464 = eq(UInt<3>(0h6), remapindex_4)
when _T_2464 :
connect remapVecData[4], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[4]
node _T_2465 = eq(UInt<3>(0h7), remapindex_4)
when _T_2465 :
connect remapVecData[4], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[4]
node _T_2466 = eq(UInt<4>(0h8), remapindex_4)
when _T_2466 :
connect remapVecData[4], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[4]
node _T_2467 = eq(UInt<4>(0h9), remapindex_4)
when _T_2467 :
connect remapVecData[4], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[4]
node _T_2468 = eq(UInt<4>(0ha), remapindex_4)
when _T_2468 :
connect remapVecData[4], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[4]
node _T_2469 = eq(UInt<4>(0hb), remapindex_4)
when _T_2469 :
connect remapVecData[4], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[4]
node _T_2470 = eq(UInt<4>(0hc), remapindex_4)
when _T_2470 :
connect remapVecData[4], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[4]
node _T_2471 = eq(UInt<4>(0hd), remapindex_4)
when _T_2471 :
connect remapVecData[4], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[4]
node _T_2472 = eq(UInt<4>(0he), remapindex_4)
when _T_2472 :
connect remapVecData[4], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[4]
node _T_2473 = eq(UInt<4>(0hf), remapindex_4)
when _T_2473 :
connect remapVecData[4], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[4]
node _T_2474 = eq(UInt<5>(0h10), remapindex_4)
when _T_2474 :
connect remapVecData[4], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[4]
node _T_2475 = eq(UInt<5>(0h11), remapindex_4)
when _T_2475 :
connect remapVecData[4], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[4]
node _T_2476 = eq(UInt<5>(0h12), remapindex_4)
when _T_2476 :
connect remapVecData[4], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[4]
node _T_2477 = eq(UInt<5>(0h13), remapindex_4)
when _T_2477 :
connect remapVecData[4], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[4]
node _T_2478 = eq(UInt<5>(0h14), remapindex_4)
when _T_2478 :
connect remapVecData[4], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[4]
node _T_2479 = eq(UInt<5>(0h15), remapindex_4)
when _T_2479 :
connect remapVecData[4], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[4]
node _T_2480 = eq(UInt<5>(0h16), remapindex_4)
when _T_2480 :
connect remapVecData[4], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[4]
node _T_2481 = eq(UInt<5>(0h17), remapindex_4)
when _T_2481 :
connect remapVecData[4], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[4]
node _T_2482 = eq(UInt<5>(0h18), remapindex_4)
when _T_2482 :
connect remapVecData[4], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[4]
node _T_2483 = eq(UInt<5>(0h19), remapindex_4)
when _T_2483 :
connect remapVecData[4], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[4]
node _T_2484 = eq(UInt<5>(0h1a), remapindex_4)
when _T_2484 :
connect remapVecData[4], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[4]
node _T_2485 = eq(UInt<5>(0h1b), remapindex_4)
when _T_2485 :
connect remapVecData[4], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[4]
node _T_2486 = eq(UInt<5>(0h1c), remapindex_4)
when _T_2486 :
connect remapVecData[4], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[4]
node _T_2487 = eq(UInt<5>(0h1d), remapindex_4)
when _T_2487 :
connect remapVecData[4], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[4]
node _T_2488 = eq(UInt<5>(0h1e), remapindex_4)
when _T_2488 :
connect remapVecData[4], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[4]
node _T_2489 = eq(UInt<5>(0h1f), remapindex_4)
when _T_2489 :
connect remapVecData[4], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[4]
node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index)
node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20))
node _T_2490 = eq(UInt<1>(0h0), remapindex_5)
when _T_2490 :
connect remapVecData[5], Queue64_UInt8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[5]
node _T_2491 = eq(UInt<1>(0h1), remapindex_5)
when _T_2491 :
connect remapVecData[5], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[5]
node _T_2492 = eq(UInt<2>(0h2), remapindex_5)
when _T_2492 :
connect remapVecData[5], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[5]
node _T_2493 = eq(UInt<2>(0h3), remapindex_5)
when _T_2493 :
connect remapVecData[5], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[5]
node _T_2494 = eq(UInt<3>(0h4), remapindex_5)
when _T_2494 :
connect remapVecData[5], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[5]
node _T_2495 = eq(UInt<3>(0h5), remapindex_5)
when _T_2495 :
connect remapVecData[5], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[5]
node _T_2496 = eq(UInt<3>(0h6), remapindex_5)
when _T_2496 :
connect remapVecData[5], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[5]
node _T_2497 = eq(UInt<3>(0h7), remapindex_5)
when _T_2497 :
connect remapVecData[5], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[5]
node _T_2498 = eq(UInt<4>(0h8), remapindex_5)
when _T_2498 :
connect remapVecData[5], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[5]
node _T_2499 = eq(UInt<4>(0h9), remapindex_5)
when _T_2499 :
connect remapVecData[5], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[5]
node _T_2500 = eq(UInt<4>(0ha), remapindex_5)
when _T_2500 :
connect remapVecData[5], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[5]
node _T_2501 = eq(UInt<4>(0hb), remapindex_5)
when _T_2501 :
connect remapVecData[5], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[5]
node _T_2502 = eq(UInt<4>(0hc), remapindex_5)
when _T_2502 :
connect remapVecData[5], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[5]
node _T_2503 = eq(UInt<4>(0hd), remapindex_5)
when _T_2503 :
connect remapVecData[5], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[5]
node _T_2504 = eq(UInt<4>(0he), remapindex_5)
when _T_2504 :
connect remapVecData[5], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[5]
node _T_2505 = eq(UInt<4>(0hf), remapindex_5)
when _T_2505 :
connect remapVecData[5], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[5]
node _T_2506 = eq(UInt<5>(0h10), remapindex_5)
when _T_2506 :
connect remapVecData[5], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[5]
node _T_2507 = eq(UInt<5>(0h11), remapindex_5)
when _T_2507 :
connect remapVecData[5], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[5]
node _T_2508 = eq(UInt<5>(0h12), remapindex_5)
when _T_2508 :
connect remapVecData[5], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[5]
node _T_2509 = eq(UInt<5>(0h13), remapindex_5)
when _T_2509 :
connect remapVecData[5], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[5]
node _T_2510 = eq(UInt<5>(0h14), remapindex_5)
when _T_2510 :
connect remapVecData[5], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[5]
node _T_2511 = eq(UInt<5>(0h15), remapindex_5)
when _T_2511 :
connect remapVecData[5], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[5]
node _T_2512 = eq(UInt<5>(0h16), remapindex_5)
when _T_2512 :
connect remapVecData[5], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[5]
node _T_2513 = eq(UInt<5>(0h17), remapindex_5)
when _T_2513 :
connect remapVecData[5], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[5]
node _T_2514 = eq(UInt<5>(0h18), remapindex_5)
when _T_2514 :
connect remapVecData[5], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[5]
node _T_2515 = eq(UInt<5>(0h19), remapindex_5)
when _T_2515 :
connect remapVecData[5], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[5]
node _T_2516 = eq(UInt<5>(0h1a), remapindex_5)
when _T_2516 :
connect remapVecData[5], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[5]
node _T_2517 = eq(UInt<5>(0h1b), remapindex_5)
when _T_2517 :
connect remapVecData[5], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[5]
node _T_2518 = eq(UInt<5>(0h1c), remapindex_5)
when _T_2518 :
connect remapVecData[5], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[5]
node _T_2519 = eq(UInt<5>(0h1d), remapindex_5)
when _T_2519 :
connect remapVecData[5], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[5]
node _T_2520 = eq(UInt<5>(0h1e), remapindex_5)
when _T_2520 :
connect remapVecData[5], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[5]
node _T_2521 = eq(UInt<5>(0h1f), remapindex_5)
when _T_2521 :
connect remapVecData[5], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[5]
node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index)
node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20))
node _T_2522 = eq(UInt<1>(0h0), remapindex_6)
when _T_2522 :
connect remapVecData[6], Queue64_UInt8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[6]
node _T_2523 = eq(UInt<1>(0h1), remapindex_6)
when _T_2523 :
connect remapVecData[6], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[6]
node _T_2524 = eq(UInt<2>(0h2), remapindex_6)
when _T_2524 :
connect remapVecData[6], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[6]
node _T_2525 = eq(UInt<2>(0h3), remapindex_6)
when _T_2525 :
connect remapVecData[6], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[6]
node _T_2526 = eq(UInt<3>(0h4), remapindex_6)
when _T_2526 :
connect remapVecData[6], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[6]
node _T_2527 = eq(UInt<3>(0h5), remapindex_6)
when _T_2527 :
connect remapVecData[6], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[6]
node _T_2528 = eq(UInt<3>(0h6), remapindex_6)
when _T_2528 :
connect remapVecData[6], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[6]
node _T_2529 = eq(UInt<3>(0h7), remapindex_6)
when _T_2529 :
connect remapVecData[6], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[6]
node _T_2530 = eq(UInt<4>(0h8), remapindex_6)
when _T_2530 :
connect remapVecData[6], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[6]
node _T_2531 = eq(UInt<4>(0h9), remapindex_6)
when _T_2531 :
connect remapVecData[6], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[6]
node _T_2532 = eq(UInt<4>(0ha), remapindex_6)
when _T_2532 :
connect remapVecData[6], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[6]
node _T_2533 = eq(UInt<4>(0hb), remapindex_6)
when _T_2533 :
connect remapVecData[6], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[6]
node _T_2534 = eq(UInt<4>(0hc), remapindex_6)
when _T_2534 :
connect remapVecData[6], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[6]
node _T_2535 = eq(UInt<4>(0hd), remapindex_6)
when _T_2535 :
connect remapVecData[6], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[6]
node _T_2536 = eq(UInt<4>(0he), remapindex_6)
when _T_2536 :
connect remapVecData[6], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[6]
node _T_2537 = eq(UInt<4>(0hf), remapindex_6)
when _T_2537 :
connect remapVecData[6], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[6]
node _T_2538 = eq(UInt<5>(0h10), remapindex_6)
when _T_2538 :
connect remapVecData[6], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[6]
node _T_2539 = eq(UInt<5>(0h11), remapindex_6)
when _T_2539 :
connect remapVecData[6], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[6]
node _T_2540 = eq(UInt<5>(0h12), remapindex_6)
when _T_2540 :
connect remapVecData[6], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[6]
node _T_2541 = eq(UInt<5>(0h13), remapindex_6)
when _T_2541 :
connect remapVecData[6], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[6]
node _T_2542 = eq(UInt<5>(0h14), remapindex_6)
when _T_2542 :
connect remapVecData[6], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[6]
node _T_2543 = eq(UInt<5>(0h15), remapindex_6)
when _T_2543 :
connect remapVecData[6], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[6]
node _T_2544 = eq(UInt<5>(0h16), remapindex_6)
when _T_2544 :
connect remapVecData[6], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[6]
node _T_2545 = eq(UInt<5>(0h17), remapindex_6)
when _T_2545 :
connect remapVecData[6], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[6]
node _T_2546 = eq(UInt<5>(0h18), remapindex_6)
when _T_2546 :
connect remapVecData[6], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[6]
node _T_2547 = eq(UInt<5>(0h19), remapindex_6)
when _T_2547 :
connect remapVecData[6], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[6]
node _T_2548 = eq(UInt<5>(0h1a), remapindex_6)
when _T_2548 :
connect remapVecData[6], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[6]
node _T_2549 = eq(UInt<5>(0h1b), remapindex_6)
when _T_2549 :
connect remapVecData[6], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[6]
node _T_2550 = eq(UInt<5>(0h1c), remapindex_6)
when _T_2550 :
connect remapVecData[6], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[6]
node _T_2551 = eq(UInt<5>(0h1d), remapindex_6)
when _T_2551 :
connect remapVecData[6], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[6]
node _T_2552 = eq(UInt<5>(0h1e), remapindex_6)
when _T_2552 :
connect remapVecData[6], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[6]
node _T_2553 = eq(UInt<5>(0h1f), remapindex_6)
when _T_2553 :
connect remapVecData[6], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[6]
node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index)
node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20))
node _T_2554 = eq(UInt<1>(0h0), remapindex_7)
when _T_2554 :
connect remapVecData[7], Queue64_UInt8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[7]
node _T_2555 = eq(UInt<1>(0h1), remapindex_7)
when _T_2555 :
connect remapVecData[7], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[7]
node _T_2556 = eq(UInt<2>(0h2), remapindex_7)
when _T_2556 :
connect remapVecData[7], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[7]
node _T_2557 = eq(UInt<2>(0h3), remapindex_7)
when _T_2557 :
connect remapVecData[7], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[7]
node _T_2558 = eq(UInt<3>(0h4), remapindex_7)
when _T_2558 :
connect remapVecData[7], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[7]
node _T_2559 = eq(UInt<3>(0h5), remapindex_7)
when _T_2559 :
connect remapVecData[7], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[7]
node _T_2560 = eq(UInt<3>(0h6), remapindex_7)
when _T_2560 :
connect remapVecData[7], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[7]
node _T_2561 = eq(UInt<3>(0h7), remapindex_7)
when _T_2561 :
connect remapVecData[7], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[7]
node _T_2562 = eq(UInt<4>(0h8), remapindex_7)
when _T_2562 :
connect remapVecData[7], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[7]
node _T_2563 = eq(UInt<4>(0h9), remapindex_7)
when _T_2563 :
connect remapVecData[7], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[7]
node _T_2564 = eq(UInt<4>(0ha), remapindex_7)
when _T_2564 :
connect remapVecData[7], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[7]
node _T_2565 = eq(UInt<4>(0hb), remapindex_7)
when _T_2565 :
connect remapVecData[7], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[7]
node _T_2566 = eq(UInt<4>(0hc), remapindex_7)
when _T_2566 :
connect remapVecData[7], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[7]
node _T_2567 = eq(UInt<4>(0hd), remapindex_7)
when _T_2567 :
connect remapVecData[7], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[7]
node _T_2568 = eq(UInt<4>(0he), remapindex_7)
when _T_2568 :
connect remapVecData[7], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[7]
node _T_2569 = eq(UInt<4>(0hf), remapindex_7)
when _T_2569 :
connect remapVecData[7], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[7]
node _T_2570 = eq(UInt<5>(0h10), remapindex_7)
when _T_2570 :
connect remapVecData[7], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[7]
node _T_2571 = eq(UInt<5>(0h11), remapindex_7)
when _T_2571 :
connect remapVecData[7], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[7]
node _T_2572 = eq(UInt<5>(0h12), remapindex_7)
when _T_2572 :
connect remapVecData[7], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[7]
node _T_2573 = eq(UInt<5>(0h13), remapindex_7)
when _T_2573 :
connect remapVecData[7], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[7]
node _T_2574 = eq(UInt<5>(0h14), remapindex_7)
when _T_2574 :
connect remapVecData[7], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[7]
node _T_2575 = eq(UInt<5>(0h15), remapindex_7)
when _T_2575 :
connect remapVecData[7], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[7]
node _T_2576 = eq(UInt<5>(0h16), remapindex_7)
when _T_2576 :
connect remapVecData[7], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[7]
node _T_2577 = eq(UInt<5>(0h17), remapindex_7)
when _T_2577 :
connect remapVecData[7], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[7]
node _T_2578 = eq(UInt<5>(0h18), remapindex_7)
when _T_2578 :
connect remapVecData[7], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[7]
node _T_2579 = eq(UInt<5>(0h19), remapindex_7)
when _T_2579 :
connect remapVecData[7], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[7]
node _T_2580 = eq(UInt<5>(0h1a), remapindex_7)
when _T_2580 :
connect remapVecData[7], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[7]
node _T_2581 = eq(UInt<5>(0h1b), remapindex_7)
when _T_2581 :
connect remapVecData[7], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[7]
node _T_2582 = eq(UInt<5>(0h1c), remapindex_7)
when _T_2582 :
connect remapVecData[7], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[7]
node _T_2583 = eq(UInt<5>(0h1d), remapindex_7)
when _T_2583 :
connect remapVecData[7], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[7]
node _T_2584 = eq(UInt<5>(0h1e), remapindex_7)
when _T_2584 :
connect remapVecData[7], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[7]
node _T_2585 = eq(UInt<5>(0h1f), remapindex_7)
when _T_2585 :
connect remapVecData[7], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[7]
node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index)
node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20))
node _T_2586 = eq(UInt<1>(0h0), remapindex_8)
when _T_2586 :
connect remapVecData[8], Queue64_UInt8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[8]
node _T_2587 = eq(UInt<1>(0h1), remapindex_8)
when _T_2587 :
connect remapVecData[8], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[8]
node _T_2588 = eq(UInt<2>(0h2), remapindex_8)
when _T_2588 :
connect remapVecData[8], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[8]
node _T_2589 = eq(UInt<2>(0h3), remapindex_8)
when _T_2589 :
connect remapVecData[8], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[8]
node _T_2590 = eq(UInt<3>(0h4), remapindex_8)
when _T_2590 :
connect remapVecData[8], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[8]
node _T_2591 = eq(UInt<3>(0h5), remapindex_8)
when _T_2591 :
connect remapVecData[8], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[8]
node _T_2592 = eq(UInt<3>(0h6), remapindex_8)
when _T_2592 :
connect remapVecData[8], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[8]
node _T_2593 = eq(UInt<3>(0h7), remapindex_8)
when _T_2593 :
connect remapVecData[8], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[8]
node _T_2594 = eq(UInt<4>(0h8), remapindex_8)
when _T_2594 :
connect remapVecData[8], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[8]
node _T_2595 = eq(UInt<4>(0h9), remapindex_8)
when _T_2595 :
connect remapVecData[8], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[8]
node _T_2596 = eq(UInt<4>(0ha), remapindex_8)
when _T_2596 :
connect remapVecData[8], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[8]
node _T_2597 = eq(UInt<4>(0hb), remapindex_8)
when _T_2597 :
connect remapVecData[8], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[8]
node _T_2598 = eq(UInt<4>(0hc), remapindex_8)
when _T_2598 :
connect remapVecData[8], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[8]
node _T_2599 = eq(UInt<4>(0hd), remapindex_8)
when _T_2599 :
connect remapVecData[8], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[8]
node _T_2600 = eq(UInt<4>(0he), remapindex_8)
when _T_2600 :
connect remapVecData[8], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[8]
node _T_2601 = eq(UInt<4>(0hf), remapindex_8)
when _T_2601 :
connect remapVecData[8], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[8]
node _T_2602 = eq(UInt<5>(0h10), remapindex_8)
when _T_2602 :
connect remapVecData[8], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[8]
node _T_2603 = eq(UInt<5>(0h11), remapindex_8)
when _T_2603 :
connect remapVecData[8], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[8]
node _T_2604 = eq(UInt<5>(0h12), remapindex_8)
when _T_2604 :
connect remapVecData[8], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[8]
node _T_2605 = eq(UInt<5>(0h13), remapindex_8)
when _T_2605 :
connect remapVecData[8], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[8]
node _T_2606 = eq(UInt<5>(0h14), remapindex_8)
when _T_2606 :
connect remapVecData[8], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[8]
node _T_2607 = eq(UInt<5>(0h15), remapindex_8)
when _T_2607 :
connect remapVecData[8], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[8]
node _T_2608 = eq(UInt<5>(0h16), remapindex_8)
when _T_2608 :
connect remapVecData[8], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[8]
node _T_2609 = eq(UInt<5>(0h17), remapindex_8)
when _T_2609 :
connect remapVecData[8], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[8]
node _T_2610 = eq(UInt<5>(0h18), remapindex_8)
when _T_2610 :
connect remapVecData[8], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[8]
node _T_2611 = eq(UInt<5>(0h19), remapindex_8)
when _T_2611 :
connect remapVecData[8], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[8]
node _T_2612 = eq(UInt<5>(0h1a), remapindex_8)
when _T_2612 :
connect remapVecData[8], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[8]
node _T_2613 = eq(UInt<5>(0h1b), remapindex_8)
when _T_2613 :
connect remapVecData[8], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[8]
node _T_2614 = eq(UInt<5>(0h1c), remapindex_8)
when _T_2614 :
connect remapVecData[8], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[8]
node _T_2615 = eq(UInt<5>(0h1d), remapindex_8)
when _T_2615 :
connect remapVecData[8], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[8]
node _T_2616 = eq(UInt<5>(0h1e), remapindex_8)
when _T_2616 :
connect remapVecData[8], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[8]
node _T_2617 = eq(UInt<5>(0h1f), remapindex_8)
when _T_2617 :
connect remapVecData[8], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[8]
node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index)
node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20))
node _T_2618 = eq(UInt<1>(0h0), remapindex_9)
when _T_2618 :
connect remapVecData[9], Queue64_UInt8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[9]
node _T_2619 = eq(UInt<1>(0h1), remapindex_9)
when _T_2619 :
connect remapVecData[9], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[9]
node _T_2620 = eq(UInt<2>(0h2), remapindex_9)
when _T_2620 :
connect remapVecData[9], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[9]
node _T_2621 = eq(UInt<2>(0h3), remapindex_9)
when _T_2621 :
connect remapVecData[9], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[9]
node _T_2622 = eq(UInt<3>(0h4), remapindex_9)
when _T_2622 :
connect remapVecData[9], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[9]
node _T_2623 = eq(UInt<3>(0h5), remapindex_9)
when _T_2623 :
connect remapVecData[9], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[9]
node _T_2624 = eq(UInt<3>(0h6), remapindex_9)
when _T_2624 :
connect remapVecData[9], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[9]
node _T_2625 = eq(UInt<3>(0h7), remapindex_9)
when _T_2625 :
connect remapVecData[9], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[9]
node _T_2626 = eq(UInt<4>(0h8), remapindex_9)
when _T_2626 :
connect remapVecData[9], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[9]
node _T_2627 = eq(UInt<4>(0h9), remapindex_9)
when _T_2627 :
connect remapVecData[9], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[9]
node _T_2628 = eq(UInt<4>(0ha), remapindex_9)
when _T_2628 :
connect remapVecData[9], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[9]
node _T_2629 = eq(UInt<4>(0hb), remapindex_9)
when _T_2629 :
connect remapVecData[9], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[9]
node _T_2630 = eq(UInt<4>(0hc), remapindex_9)
when _T_2630 :
connect remapVecData[9], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[9]
node _T_2631 = eq(UInt<4>(0hd), remapindex_9)
when _T_2631 :
connect remapVecData[9], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[9]
node _T_2632 = eq(UInt<4>(0he), remapindex_9)
when _T_2632 :
connect remapVecData[9], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[9]
node _T_2633 = eq(UInt<4>(0hf), remapindex_9)
when _T_2633 :
connect remapVecData[9], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[9]
node _T_2634 = eq(UInt<5>(0h10), remapindex_9)
when _T_2634 :
connect remapVecData[9], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[9]
node _T_2635 = eq(UInt<5>(0h11), remapindex_9)
when _T_2635 :
connect remapVecData[9], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[9]
node _T_2636 = eq(UInt<5>(0h12), remapindex_9)
when _T_2636 :
connect remapVecData[9], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[9]
node _T_2637 = eq(UInt<5>(0h13), remapindex_9)
when _T_2637 :
connect remapVecData[9], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[9]
node _T_2638 = eq(UInt<5>(0h14), remapindex_9)
when _T_2638 :
connect remapVecData[9], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[9]
node _T_2639 = eq(UInt<5>(0h15), remapindex_9)
when _T_2639 :
connect remapVecData[9], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[9]
node _T_2640 = eq(UInt<5>(0h16), remapindex_9)
when _T_2640 :
connect remapVecData[9], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[9]
node _T_2641 = eq(UInt<5>(0h17), remapindex_9)
when _T_2641 :
connect remapVecData[9], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[9]
node _T_2642 = eq(UInt<5>(0h18), remapindex_9)
when _T_2642 :
connect remapVecData[9], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[9]
node _T_2643 = eq(UInt<5>(0h19), remapindex_9)
when _T_2643 :
connect remapVecData[9], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[9]
node _T_2644 = eq(UInt<5>(0h1a), remapindex_9)
when _T_2644 :
connect remapVecData[9], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[9]
node _T_2645 = eq(UInt<5>(0h1b), remapindex_9)
when _T_2645 :
connect remapVecData[9], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[9]
node _T_2646 = eq(UInt<5>(0h1c), remapindex_9)
when _T_2646 :
connect remapVecData[9], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[9]
node _T_2647 = eq(UInt<5>(0h1d), remapindex_9)
when _T_2647 :
connect remapVecData[9], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[9]
node _T_2648 = eq(UInt<5>(0h1e), remapindex_9)
when _T_2648 :
connect remapVecData[9], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[9]
node _T_2649 = eq(UInt<5>(0h1f), remapindex_9)
when _T_2649 :
connect remapVecData[9], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[9]
node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index)
node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20))
node _T_2650 = eq(UInt<1>(0h0), remapindex_10)
when _T_2650 :
connect remapVecData[10], Queue64_UInt8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[10]
node _T_2651 = eq(UInt<1>(0h1), remapindex_10)
when _T_2651 :
connect remapVecData[10], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[10]
node _T_2652 = eq(UInt<2>(0h2), remapindex_10)
when _T_2652 :
connect remapVecData[10], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[10]
node _T_2653 = eq(UInt<2>(0h3), remapindex_10)
when _T_2653 :
connect remapVecData[10], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[10]
node _T_2654 = eq(UInt<3>(0h4), remapindex_10)
when _T_2654 :
connect remapVecData[10], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[10]
node _T_2655 = eq(UInt<3>(0h5), remapindex_10)
when _T_2655 :
connect remapVecData[10], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[10]
node _T_2656 = eq(UInt<3>(0h6), remapindex_10)
when _T_2656 :
connect remapVecData[10], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[10]
node _T_2657 = eq(UInt<3>(0h7), remapindex_10)
when _T_2657 :
connect remapVecData[10], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[10]
node _T_2658 = eq(UInt<4>(0h8), remapindex_10)
when _T_2658 :
connect remapVecData[10], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[10]
node _T_2659 = eq(UInt<4>(0h9), remapindex_10)
when _T_2659 :
connect remapVecData[10], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[10]
node _T_2660 = eq(UInt<4>(0ha), remapindex_10)
when _T_2660 :
connect remapVecData[10], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[10]
node _T_2661 = eq(UInt<4>(0hb), remapindex_10)
when _T_2661 :
connect remapVecData[10], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[10]
node _T_2662 = eq(UInt<4>(0hc), remapindex_10)
when _T_2662 :
connect remapVecData[10], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[10]
node _T_2663 = eq(UInt<4>(0hd), remapindex_10)
when _T_2663 :
connect remapVecData[10], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[10]
node _T_2664 = eq(UInt<4>(0he), remapindex_10)
when _T_2664 :
connect remapVecData[10], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[10]
node _T_2665 = eq(UInt<4>(0hf), remapindex_10)
when _T_2665 :
connect remapVecData[10], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[10]
node _T_2666 = eq(UInt<5>(0h10), remapindex_10)
when _T_2666 :
connect remapVecData[10], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[10]
node _T_2667 = eq(UInt<5>(0h11), remapindex_10)
when _T_2667 :
connect remapVecData[10], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[10]
node _T_2668 = eq(UInt<5>(0h12), remapindex_10)
when _T_2668 :
connect remapVecData[10], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[10]
node _T_2669 = eq(UInt<5>(0h13), remapindex_10)
when _T_2669 :
connect remapVecData[10], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[10]
node _T_2670 = eq(UInt<5>(0h14), remapindex_10)
when _T_2670 :
connect remapVecData[10], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[10]
node _T_2671 = eq(UInt<5>(0h15), remapindex_10)
when _T_2671 :
connect remapVecData[10], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[10]
node _T_2672 = eq(UInt<5>(0h16), remapindex_10)
when _T_2672 :
connect remapVecData[10], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[10]
node _T_2673 = eq(UInt<5>(0h17), remapindex_10)
when _T_2673 :
connect remapVecData[10], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[10]
node _T_2674 = eq(UInt<5>(0h18), remapindex_10)
when _T_2674 :
connect remapVecData[10], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[10]
node _T_2675 = eq(UInt<5>(0h19), remapindex_10)
when _T_2675 :
connect remapVecData[10], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[10]
node _T_2676 = eq(UInt<5>(0h1a), remapindex_10)
when _T_2676 :
connect remapVecData[10], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[10]
node _T_2677 = eq(UInt<5>(0h1b), remapindex_10)
when _T_2677 :
connect remapVecData[10], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[10]
node _T_2678 = eq(UInt<5>(0h1c), remapindex_10)
when _T_2678 :
connect remapVecData[10], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[10]
node _T_2679 = eq(UInt<5>(0h1d), remapindex_10)
when _T_2679 :
connect remapVecData[10], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[10]
node _T_2680 = eq(UInt<5>(0h1e), remapindex_10)
when _T_2680 :
connect remapVecData[10], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[10]
node _T_2681 = eq(UInt<5>(0h1f), remapindex_10)
when _T_2681 :
connect remapVecData[10], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[10]
node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index)
node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20))
node _T_2682 = eq(UInt<1>(0h0), remapindex_11)
when _T_2682 :
connect remapVecData[11], Queue64_UInt8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[11]
node _T_2683 = eq(UInt<1>(0h1), remapindex_11)
when _T_2683 :
connect remapVecData[11], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[11]
node _T_2684 = eq(UInt<2>(0h2), remapindex_11)
when _T_2684 :
connect remapVecData[11], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[11]
node _T_2685 = eq(UInt<2>(0h3), remapindex_11)
when _T_2685 :
connect remapVecData[11], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[11]
node _T_2686 = eq(UInt<3>(0h4), remapindex_11)
when _T_2686 :
connect remapVecData[11], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[11]
node _T_2687 = eq(UInt<3>(0h5), remapindex_11)
when _T_2687 :
connect remapVecData[11], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[11]
node _T_2688 = eq(UInt<3>(0h6), remapindex_11)
when _T_2688 :
connect remapVecData[11], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[11]
node _T_2689 = eq(UInt<3>(0h7), remapindex_11)
when _T_2689 :
connect remapVecData[11], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[11]
node _T_2690 = eq(UInt<4>(0h8), remapindex_11)
when _T_2690 :
connect remapVecData[11], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[11]
node _T_2691 = eq(UInt<4>(0h9), remapindex_11)
when _T_2691 :
connect remapVecData[11], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[11]
node _T_2692 = eq(UInt<4>(0ha), remapindex_11)
when _T_2692 :
connect remapVecData[11], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[11]
node _T_2693 = eq(UInt<4>(0hb), remapindex_11)
when _T_2693 :
connect remapVecData[11], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[11]
node _T_2694 = eq(UInt<4>(0hc), remapindex_11)
when _T_2694 :
connect remapVecData[11], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[11]
node _T_2695 = eq(UInt<4>(0hd), remapindex_11)
when _T_2695 :
connect remapVecData[11], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[11]
node _T_2696 = eq(UInt<4>(0he), remapindex_11)
when _T_2696 :
connect remapVecData[11], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[11]
node _T_2697 = eq(UInt<4>(0hf), remapindex_11)
when _T_2697 :
connect remapVecData[11], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[11]
node _T_2698 = eq(UInt<5>(0h10), remapindex_11)
when _T_2698 :
connect remapVecData[11], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[11]
node _T_2699 = eq(UInt<5>(0h11), remapindex_11)
when _T_2699 :
connect remapVecData[11], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[11]
node _T_2700 = eq(UInt<5>(0h12), remapindex_11)
when _T_2700 :
connect remapVecData[11], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[11]
node _T_2701 = eq(UInt<5>(0h13), remapindex_11)
when _T_2701 :
connect remapVecData[11], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[11]
node _T_2702 = eq(UInt<5>(0h14), remapindex_11)
when _T_2702 :
connect remapVecData[11], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[11]
node _T_2703 = eq(UInt<5>(0h15), remapindex_11)
when _T_2703 :
connect remapVecData[11], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[11]
node _T_2704 = eq(UInt<5>(0h16), remapindex_11)
when _T_2704 :
connect remapVecData[11], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[11]
node _T_2705 = eq(UInt<5>(0h17), remapindex_11)
when _T_2705 :
connect remapVecData[11], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[11]
node _T_2706 = eq(UInt<5>(0h18), remapindex_11)
when _T_2706 :
connect remapVecData[11], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[11]
node _T_2707 = eq(UInt<5>(0h19), remapindex_11)
when _T_2707 :
connect remapVecData[11], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[11]
node _T_2708 = eq(UInt<5>(0h1a), remapindex_11)
when _T_2708 :
connect remapVecData[11], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[11]
node _T_2709 = eq(UInt<5>(0h1b), remapindex_11)
when _T_2709 :
connect remapVecData[11], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[11]
node _T_2710 = eq(UInt<5>(0h1c), remapindex_11)
when _T_2710 :
connect remapVecData[11], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[11]
node _T_2711 = eq(UInt<5>(0h1d), remapindex_11)
when _T_2711 :
connect remapVecData[11], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[11]
node _T_2712 = eq(UInt<5>(0h1e), remapindex_11)
when _T_2712 :
connect remapVecData[11], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[11]
node _T_2713 = eq(UInt<5>(0h1f), remapindex_11)
when _T_2713 :
connect remapVecData[11], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[11]
node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index)
node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20))
node _T_2714 = eq(UInt<1>(0h0), remapindex_12)
when _T_2714 :
connect remapVecData[12], Queue64_UInt8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[12]
node _T_2715 = eq(UInt<1>(0h1), remapindex_12)
when _T_2715 :
connect remapVecData[12], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[12]
node _T_2716 = eq(UInt<2>(0h2), remapindex_12)
when _T_2716 :
connect remapVecData[12], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[12]
node _T_2717 = eq(UInt<2>(0h3), remapindex_12)
when _T_2717 :
connect remapVecData[12], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[12]
node _T_2718 = eq(UInt<3>(0h4), remapindex_12)
when _T_2718 :
connect remapVecData[12], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[12]
node _T_2719 = eq(UInt<3>(0h5), remapindex_12)
when _T_2719 :
connect remapVecData[12], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[12]
node _T_2720 = eq(UInt<3>(0h6), remapindex_12)
when _T_2720 :
connect remapVecData[12], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[12]
node _T_2721 = eq(UInt<3>(0h7), remapindex_12)
when _T_2721 :
connect remapVecData[12], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[12]
node _T_2722 = eq(UInt<4>(0h8), remapindex_12)
when _T_2722 :
connect remapVecData[12], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[12]
node _T_2723 = eq(UInt<4>(0h9), remapindex_12)
when _T_2723 :
connect remapVecData[12], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[12]
node _T_2724 = eq(UInt<4>(0ha), remapindex_12)
when _T_2724 :
connect remapVecData[12], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[12]
node _T_2725 = eq(UInt<4>(0hb), remapindex_12)
when _T_2725 :
connect remapVecData[12], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[12]
node _T_2726 = eq(UInt<4>(0hc), remapindex_12)
when _T_2726 :
connect remapVecData[12], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[12]
node _T_2727 = eq(UInt<4>(0hd), remapindex_12)
when _T_2727 :
connect remapVecData[12], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[12]
node _T_2728 = eq(UInt<4>(0he), remapindex_12)
when _T_2728 :
connect remapVecData[12], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[12]
node _T_2729 = eq(UInt<4>(0hf), remapindex_12)
when _T_2729 :
connect remapVecData[12], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[12]
node _T_2730 = eq(UInt<5>(0h10), remapindex_12)
when _T_2730 :
connect remapVecData[12], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[12]
node _T_2731 = eq(UInt<5>(0h11), remapindex_12)
when _T_2731 :
connect remapVecData[12], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[12]
node _T_2732 = eq(UInt<5>(0h12), remapindex_12)
when _T_2732 :
connect remapVecData[12], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[12]
node _T_2733 = eq(UInt<5>(0h13), remapindex_12)
when _T_2733 :
connect remapVecData[12], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[12]
node _T_2734 = eq(UInt<5>(0h14), remapindex_12)
when _T_2734 :
connect remapVecData[12], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[12]
node _T_2735 = eq(UInt<5>(0h15), remapindex_12)
when _T_2735 :
connect remapVecData[12], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[12]
node _T_2736 = eq(UInt<5>(0h16), remapindex_12)
when _T_2736 :
connect remapVecData[12], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[12]
node _T_2737 = eq(UInt<5>(0h17), remapindex_12)
when _T_2737 :
connect remapVecData[12], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[12]
node _T_2738 = eq(UInt<5>(0h18), remapindex_12)
when _T_2738 :
connect remapVecData[12], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[12]
node _T_2739 = eq(UInt<5>(0h19), remapindex_12)
when _T_2739 :
connect remapVecData[12], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[12]
node _T_2740 = eq(UInt<5>(0h1a), remapindex_12)
when _T_2740 :
connect remapVecData[12], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[12]
node _T_2741 = eq(UInt<5>(0h1b), remapindex_12)
when _T_2741 :
connect remapVecData[12], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[12]
node _T_2742 = eq(UInt<5>(0h1c), remapindex_12)
when _T_2742 :
connect remapVecData[12], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[12]
node _T_2743 = eq(UInt<5>(0h1d), remapindex_12)
when _T_2743 :
connect remapVecData[12], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[12]
node _T_2744 = eq(UInt<5>(0h1e), remapindex_12)
when _T_2744 :
connect remapVecData[12], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[12]
node _T_2745 = eq(UInt<5>(0h1f), remapindex_12)
when _T_2745 :
connect remapVecData[12], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[12]
node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index)
node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20))
node _T_2746 = eq(UInt<1>(0h0), remapindex_13)
when _T_2746 :
connect remapVecData[13], Queue64_UInt8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[13]
node _T_2747 = eq(UInt<1>(0h1), remapindex_13)
when _T_2747 :
connect remapVecData[13], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[13]
node _T_2748 = eq(UInt<2>(0h2), remapindex_13)
when _T_2748 :
connect remapVecData[13], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[13]
node _T_2749 = eq(UInt<2>(0h3), remapindex_13)
when _T_2749 :
connect remapVecData[13], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[13]
node _T_2750 = eq(UInt<3>(0h4), remapindex_13)
when _T_2750 :
connect remapVecData[13], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[13]
node _T_2751 = eq(UInt<3>(0h5), remapindex_13)
when _T_2751 :
connect remapVecData[13], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[13]
node _T_2752 = eq(UInt<3>(0h6), remapindex_13)
when _T_2752 :
connect remapVecData[13], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[13]
node _T_2753 = eq(UInt<3>(0h7), remapindex_13)
when _T_2753 :
connect remapVecData[13], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[13]
node _T_2754 = eq(UInt<4>(0h8), remapindex_13)
when _T_2754 :
connect remapVecData[13], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[13]
node _T_2755 = eq(UInt<4>(0h9), remapindex_13)
when _T_2755 :
connect remapVecData[13], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[13]
node _T_2756 = eq(UInt<4>(0ha), remapindex_13)
when _T_2756 :
connect remapVecData[13], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[13]
node _T_2757 = eq(UInt<4>(0hb), remapindex_13)
when _T_2757 :
connect remapVecData[13], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[13]
node _T_2758 = eq(UInt<4>(0hc), remapindex_13)
when _T_2758 :
connect remapVecData[13], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[13]
node _T_2759 = eq(UInt<4>(0hd), remapindex_13)
when _T_2759 :
connect remapVecData[13], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[13]
node _T_2760 = eq(UInt<4>(0he), remapindex_13)
when _T_2760 :
connect remapVecData[13], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[13]
node _T_2761 = eq(UInt<4>(0hf), remapindex_13)
when _T_2761 :
connect remapVecData[13], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[13]
node _T_2762 = eq(UInt<5>(0h10), remapindex_13)
when _T_2762 :
connect remapVecData[13], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[13]
node _T_2763 = eq(UInt<5>(0h11), remapindex_13)
when _T_2763 :
connect remapVecData[13], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[13]
node _T_2764 = eq(UInt<5>(0h12), remapindex_13)
when _T_2764 :
connect remapVecData[13], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[13]
node _T_2765 = eq(UInt<5>(0h13), remapindex_13)
when _T_2765 :
connect remapVecData[13], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[13]
node _T_2766 = eq(UInt<5>(0h14), remapindex_13)
when _T_2766 :
connect remapVecData[13], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[13]
node _T_2767 = eq(UInt<5>(0h15), remapindex_13)
when _T_2767 :
connect remapVecData[13], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[13]
node _T_2768 = eq(UInt<5>(0h16), remapindex_13)
when _T_2768 :
connect remapVecData[13], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[13]
node _T_2769 = eq(UInt<5>(0h17), remapindex_13)
when _T_2769 :
connect remapVecData[13], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[13]
node _T_2770 = eq(UInt<5>(0h18), remapindex_13)
when _T_2770 :
connect remapVecData[13], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[13]
node _T_2771 = eq(UInt<5>(0h19), remapindex_13)
when _T_2771 :
connect remapVecData[13], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[13]
node _T_2772 = eq(UInt<5>(0h1a), remapindex_13)
when _T_2772 :
connect remapVecData[13], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[13]
node _T_2773 = eq(UInt<5>(0h1b), remapindex_13)
when _T_2773 :
connect remapVecData[13], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[13]
node _T_2774 = eq(UInt<5>(0h1c), remapindex_13)
when _T_2774 :
connect remapVecData[13], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[13]
node _T_2775 = eq(UInt<5>(0h1d), remapindex_13)
when _T_2775 :
connect remapVecData[13], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[13]
node _T_2776 = eq(UInt<5>(0h1e), remapindex_13)
when _T_2776 :
connect remapVecData[13], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[13]
node _T_2777 = eq(UInt<5>(0h1f), remapindex_13)
when _T_2777 :
connect remapVecData[13], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[13]
node _remapindex_T_14 = add(UInt<4>(0he), read_start_index)
node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20))
node _T_2778 = eq(UInt<1>(0h0), remapindex_14)
when _T_2778 :
connect remapVecData[14], Queue64_UInt8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[14]
node _T_2779 = eq(UInt<1>(0h1), remapindex_14)
when _T_2779 :
connect remapVecData[14], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[14]
node _T_2780 = eq(UInt<2>(0h2), remapindex_14)
when _T_2780 :
connect remapVecData[14], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[14]
node _T_2781 = eq(UInt<2>(0h3), remapindex_14)
when _T_2781 :
connect remapVecData[14], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[14]
node _T_2782 = eq(UInt<3>(0h4), remapindex_14)
when _T_2782 :
connect remapVecData[14], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[14]
node _T_2783 = eq(UInt<3>(0h5), remapindex_14)
when _T_2783 :
connect remapVecData[14], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[14]
node _T_2784 = eq(UInt<3>(0h6), remapindex_14)
when _T_2784 :
connect remapVecData[14], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[14]
node _T_2785 = eq(UInt<3>(0h7), remapindex_14)
when _T_2785 :
connect remapVecData[14], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[14]
node _T_2786 = eq(UInt<4>(0h8), remapindex_14)
when _T_2786 :
connect remapVecData[14], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[14]
node _T_2787 = eq(UInt<4>(0h9), remapindex_14)
when _T_2787 :
connect remapVecData[14], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[14]
node _T_2788 = eq(UInt<4>(0ha), remapindex_14)
when _T_2788 :
connect remapVecData[14], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[14]
node _T_2789 = eq(UInt<4>(0hb), remapindex_14)
when _T_2789 :
connect remapVecData[14], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[14]
node _T_2790 = eq(UInt<4>(0hc), remapindex_14)
when _T_2790 :
connect remapVecData[14], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[14]
node _T_2791 = eq(UInt<4>(0hd), remapindex_14)
when _T_2791 :
connect remapVecData[14], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[14]
node _T_2792 = eq(UInt<4>(0he), remapindex_14)
when _T_2792 :
connect remapVecData[14], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[14]
node _T_2793 = eq(UInt<4>(0hf), remapindex_14)
when _T_2793 :
connect remapVecData[14], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[14]
node _T_2794 = eq(UInt<5>(0h10), remapindex_14)
when _T_2794 :
connect remapVecData[14], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[14]
node _T_2795 = eq(UInt<5>(0h11), remapindex_14)
when _T_2795 :
connect remapVecData[14], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[14]
node _T_2796 = eq(UInt<5>(0h12), remapindex_14)
when _T_2796 :
connect remapVecData[14], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[14]
node _T_2797 = eq(UInt<5>(0h13), remapindex_14)
when _T_2797 :
connect remapVecData[14], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[14]
node _T_2798 = eq(UInt<5>(0h14), remapindex_14)
when _T_2798 :
connect remapVecData[14], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[14]
node _T_2799 = eq(UInt<5>(0h15), remapindex_14)
when _T_2799 :
connect remapVecData[14], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[14]
node _T_2800 = eq(UInt<5>(0h16), remapindex_14)
when _T_2800 :
connect remapVecData[14], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[14]
node _T_2801 = eq(UInt<5>(0h17), remapindex_14)
when _T_2801 :
connect remapVecData[14], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[14]
node _T_2802 = eq(UInt<5>(0h18), remapindex_14)
when _T_2802 :
connect remapVecData[14], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[14]
node _T_2803 = eq(UInt<5>(0h19), remapindex_14)
when _T_2803 :
connect remapVecData[14], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[14]
node _T_2804 = eq(UInt<5>(0h1a), remapindex_14)
when _T_2804 :
connect remapVecData[14], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[14]
node _T_2805 = eq(UInt<5>(0h1b), remapindex_14)
when _T_2805 :
connect remapVecData[14], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[14]
node _T_2806 = eq(UInt<5>(0h1c), remapindex_14)
when _T_2806 :
connect remapVecData[14], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[14]
node _T_2807 = eq(UInt<5>(0h1d), remapindex_14)
when _T_2807 :
connect remapVecData[14], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[14]
node _T_2808 = eq(UInt<5>(0h1e), remapindex_14)
when _T_2808 :
connect remapVecData[14], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[14]
node _T_2809 = eq(UInt<5>(0h1f), remapindex_14)
when _T_2809 :
connect remapVecData[14], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[14]
node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index)
node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20))
node _T_2810 = eq(UInt<1>(0h0), remapindex_15)
when _T_2810 :
connect remapVecData[15], Queue64_UInt8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[15]
node _T_2811 = eq(UInt<1>(0h1), remapindex_15)
when _T_2811 :
connect remapVecData[15], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[15]
node _T_2812 = eq(UInt<2>(0h2), remapindex_15)
when _T_2812 :
connect remapVecData[15], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[15]
node _T_2813 = eq(UInt<2>(0h3), remapindex_15)
when _T_2813 :
connect remapVecData[15], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[15]
node _T_2814 = eq(UInt<3>(0h4), remapindex_15)
when _T_2814 :
connect remapVecData[15], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[15]
node _T_2815 = eq(UInt<3>(0h5), remapindex_15)
when _T_2815 :
connect remapVecData[15], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[15]
node _T_2816 = eq(UInt<3>(0h6), remapindex_15)
when _T_2816 :
connect remapVecData[15], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[15]
node _T_2817 = eq(UInt<3>(0h7), remapindex_15)
when _T_2817 :
connect remapVecData[15], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[15]
node _T_2818 = eq(UInt<4>(0h8), remapindex_15)
when _T_2818 :
connect remapVecData[15], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[15]
node _T_2819 = eq(UInt<4>(0h9), remapindex_15)
when _T_2819 :
connect remapVecData[15], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[15]
node _T_2820 = eq(UInt<4>(0ha), remapindex_15)
when _T_2820 :
connect remapVecData[15], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[15]
node _T_2821 = eq(UInt<4>(0hb), remapindex_15)
when _T_2821 :
connect remapVecData[15], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[15]
node _T_2822 = eq(UInt<4>(0hc), remapindex_15)
when _T_2822 :
connect remapVecData[15], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[15]
node _T_2823 = eq(UInt<4>(0hd), remapindex_15)
when _T_2823 :
connect remapVecData[15], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[15]
node _T_2824 = eq(UInt<4>(0he), remapindex_15)
when _T_2824 :
connect remapVecData[15], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[15]
node _T_2825 = eq(UInt<4>(0hf), remapindex_15)
when _T_2825 :
connect remapVecData[15], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[15]
node _T_2826 = eq(UInt<5>(0h10), remapindex_15)
when _T_2826 :
connect remapVecData[15], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[15]
node _T_2827 = eq(UInt<5>(0h11), remapindex_15)
when _T_2827 :
connect remapVecData[15], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[15]
node _T_2828 = eq(UInt<5>(0h12), remapindex_15)
when _T_2828 :
connect remapVecData[15], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[15]
node _T_2829 = eq(UInt<5>(0h13), remapindex_15)
when _T_2829 :
connect remapVecData[15], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[15]
node _T_2830 = eq(UInt<5>(0h14), remapindex_15)
when _T_2830 :
connect remapVecData[15], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[15]
node _T_2831 = eq(UInt<5>(0h15), remapindex_15)
when _T_2831 :
connect remapVecData[15], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[15]
node _T_2832 = eq(UInt<5>(0h16), remapindex_15)
when _T_2832 :
connect remapVecData[15], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[15]
node _T_2833 = eq(UInt<5>(0h17), remapindex_15)
when _T_2833 :
connect remapVecData[15], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[15]
node _T_2834 = eq(UInt<5>(0h18), remapindex_15)
when _T_2834 :
connect remapVecData[15], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[15]
node _T_2835 = eq(UInt<5>(0h19), remapindex_15)
when _T_2835 :
connect remapVecData[15], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[15]
node _T_2836 = eq(UInt<5>(0h1a), remapindex_15)
when _T_2836 :
connect remapVecData[15], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[15]
node _T_2837 = eq(UInt<5>(0h1b), remapindex_15)
when _T_2837 :
connect remapVecData[15], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[15]
node _T_2838 = eq(UInt<5>(0h1c), remapindex_15)
when _T_2838 :
connect remapVecData[15], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[15]
node _T_2839 = eq(UInt<5>(0h1d), remapindex_15)
when _T_2839 :
connect remapVecData[15], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[15]
node _T_2840 = eq(UInt<5>(0h1e), remapindex_15)
when _T_2840 :
connect remapVecData[15], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[15]
node _T_2841 = eq(UInt<5>(0h1f), remapindex_15)
when _T_2841 :
connect remapVecData[15], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[15]
node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index)
node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20))
node _T_2842 = eq(UInt<1>(0h0), remapindex_16)
when _T_2842 :
connect remapVecData[16], Queue64_UInt8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[16]
node _T_2843 = eq(UInt<1>(0h1), remapindex_16)
when _T_2843 :
connect remapVecData[16], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[16]
node _T_2844 = eq(UInt<2>(0h2), remapindex_16)
when _T_2844 :
connect remapVecData[16], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[16]
node _T_2845 = eq(UInt<2>(0h3), remapindex_16)
when _T_2845 :
connect remapVecData[16], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[16]
node _T_2846 = eq(UInt<3>(0h4), remapindex_16)
when _T_2846 :
connect remapVecData[16], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[16]
node _T_2847 = eq(UInt<3>(0h5), remapindex_16)
when _T_2847 :
connect remapVecData[16], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[16]
node _T_2848 = eq(UInt<3>(0h6), remapindex_16)
when _T_2848 :
connect remapVecData[16], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[16]
node _T_2849 = eq(UInt<3>(0h7), remapindex_16)
when _T_2849 :
connect remapVecData[16], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[16]
node _T_2850 = eq(UInt<4>(0h8), remapindex_16)
when _T_2850 :
connect remapVecData[16], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[16]
node _T_2851 = eq(UInt<4>(0h9), remapindex_16)
when _T_2851 :
connect remapVecData[16], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[16]
node _T_2852 = eq(UInt<4>(0ha), remapindex_16)
when _T_2852 :
connect remapVecData[16], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[16]
node _T_2853 = eq(UInt<4>(0hb), remapindex_16)
when _T_2853 :
connect remapVecData[16], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[16]
node _T_2854 = eq(UInt<4>(0hc), remapindex_16)
when _T_2854 :
connect remapVecData[16], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[16]
node _T_2855 = eq(UInt<4>(0hd), remapindex_16)
when _T_2855 :
connect remapVecData[16], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[16]
node _T_2856 = eq(UInt<4>(0he), remapindex_16)
when _T_2856 :
connect remapVecData[16], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[16]
node _T_2857 = eq(UInt<4>(0hf), remapindex_16)
when _T_2857 :
connect remapVecData[16], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[16]
node _T_2858 = eq(UInt<5>(0h10), remapindex_16)
when _T_2858 :
connect remapVecData[16], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[16]
node _T_2859 = eq(UInt<5>(0h11), remapindex_16)
when _T_2859 :
connect remapVecData[16], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[16]
node _T_2860 = eq(UInt<5>(0h12), remapindex_16)
when _T_2860 :
connect remapVecData[16], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[16]
node _T_2861 = eq(UInt<5>(0h13), remapindex_16)
when _T_2861 :
connect remapVecData[16], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[16]
node _T_2862 = eq(UInt<5>(0h14), remapindex_16)
when _T_2862 :
connect remapVecData[16], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[16]
node _T_2863 = eq(UInt<5>(0h15), remapindex_16)
when _T_2863 :
connect remapVecData[16], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[16]
node _T_2864 = eq(UInt<5>(0h16), remapindex_16)
when _T_2864 :
connect remapVecData[16], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[16]
node _T_2865 = eq(UInt<5>(0h17), remapindex_16)
when _T_2865 :
connect remapVecData[16], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[16]
node _T_2866 = eq(UInt<5>(0h18), remapindex_16)
when _T_2866 :
connect remapVecData[16], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[16]
node _T_2867 = eq(UInt<5>(0h19), remapindex_16)
when _T_2867 :
connect remapVecData[16], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[16]
node _T_2868 = eq(UInt<5>(0h1a), remapindex_16)
when _T_2868 :
connect remapVecData[16], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[16]
node _T_2869 = eq(UInt<5>(0h1b), remapindex_16)
when _T_2869 :
connect remapVecData[16], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[16]
node _T_2870 = eq(UInt<5>(0h1c), remapindex_16)
when _T_2870 :
connect remapVecData[16], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[16]
node _T_2871 = eq(UInt<5>(0h1d), remapindex_16)
when _T_2871 :
connect remapVecData[16], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[16]
node _T_2872 = eq(UInt<5>(0h1e), remapindex_16)
when _T_2872 :
connect remapVecData[16], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[16]
node _T_2873 = eq(UInt<5>(0h1f), remapindex_16)
when _T_2873 :
connect remapVecData[16], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[16]
node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index)
node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20))
node _T_2874 = eq(UInt<1>(0h0), remapindex_17)
when _T_2874 :
connect remapVecData[17], Queue64_UInt8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[17]
node _T_2875 = eq(UInt<1>(0h1), remapindex_17)
when _T_2875 :
connect remapVecData[17], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[17]
node _T_2876 = eq(UInt<2>(0h2), remapindex_17)
when _T_2876 :
connect remapVecData[17], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[17]
node _T_2877 = eq(UInt<2>(0h3), remapindex_17)
when _T_2877 :
connect remapVecData[17], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[17]
node _T_2878 = eq(UInt<3>(0h4), remapindex_17)
when _T_2878 :
connect remapVecData[17], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[17]
node _T_2879 = eq(UInt<3>(0h5), remapindex_17)
when _T_2879 :
connect remapVecData[17], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[17]
node _T_2880 = eq(UInt<3>(0h6), remapindex_17)
when _T_2880 :
connect remapVecData[17], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[17]
node _T_2881 = eq(UInt<3>(0h7), remapindex_17)
when _T_2881 :
connect remapVecData[17], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[17]
node _T_2882 = eq(UInt<4>(0h8), remapindex_17)
when _T_2882 :
connect remapVecData[17], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[17]
node _T_2883 = eq(UInt<4>(0h9), remapindex_17)
when _T_2883 :
connect remapVecData[17], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[17]
node _T_2884 = eq(UInt<4>(0ha), remapindex_17)
when _T_2884 :
connect remapVecData[17], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[17]
node _T_2885 = eq(UInt<4>(0hb), remapindex_17)
when _T_2885 :
connect remapVecData[17], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[17]
node _T_2886 = eq(UInt<4>(0hc), remapindex_17)
when _T_2886 :
connect remapVecData[17], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[17]
node _T_2887 = eq(UInt<4>(0hd), remapindex_17)
when _T_2887 :
connect remapVecData[17], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[17]
node _T_2888 = eq(UInt<4>(0he), remapindex_17)
when _T_2888 :
connect remapVecData[17], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[17]
node _T_2889 = eq(UInt<4>(0hf), remapindex_17)
when _T_2889 :
connect remapVecData[17], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[17]
node _T_2890 = eq(UInt<5>(0h10), remapindex_17)
when _T_2890 :
connect remapVecData[17], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[17]
node _T_2891 = eq(UInt<5>(0h11), remapindex_17)
when _T_2891 :
connect remapVecData[17], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[17]
node _T_2892 = eq(UInt<5>(0h12), remapindex_17)
when _T_2892 :
connect remapVecData[17], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[17]
node _T_2893 = eq(UInt<5>(0h13), remapindex_17)
when _T_2893 :
connect remapVecData[17], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[17]
node _T_2894 = eq(UInt<5>(0h14), remapindex_17)
when _T_2894 :
connect remapVecData[17], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[17]
node _T_2895 = eq(UInt<5>(0h15), remapindex_17)
when _T_2895 :
connect remapVecData[17], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[17]
node _T_2896 = eq(UInt<5>(0h16), remapindex_17)
when _T_2896 :
connect remapVecData[17], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[17]
node _T_2897 = eq(UInt<5>(0h17), remapindex_17)
when _T_2897 :
connect remapVecData[17], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[17]
node _T_2898 = eq(UInt<5>(0h18), remapindex_17)
when _T_2898 :
connect remapVecData[17], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[17]
node _T_2899 = eq(UInt<5>(0h19), remapindex_17)
when _T_2899 :
connect remapVecData[17], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[17]
node _T_2900 = eq(UInt<5>(0h1a), remapindex_17)
when _T_2900 :
connect remapVecData[17], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[17]
node _T_2901 = eq(UInt<5>(0h1b), remapindex_17)
when _T_2901 :
connect remapVecData[17], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[17]
node _T_2902 = eq(UInt<5>(0h1c), remapindex_17)
when _T_2902 :
connect remapVecData[17], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[17]
node _T_2903 = eq(UInt<5>(0h1d), remapindex_17)
when _T_2903 :
connect remapVecData[17], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[17]
node _T_2904 = eq(UInt<5>(0h1e), remapindex_17)
when _T_2904 :
connect remapVecData[17], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[17]
node _T_2905 = eq(UInt<5>(0h1f), remapindex_17)
when _T_2905 :
connect remapVecData[17], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[17]
node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index)
node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20))
node _T_2906 = eq(UInt<1>(0h0), remapindex_18)
when _T_2906 :
connect remapVecData[18], Queue64_UInt8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[18]
node _T_2907 = eq(UInt<1>(0h1), remapindex_18)
when _T_2907 :
connect remapVecData[18], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[18]
node _T_2908 = eq(UInt<2>(0h2), remapindex_18)
when _T_2908 :
connect remapVecData[18], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[18]
node _T_2909 = eq(UInt<2>(0h3), remapindex_18)
when _T_2909 :
connect remapVecData[18], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[18]
node _T_2910 = eq(UInt<3>(0h4), remapindex_18)
when _T_2910 :
connect remapVecData[18], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[18]
node _T_2911 = eq(UInt<3>(0h5), remapindex_18)
when _T_2911 :
connect remapVecData[18], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[18]
node _T_2912 = eq(UInt<3>(0h6), remapindex_18)
when _T_2912 :
connect remapVecData[18], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[18]
node _T_2913 = eq(UInt<3>(0h7), remapindex_18)
when _T_2913 :
connect remapVecData[18], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[18]
node _T_2914 = eq(UInt<4>(0h8), remapindex_18)
when _T_2914 :
connect remapVecData[18], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[18]
node _T_2915 = eq(UInt<4>(0h9), remapindex_18)
when _T_2915 :
connect remapVecData[18], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[18]
node _T_2916 = eq(UInt<4>(0ha), remapindex_18)
when _T_2916 :
connect remapVecData[18], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[18]
node _T_2917 = eq(UInt<4>(0hb), remapindex_18)
when _T_2917 :
connect remapVecData[18], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[18]
node _T_2918 = eq(UInt<4>(0hc), remapindex_18)
when _T_2918 :
connect remapVecData[18], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[18]
node _T_2919 = eq(UInt<4>(0hd), remapindex_18)
when _T_2919 :
connect remapVecData[18], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[18]
node _T_2920 = eq(UInt<4>(0he), remapindex_18)
when _T_2920 :
connect remapVecData[18], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[18]
node _T_2921 = eq(UInt<4>(0hf), remapindex_18)
when _T_2921 :
connect remapVecData[18], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[18]
node _T_2922 = eq(UInt<5>(0h10), remapindex_18)
when _T_2922 :
connect remapVecData[18], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[18]
node _T_2923 = eq(UInt<5>(0h11), remapindex_18)
when _T_2923 :
connect remapVecData[18], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[18]
node _T_2924 = eq(UInt<5>(0h12), remapindex_18)
when _T_2924 :
connect remapVecData[18], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[18]
node _T_2925 = eq(UInt<5>(0h13), remapindex_18)
when _T_2925 :
connect remapVecData[18], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[18]
node _T_2926 = eq(UInt<5>(0h14), remapindex_18)
when _T_2926 :
connect remapVecData[18], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[18]
node _T_2927 = eq(UInt<5>(0h15), remapindex_18)
when _T_2927 :
connect remapVecData[18], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[18]
node _T_2928 = eq(UInt<5>(0h16), remapindex_18)
when _T_2928 :
connect remapVecData[18], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[18]
node _T_2929 = eq(UInt<5>(0h17), remapindex_18)
when _T_2929 :
connect remapVecData[18], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[18]
node _T_2930 = eq(UInt<5>(0h18), remapindex_18)
when _T_2930 :
connect remapVecData[18], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[18]
node _T_2931 = eq(UInt<5>(0h19), remapindex_18)
when _T_2931 :
connect remapVecData[18], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[18]
node _T_2932 = eq(UInt<5>(0h1a), remapindex_18)
when _T_2932 :
connect remapVecData[18], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[18]
node _T_2933 = eq(UInt<5>(0h1b), remapindex_18)
when _T_2933 :
connect remapVecData[18], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[18]
node _T_2934 = eq(UInt<5>(0h1c), remapindex_18)
when _T_2934 :
connect remapVecData[18], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[18]
node _T_2935 = eq(UInt<5>(0h1d), remapindex_18)
when _T_2935 :
connect remapVecData[18], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[18]
node _T_2936 = eq(UInt<5>(0h1e), remapindex_18)
when _T_2936 :
connect remapVecData[18], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[18]
node _T_2937 = eq(UInt<5>(0h1f), remapindex_18)
when _T_2937 :
connect remapVecData[18], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[18]
node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index)
node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20))
node _T_2938 = eq(UInt<1>(0h0), remapindex_19)
when _T_2938 :
connect remapVecData[19], Queue64_UInt8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[19]
node _T_2939 = eq(UInt<1>(0h1), remapindex_19)
when _T_2939 :
connect remapVecData[19], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[19]
node _T_2940 = eq(UInt<2>(0h2), remapindex_19)
when _T_2940 :
connect remapVecData[19], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[19]
node _T_2941 = eq(UInt<2>(0h3), remapindex_19)
when _T_2941 :
connect remapVecData[19], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[19]
node _T_2942 = eq(UInt<3>(0h4), remapindex_19)
when _T_2942 :
connect remapVecData[19], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[19]
node _T_2943 = eq(UInt<3>(0h5), remapindex_19)
when _T_2943 :
connect remapVecData[19], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[19]
node _T_2944 = eq(UInt<3>(0h6), remapindex_19)
when _T_2944 :
connect remapVecData[19], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[19]
node _T_2945 = eq(UInt<3>(0h7), remapindex_19)
when _T_2945 :
connect remapVecData[19], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[19]
node _T_2946 = eq(UInt<4>(0h8), remapindex_19)
when _T_2946 :
connect remapVecData[19], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[19]
node _T_2947 = eq(UInt<4>(0h9), remapindex_19)
when _T_2947 :
connect remapVecData[19], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[19]
node _T_2948 = eq(UInt<4>(0ha), remapindex_19)
when _T_2948 :
connect remapVecData[19], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[19]
node _T_2949 = eq(UInt<4>(0hb), remapindex_19)
when _T_2949 :
connect remapVecData[19], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[19]
node _T_2950 = eq(UInt<4>(0hc), remapindex_19)
when _T_2950 :
connect remapVecData[19], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[19]
node _T_2951 = eq(UInt<4>(0hd), remapindex_19)
when _T_2951 :
connect remapVecData[19], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[19]
node _T_2952 = eq(UInt<4>(0he), remapindex_19)
when _T_2952 :
connect remapVecData[19], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[19]
node _T_2953 = eq(UInt<4>(0hf), remapindex_19)
when _T_2953 :
connect remapVecData[19], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[19]
node _T_2954 = eq(UInt<5>(0h10), remapindex_19)
when _T_2954 :
connect remapVecData[19], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[19]
node _T_2955 = eq(UInt<5>(0h11), remapindex_19)
when _T_2955 :
connect remapVecData[19], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[19]
node _T_2956 = eq(UInt<5>(0h12), remapindex_19)
when _T_2956 :
connect remapVecData[19], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[19]
node _T_2957 = eq(UInt<5>(0h13), remapindex_19)
when _T_2957 :
connect remapVecData[19], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[19]
node _T_2958 = eq(UInt<5>(0h14), remapindex_19)
when _T_2958 :
connect remapVecData[19], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[19]
node _T_2959 = eq(UInt<5>(0h15), remapindex_19)
when _T_2959 :
connect remapVecData[19], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[19]
node _T_2960 = eq(UInt<5>(0h16), remapindex_19)
when _T_2960 :
connect remapVecData[19], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[19]
node _T_2961 = eq(UInt<5>(0h17), remapindex_19)
when _T_2961 :
connect remapVecData[19], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[19]
node _T_2962 = eq(UInt<5>(0h18), remapindex_19)
when _T_2962 :
connect remapVecData[19], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[19]
node _T_2963 = eq(UInt<5>(0h19), remapindex_19)
when _T_2963 :
connect remapVecData[19], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[19]
node _T_2964 = eq(UInt<5>(0h1a), remapindex_19)
when _T_2964 :
connect remapVecData[19], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[19]
node _T_2965 = eq(UInt<5>(0h1b), remapindex_19)
when _T_2965 :
connect remapVecData[19], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[19]
node _T_2966 = eq(UInt<5>(0h1c), remapindex_19)
when _T_2966 :
connect remapVecData[19], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[19]
node _T_2967 = eq(UInt<5>(0h1d), remapindex_19)
when _T_2967 :
connect remapVecData[19], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[19]
node _T_2968 = eq(UInt<5>(0h1e), remapindex_19)
when _T_2968 :
connect remapVecData[19], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[19]
node _T_2969 = eq(UInt<5>(0h1f), remapindex_19)
when _T_2969 :
connect remapVecData[19], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[19]
node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index)
node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20))
node _T_2970 = eq(UInt<1>(0h0), remapindex_20)
when _T_2970 :
connect remapVecData[20], Queue64_UInt8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[20]
node _T_2971 = eq(UInt<1>(0h1), remapindex_20)
when _T_2971 :
connect remapVecData[20], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[20]
node _T_2972 = eq(UInt<2>(0h2), remapindex_20)
when _T_2972 :
connect remapVecData[20], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[20]
node _T_2973 = eq(UInt<2>(0h3), remapindex_20)
when _T_2973 :
connect remapVecData[20], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[20]
node _T_2974 = eq(UInt<3>(0h4), remapindex_20)
when _T_2974 :
connect remapVecData[20], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[20]
node _T_2975 = eq(UInt<3>(0h5), remapindex_20)
when _T_2975 :
connect remapVecData[20], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[20]
node _T_2976 = eq(UInt<3>(0h6), remapindex_20)
when _T_2976 :
connect remapVecData[20], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[20]
node _T_2977 = eq(UInt<3>(0h7), remapindex_20)
when _T_2977 :
connect remapVecData[20], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[20]
node _T_2978 = eq(UInt<4>(0h8), remapindex_20)
when _T_2978 :
connect remapVecData[20], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[20]
node _T_2979 = eq(UInt<4>(0h9), remapindex_20)
when _T_2979 :
connect remapVecData[20], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[20]
node _T_2980 = eq(UInt<4>(0ha), remapindex_20)
when _T_2980 :
connect remapVecData[20], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[20]
node _T_2981 = eq(UInt<4>(0hb), remapindex_20)
when _T_2981 :
connect remapVecData[20], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[20]
node _T_2982 = eq(UInt<4>(0hc), remapindex_20)
when _T_2982 :
connect remapVecData[20], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[20]
node _T_2983 = eq(UInt<4>(0hd), remapindex_20)
when _T_2983 :
connect remapVecData[20], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[20]
node _T_2984 = eq(UInt<4>(0he), remapindex_20)
when _T_2984 :
connect remapVecData[20], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[20]
node _T_2985 = eq(UInt<4>(0hf), remapindex_20)
when _T_2985 :
connect remapVecData[20], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[20]
node _T_2986 = eq(UInt<5>(0h10), remapindex_20)
when _T_2986 :
connect remapVecData[20], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[20]
node _T_2987 = eq(UInt<5>(0h11), remapindex_20)
when _T_2987 :
connect remapVecData[20], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[20]
node _T_2988 = eq(UInt<5>(0h12), remapindex_20)
when _T_2988 :
connect remapVecData[20], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[20]
node _T_2989 = eq(UInt<5>(0h13), remapindex_20)
when _T_2989 :
connect remapVecData[20], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[20]
node _T_2990 = eq(UInt<5>(0h14), remapindex_20)
when _T_2990 :
connect remapVecData[20], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[20]
node _T_2991 = eq(UInt<5>(0h15), remapindex_20)
when _T_2991 :
connect remapVecData[20], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[20]
node _T_2992 = eq(UInt<5>(0h16), remapindex_20)
when _T_2992 :
connect remapVecData[20], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[20]
node _T_2993 = eq(UInt<5>(0h17), remapindex_20)
when _T_2993 :
connect remapVecData[20], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[20]
node _T_2994 = eq(UInt<5>(0h18), remapindex_20)
when _T_2994 :
connect remapVecData[20], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[20]
node _T_2995 = eq(UInt<5>(0h19), remapindex_20)
when _T_2995 :
connect remapVecData[20], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[20]
node _T_2996 = eq(UInt<5>(0h1a), remapindex_20)
when _T_2996 :
connect remapVecData[20], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[20]
node _T_2997 = eq(UInt<5>(0h1b), remapindex_20)
when _T_2997 :
connect remapVecData[20], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[20]
node _T_2998 = eq(UInt<5>(0h1c), remapindex_20)
when _T_2998 :
connect remapVecData[20], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[20]
node _T_2999 = eq(UInt<5>(0h1d), remapindex_20)
when _T_2999 :
connect remapVecData[20], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[20]
node _T_3000 = eq(UInt<5>(0h1e), remapindex_20)
when _T_3000 :
connect remapVecData[20], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[20]
node _T_3001 = eq(UInt<5>(0h1f), remapindex_20)
when _T_3001 :
connect remapVecData[20], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[20]
node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index)
node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20))
node _T_3002 = eq(UInt<1>(0h0), remapindex_21)
when _T_3002 :
connect remapVecData[21], Queue64_UInt8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[21]
node _T_3003 = eq(UInt<1>(0h1), remapindex_21)
when _T_3003 :
connect remapVecData[21], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[21]
node _T_3004 = eq(UInt<2>(0h2), remapindex_21)
when _T_3004 :
connect remapVecData[21], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[21]
node _T_3005 = eq(UInt<2>(0h3), remapindex_21)
when _T_3005 :
connect remapVecData[21], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[21]
node _T_3006 = eq(UInt<3>(0h4), remapindex_21)
when _T_3006 :
connect remapVecData[21], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[21]
node _T_3007 = eq(UInt<3>(0h5), remapindex_21)
when _T_3007 :
connect remapVecData[21], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[21]
node _T_3008 = eq(UInt<3>(0h6), remapindex_21)
when _T_3008 :
connect remapVecData[21], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[21]
node _T_3009 = eq(UInt<3>(0h7), remapindex_21)
when _T_3009 :
connect remapVecData[21], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[21]
node _T_3010 = eq(UInt<4>(0h8), remapindex_21)
when _T_3010 :
connect remapVecData[21], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[21]
node _T_3011 = eq(UInt<4>(0h9), remapindex_21)
when _T_3011 :
connect remapVecData[21], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[21]
node _T_3012 = eq(UInt<4>(0ha), remapindex_21)
when _T_3012 :
connect remapVecData[21], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[21]
node _T_3013 = eq(UInt<4>(0hb), remapindex_21)
when _T_3013 :
connect remapVecData[21], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[21]
node _T_3014 = eq(UInt<4>(0hc), remapindex_21)
when _T_3014 :
connect remapVecData[21], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[21]
node _T_3015 = eq(UInt<4>(0hd), remapindex_21)
when _T_3015 :
connect remapVecData[21], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[21]
node _T_3016 = eq(UInt<4>(0he), remapindex_21)
when _T_3016 :
connect remapVecData[21], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[21]
node _T_3017 = eq(UInt<4>(0hf), remapindex_21)
when _T_3017 :
connect remapVecData[21], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[21]
node _T_3018 = eq(UInt<5>(0h10), remapindex_21)
when _T_3018 :
connect remapVecData[21], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[21]
node _T_3019 = eq(UInt<5>(0h11), remapindex_21)
when _T_3019 :
connect remapVecData[21], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[21]
node _T_3020 = eq(UInt<5>(0h12), remapindex_21)
when _T_3020 :
connect remapVecData[21], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[21]
node _T_3021 = eq(UInt<5>(0h13), remapindex_21)
when _T_3021 :
connect remapVecData[21], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[21]
node _T_3022 = eq(UInt<5>(0h14), remapindex_21)
when _T_3022 :
connect remapVecData[21], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[21]
node _T_3023 = eq(UInt<5>(0h15), remapindex_21)
when _T_3023 :
connect remapVecData[21], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[21]
node _T_3024 = eq(UInt<5>(0h16), remapindex_21)
when _T_3024 :
connect remapVecData[21], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[21]
node _T_3025 = eq(UInt<5>(0h17), remapindex_21)
when _T_3025 :
connect remapVecData[21], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[21]
node _T_3026 = eq(UInt<5>(0h18), remapindex_21)
when _T_3026 :
connect remapVecData[21], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[21]
node _T_3027 = eq(UInt<5>(0h19), remapindex_21)
when _T_3027 :
connect remapVecData[21], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[21]
node _T_3028 = eq(UInt<5>(0h1a), remapindex_21)
when _T_3028 :
connect remapVecData[21], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[21]
node _T_3029 = eq(UInt<5>(0h1b), remapindex_21)
when _T_3029 :
connect remapVecData[21], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[21]
node _T_3030 = eq(UInt<5>(0h1c), remapindex_21)
when _T_3030 :
connect remapVecData[21], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[21]
node _T_3031 = eq(UInt<5>(0h1d), remapindex_21)
when _T_3031 :
connect remapVecData[21], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[21]
node _T_3032 = eq(UInt<5>(0h1e), remapindex_21)
when _T_3032 :
connect remapVecData[21], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[21]
node _T_3033 = eq(UInt<5>(0h1f), remapindex_21)
when _T_3033 :
connect remapVecData[21], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[21]
node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index)
node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20))
node _T_3034 = eq(UInt<1>(0h0), remapindex_22)
when _T_3034 :
connect remapVecData[22], Queue64_UInt8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[22]
node _T_3035 = eq(UInt<1>(0h1), remapindex_22)
when _T_3035 :
connect remapVecData[22], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[22]
node _T_3036 = eq(UInt<2>(0h2), remapindex_22)
when _T_3036 :
connect remapVecData[22], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[22]
node _T_3037 = eq(UInt<2>(0h3), remapindex_22)
when _T_3037 :
connect remapVecData[22], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[22]
node _T_3038 = eq(UInt<3>(0h4), remapindex_22)
when _T_3038 :
connect remapVecData[22], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[22]
node _T_3039 = eq(UInt<3>(0h5), remapindex_22)
when _T_3039 :
connect remapVecData[22], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[22]
node _T_3040 = eq(UInt<3>(0h6), remapindex_22)
when _T_3040 :
connect remapVecData[22], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[22]
node _T_3041 = eq(UInt<3>(0h7), remapindex_22)
when _T_3041 :
connect remapVecData[22], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[22]
node _T_3042 = eq(UInt<4>(0h8), remapindex_22)
when _T_3042 :
connect remapVecData[22], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[22]
node _T_3043 = eq(UInt<4>(0h9), remapindex_22)
when _T_3043 :
connect remapVecData[22], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[22]
node _T_3044 = eq(UInt<4>(0ha), remapindex_22)
when _T_3044 :
connect remapVecData[22], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[22]
node _T_3045 = eq(UInt<4>(0hb), remapindex_22)
when _T_3045 :
connect remapVecData[22], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[22]
node _T_3046 = eq(UInt<4>(0hc), remapindex_22)
when _T_3046 :
connect remapVecData[22], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[22]
node _T_3047 = eq(UInt<4>(0hd), remapindex_22)
when _T_3047 :
connect remapVecData[22], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[22]
node _T_3048 = eq(UInt<4>(0he), remapindex_22)
when _T_3048 :
connect remapVecData[22], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[22]
node _T_3049 = eq(UInt<4>(0hf), remapindex_22)
when _T_3049 :
connect remapVecData[22], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[22]
node _T_3050 = eq(UInt<5>(0h10), remapindex_22)
when _T_3050 :
connect remapVecData[22], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[22]
node _T_3051 = eq(UInt<5>(0h11), remapindex_22)
when _T_3051 :
connect remapVecData[22], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[22]
node _T_3052 = eq(UInt<5>(0h12), remapindex_22)
when _T_3052 :
connect remapVecData[22], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[22]
node _T_3053 = eq(UInt<5>(0h13), remapindex_22)
when _T_3053 :
connect remapVecData[22], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[22]
node _T_3054 = eq(UInt<5>(0h14), remapindex_22)
when _T_3054 :
connect remapVecData[22], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[22]
node _T_3055 = eq(UInt<5>(0h15), remapindex_22)
when _T_3055 :
connect remapVecData[22], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[22]
node _T_3056 = eq(UInt<5>(0h16), remapindex_22)
when _T_3056 :
connect remapVecData[22], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[22]
node _T_3057 = eq(UInt<5>(0h17), remapindex_22)
when _T_3057 :
connect remapVecData[22], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[22]
node _T_3058 = eq(UInt<5>(0h18), remapindex_22)
when _T_3058 :
connect remapVecData[22], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[22]
node _T_3059 = eq(UInt<5>(0h19), remapindex_22)
when _T_3059 :
connect remapVecData[22], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[22]
node _T_3060 = eq(UInt<5>(0h1a), remapindex_22)
when _T_3060 :
connect remapVecData[22], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[22]
node _T_3061 = eq(UInt<5>(0h1b), remapindex_22)
when _T_3061 :
connect remapVecData[22], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[22]
node _T_3062 = eq(UInt<5>(0h1c), remapindex_22)
when _T_3062 :
connect remapVecData[22], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[22]
node _T_3063 = eq(UInt<5>(0h1d), remapindex_22)
when _T_3063 :
connect remapVecData[22], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[22]
node _T_3064 = eq(UInt<5>(0h1e), remapindex_22)
when _T_3064 :
connect remapVecData[22], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[22]
node _T_3065 = eq(UInt<5>(0h1f), remapindex_22)
when _T_3065 :
connect remapVecData[22], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[22]
node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index)
node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20))
node _T_3066 = eq(UInt<1>(0h0), remapindex_23)
when _T_3066 :
connect remapVecData[23], Queue64_UInt8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[23]
node _T_3067 = eq(UInt<1>(0h1), remapindex_23)
when _T_3067 :
connect remapVecData[23], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[23]
node _T_3068 = eq(UInt<2>(0h2), remapindex_23)
when _T_3068 :
connect remapVecData[23], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[23]
node _T_3069 = eq(UInt<2>(0h3), remapindex_23)
when _T_3069 :
connect remapVecData[23], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[23]
node _T_3070 = eq(UInt<3>(0h4), remapindex_23)
when _T_3070 :
connect remapVecData[23], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[23]
node _T_3071 = eq(UInt<3>(0h5), remapindex_23)
when _T_3071 :
connect remapVecData[23], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[23]
node _T_3072 = eq(UInt<3>(0h6), remapindex_23)
when _T_3072 :
connect remapVecData[23], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[23]
node _T_3073 = eq(UInt<3>(0h7), remapindex_23)
when _T_3073 :
connect remapVecData[23], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[23]
node _T_3074 = eq(UInt<4>(0h8), remapindex_23)
when _T_3074 :
connect remapVecData[23], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[23]
node _T_3075 = eq(UInt<4>(0h9), remapindex_23)
when _T_3075 :
connect remapVecData[23], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[23]
node _T_3076 = eq(UInt<4>(0ha), remapindex_23)
when _T_3076 :
connect remapVecData[23], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[23]
node _T_3077 = eq(UInt<4>(0hb), remapindex_23)
when _T_3077 :
connect remapVecData[23], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[23]
node _T_3078 = eq(UInt<4>(0hc), remapindex_23)
when _T_3078 :
connect remapVecData[23], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[23]
node _T_3079 = eq(UInt<4>(0hd), remapindex_23)
when _T_3079 :
connect remapVecData[23], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[23]
node _T_3080 = eq(UInt<4>(0he), remapindex_23)
when _T_3080 :
connect remapVecData[23], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[23]
node _T_3081 = eq(UInt<4>(0hf), remapindex_23)
when _T_3081 :
connect remapVecData[23], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[23]
node _T_3082 = eq(UInt<5>(0h10), remapindex_23)
when _T_3082 :
connect remapVecData[23], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[23]
node _T_3083 = eq(UInt<5>(0h11), remapindex_23)
when _T_3083 :
connect remapVecData[23], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[23]
node _T_3084 = eq(UInt<5>(0h12), remapindex_23)
when _T_3084 :
connect remapVecData[23], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[23]
node _T_3085 = eq(UInt<5>(0h13), remapindex_23)
when _T_3085 :
connect remapVecData[23], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[23]
node _T_3086 = eq(UInt<5>(0h14), remapindex_23)
when _T_3086 :
connect remapVecData[23], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[23]
node _T_3087 = eq(UInt<5>(0h15), remapindex_23)
when _T_3087 :
connect remapVecData[23], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[23]
node _T_3088 = eq(UInt<5>(0h16), remapindex_23)
when _T_3088 :
connect remapVecData[23], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[23]
node _T_3089 = eq(UInt<5>(0h17), remapindex_23)
when _T_3089 :
connect remapVecData[23], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[23]
node _T_3090 = eq(UInt<5>(0h18), remapindex_23)
when _T_3090 :
connect remapVecData[23], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[23]
node _T_3091 = eq(UInt<5>(0h19), remapindex_23)
when _T_3091 :
connect remapVecData[23], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[23]
node _T_3092 = eq(UInt<5>(0h1a), remapindex_23)
when _T_3092 :
connect remapVecData[23], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[23]
node _T_3093 = eq(UInt<5>(0h1b), remapindex_23)
when _T_3093 :
connect remapVecData[23], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[23]
node _T_3094 = eq(UInt<5>(0h1c), remapindex_23)
when _T_3094 :
connect remapVecData[23], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[23]
node _T_3095 = eq(UInt<5>(0h1d), remapindex_23)
when _T_3095 :
connect remapVecData[23], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[23]
node _T_3096 = eq(UInt<5>(0h1e), remapindex_23)
when _T_3096 :
connect remapVecData[23], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[23]
node _T_3097 = eq(UInt<5>(0h1f), remapindex_23)
when _T_3097 :
connect remapVecData[23], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[23]
node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index)
node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20))
node _T_3098 = eq(UInt<1>(0h0), remapindex_24)
when _T_3098 :
connect remapVecData[24], Queue64_UInt8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[24]
node _T_3099 = eq(UInt<1>(0h1), remapindex_24)
when _T_3099 :
connect remapVecData[24], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[24]
node _T_3100 = eq(UInt<2>(0h2), remapindex_24)
when _T_3100 :
connect remapVecData[24], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[24]
node _T_3101 = eq(UInt<2>(0h3), remapindex_24)
when _T_3101 :
connect remapVecData[24], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[24]
node _T_3102 = eq(UInt<3>(0h4), remapindex_24)
when _T_3102 :
connect remapVecData[24], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[24]
node _T_3103 = eq(UInt<3>(0h5), remapindex_24)
when _T_3103 :
connect remapVecData[24], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[24]
node _T_3104 = eq(UInt<3>(0h6), remapindex_24)
when _T_3104 :
connect remapVecData[24], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[24]
node _T_3105 = eq(UInt<3>(0h7), remapindex_24)
when _T_3105 :
connect remapVecData[24], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[24]
node _T_3106 = eq(UInt<4>(0h8), remapindex_24)
when _T_3106 :
connect remapVecData[24], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[24]
node _T_3107 = eq(UInt<4>(0h9), remapindex_24)
when _T_3107 :
connect remapVecData[24], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[24]
node _T_3108 = eq(UInt<4>(0ha), remapindex_24)
when _T_3108 :
connect remapVecData[24], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[24]
node _T_3109 = eq(UInt<4>(0hb), remapindex_24)
when _T_3109 :
connect remapVecData[24], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[24]
node _T_3110 = eq(UInt<4>(0hc), remapindex_24)
when _T_3110 :
connect remapVecData[24], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[24]
node _T_3111 = eq(UInt<4>(0hd), remapindex_24)
when _T_3111 :
connect remapVecData[24], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[24]
node _T_3112 = eq(UInt<4>(0he), remapindex_24)
when _T_3112 :
connect remapVecData[24], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[24]
node _T_3113 = eq(UInt<4>(0hf), remapindex_24)
when _T_3113 :
connect remapVecData[24], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[24]
node _T_3114 = eq(UInt<5>(0h10), remapindex_24)
when _T_3114 :
connect remapVecData[24], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[24]
node _T_3115 = eq(UInt<5>(0h11), remapindex_24)
when _T_3115 :
connect remapVecData[24], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[24]
node _T_3116 = eq(UInt<5>(0h12), remapindex_24)
when _T_3116 :
connect remapVecData[24], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[24]
node _T_3117 = eq(UInt<5>(0h13), remapindex_24)
when _T_3117 :
connect remapVecData[24], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[24]
node _T_3118 = eq(UInt<5>(0h14), remapindex_24)
when _T_3118 :
connect remapVecData[24], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[24]
node _T_3119 = eq(UInt<5>(0h15), remapindex_24)
when _T_3119 :
connect remapVecData[24], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[24]
node _T_3120 = eq(UInt<5>(0h16), remapindex_24)
when _T_3120 :
connect remapVecData[24], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[24]
node _T_3121 = eq(UInt<5>(0h17), remapindex_24)
when _T_3121 :
connect remapVecData[24], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[24]
node _T_3122 = eq(UInt<5>(0h18), remapindex_24)
when _T_3122 :
connect remapVecData[24], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[24]
node _T_3123 = eq(UInt<5>(0h19), remapindex_24)
when _T_3123 :
connect remapVecData[24], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[24]
node _T_3124 = eq(UInt<5>(0h1a), remapindex_24)
when _T_3124 :
connect remapVecData[24], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[24]
node _T_3125 = eq(UInt<5>(0h1b), remapindex_24)
when _T_3125 :
connect remapVecData[24], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[24]
node _T_3126 = eq(UInt<5>(0h1c), remapindex_24)
when _T_3126 :
connect remapVecData[24], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[24]
node _T_3127 = eq(UInt<5>(0h1d), remapindex_24)
when _T_3127 :
connect remapVecData[24], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[24]
node _T_3128 = eq(UInt<5>(0h1e), remapindex_24)
when _T_3128 :
connect remapVecData[24], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[24]
node _T_3129 = eq(UInt<5>(0h1f), remapindex_24)
when _T_3129 :
connect remapVecData[24], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[24]
node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index)
node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20))
node _T_3130 = eq(UInt<1>(0h0), remapindex_25)
when _T_3130 :
connect remapVecData[25], Queue64_UInt8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[25]
node _T_3131 = eq(UInt<1>(0h1), remapindex_25)
when _T_3131 :
connect remapVecData[25], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[25]
node _T_3132 = eq(UInt<2>(0h2), remapindex_25)
when _T_3132 :
connect remapVecData[25], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[25]
node _T_3133 = eq(UInt<2>(0h3), remapindex_25)
when _T_3133 :
connect remapVecData[25], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[25]
node _T_3134 = eq(UInt<3>(0h4), remapindex_25)
when _T_3134 :
connect remapVecData[25], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[25]
node _T_3135 = eq(UInt<3>(0h5), remapindex_25)
when _T_3135 :
connect remapVecData[25], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[25]
node _T_3136 = eq(UInt<3>(0h6), remapindex_25)
when _T_3136 :
connect remapVecData[25], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[25]
node _T_3137 = eq(UInt<3>(0h7), remapindex_25)
when _T_3137 :
connect remapVecData[25], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[25]
node _T_3138 = eq(UInt<4>(0h8), remapindex_25)
when _T_3138 :
connect remapVecData[25], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[25]
node _T_3139 = eq(UInt<4>(0h9), remapindex_25)
when _T_3139 :
connect remapVecData[25], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[25]
node _T_3140 = eq(UInt<4>(0ha), remapindex_25)
when _T_3140 :
connect remapVecData[25], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[25]
node _T_3141 = eq(UInt<4>(0hb), remapindex_25)
when _T_3141 :
connect remapVecData[25], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[25]
node _T_3142 = eq(UInt<4>(0hc), remapindex_25)
when _T_3142 :
connect remapVecData[25], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[25]
node _T_3143 = eq(UInt<4>(0hd), remapindex_25)
when _T_3143 :
connect remapVecData[25], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[25]
node _T_3144 = eq(UInt<4>(0he), remapindex_25)
when _T_3144 :
connect remapVecData[25], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[25]
node _T_3145 = eq(UInt<4>(0hf), remapindex_25)
when _T_3145 :
connect remapVecData[25], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[25]
node _T_3146 = eq(UInt<5>(0h10), remapindex_25)
when _T_3146 :
connect remapVecData[25], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[25]
node _T_3147 = eq(UInt<5>(0h11), remapindex_25)
when _T_3147 :
connect remapVecData[25], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[25]
node _T_3148 = eq(UInt<5>(0h12), remapindex_25)
when _T_3148 :
connect remapVecData[25], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[25]
node _T_3149 = eq(UInt<5>(0h13), remapindex_25)
when _T_3149 :
connect remapVecData[25], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[25]
node _T_3150 = eq(UInt<5>(0h14), remapindex_25)
when _T_3150 :
connect remapVecData[25], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[25]
node _T_3151 = eq(UInt<5>(0h15), remapindex_25)
when _T_3151 :
connect remapVecData[25], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[25]
node _T_3152 = eq(UInt<5>(0h16), remapindex_25)
when _T_3152 :
connect remapVecData[25], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[25]
node _T_3153 = eq(UInt<5>(0h17), remapindex_25)
when _T_3153 :
connect remapVecData[25], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[25]
node _T_3154 = eq(UInt<5>(0h18), remapindex_25)
when _T_3154 :
connect remapVecData[25], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[25]
node _T_3155 = eq(UInt<5>(0h19), remapindex_25)
when _T_3155 :
connect remapVecData[25], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[25]
node _T_3156 = eq(UInt<5>(0h1a), remapindex_25)
when _T_3156 :
connect remapVecData[25], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[25]
node _T_3157 = eq(UInt<5>(0h1b), remapindex_25)
when _T_3157 :
connect remapVecData[25], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[25]
node _T_3158 = eq(UInt<5>(0h1c), remapindex_25)
when _T_3158 :
connect remapVecData[25], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[25]
node _T_3159 = eq(UInt<5>(0h1d), remapindex_25)
when _T_3159 :
connect remapVecData[25], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[25]
node _T_3160 = eq(UInt<5>(0h1e), remapindex_25)
when _T_3160 :
connect remapVecData[25], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[25]
node _T_3161 = eq(UInt<5>(0h1f), remapindex_25)
when _T_3161 :
connect remapVecData[25], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[25]
node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index)
node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20))
node _T_3162 = eq(UInt<1>(0h0), remapindex_26)
when _T_3162 :
connect remapVecData[26], Queue64_UInt8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[26]
node _T_3163 = eq(UInt<1>(0h1), remapindex_26)
when _T_3163 :
connect remapVecData[26], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[26]
node _T_3164 = eq(UInt<2>(0h2), remapindex_26)
when _T_3164 :
connect remapVecData[26], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[26]
node _T_3165 = eq(UInt<2>(0h3), remapindex_26)
when _T_3165 :
connect remapVecData[26], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[26]
node _T_3166 = eq(UInt<3>(0h4), remapindex_26)
when _T_3166 :
connect remapVecData[26], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[26]
node _T_3167 = eq(UInt<3>(0h5), remapindex_26)
when _T_3167 :
connect remapVecData[26], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[26]
node _T_3168 = eq(UInt<3>(0h6), remapindex_26)
when _T_3168 :
connect remapVecData[26], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[26]
node _T_3169 = eq(UInt<3>(0h7), remapindex_26)
when _T_3169 :
connect remapVecData[26], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[26]
node _T_3170 = eq(UInt<4>(0h8), remapindex_26)
when _T_3170 :
connect remapVecData[26], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[26]
node _T_3171 = eq(UInt<4>(0h9), remapindex_26)
when _T_3171 :
connect remapVecData[26], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[26]
node _T_3172 = eq(UInt<4>(0ha), remapindex_26)
when _T_3172 :
connect remapVecData[26], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[26]
node _T_3173 = eq(UInt<4>(0hb), remapindex_26)
when _T_3173 :
connect remapVecData[26], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[26]
node _T_3174 = eq(UInt<4>(0hc), remapindex_26)
when _T_3174 :
connect remapVecData[26], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[26]
node _T_3175 = eq(UInt<4>(0hd), remapindex_26)
when _T_3175 :
connect remapVecData[26], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[26]
node _T_3176 = eq(UInt<4>(0he), remapindex_26)
when _T_3176 :
connect remapVecData[26], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[26]
node _T_3177 = eq(UInt<4>(0hf), remapindex_26)
when _T_3177 :
connect remapVecData[26], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[26]
node _T_3178 = eq(UInt<5>(0h10), remapindex_26)
when _T_3178 :
connect remapVecData[26], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[26]
node _T_3179 = eq(UInt<5>(0h11), remapindex_26)
when _T_3179 :
connect remapVecData[26], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[26]
node _T_3180 = eq(UInt<5>(0h12), remapindex_26)
when _T_3180 :
connect remapVecData[26], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[26]
node _T_3181 = eq(UInt<5>(0h13), remapindex_26)
when _T_3181 :
connect remapVecData[26], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[26]
node _T_3182 = eq(UInt<5>(0h14), remapindex_26)
when _T_3182 :
connect remapVecData[26], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[26]
node _T_3183 = eq(UInt<5>(0h15), remapindex_26)
when _T_3183 :
connect remapVecData[26], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[26]
node _T_3184 = eq(UInt<5>(0h16), remapindex_26)
when _T_3184 :
connect remapVecData[26], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[26]
node _T_3185 = eq(UInt<5>(0h17), remapindex_26)
when _T_3185 :
connect remapVecData[26], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[26]
node _T_3186 = eq(UInt<5>(0h18), remapindex_26)
when _T_3186 :
connect remapVecData[26], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[26]
node _T_3187 = eq(UInt<5>(0h19), remapindex_26)
when _T_3187 :
connect remapVecData[26], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[26]
node _T_3188 = eq(UInt<5>(0h1a), remapindex_26)
when _T_3188 :
connect remapVecData[26], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[26]
node _T_3189 = eq(UInt<5>(0h1b), remapindex_26)
when _T_3189 :
connect remapVecData[26], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[26]
node _T_3190 = eq(UInt<5>(0h1c), remapindex_26)
when _T_3190 :
connect remapVecData[26], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[26]
node _T_3191 = eq(UInt<5>(0h1d), remapindex_26)
when _T_3191 :
connect remapVecData[26], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[26]
node _T_3192 = eq(UInt<5>(0h1e), remapindex_26)
when _T_3192 :
connect remapVecData[26], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[26]
node _T_3193 = eq(UInt<5>(0h1f), remapindex_26)
when _T_3193 :
connect remapVecData[26], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[26]
node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index)
node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20))
node _T_3194 = eq(UInt<1>(0h0), remapindex_27)
when _T_3194 :
connect remapVecData[27], Queue64_UInt8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[27]
node _T_3195 = eq(UInt<1>(0h1), remapindex_27)
when _T_3195 :
connect remapVecData[27], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[27]
node _T_3196 = eq(UInt<2>(0h2), remapindex_27)
when _T_3196 :
connect remapVecData[27], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[27]
node _T_3197 = eq(UInt<2>(0h3), remapindex_27)
when _T_3197 :
connect remapVecData[27], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[27]
node _T_3198 = eq(UInt<3>(0h4), remapindex_27)
when _T_3198 :
connect remapVecData[27], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[27]
node _T_3199 = eq(UInt<3>(0h5), remapindex_27)
when _T_3199 :
connect remapVecData[27], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[27]
node _T_3200 = eq(UInt<3>(0h6), remapindex_27)
when _T_3200 :
connect remapVecData[27], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[27]
node _T_3201 = eq(UInt<3>(0h7), remapindex_27)
when _T_3201 :
connect remapVecData[27], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[27]
node _T_3202 = eq(UInt<4>(0h8), remapindex_27)
when _T_3202 :
connect remapVecData[27], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[27]
node _T_3203 = eq(UInt<4>(0h9), remapindex_27)
when _T_3203 :
connect remapVecData[27], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[27]
node _T_3204 = eq(UInt<4>(0ha), remapindex_27)
when _T_3204 :
connect remapVecData[27], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[27]
node _T_3205 = eq(UInt<4>(0hb), remapindex_27)
when _T_3205 :
connect remapVecData[27], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[27]
node _T_3206 = eq(UInt<4>(0hc), remapindex_27)
when _T_3206 :
connect remapVecData[27], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[27]
node _T_3207 = eq(UInt<4>(0hd), remapindex_27)
when _T_3207 :
connect remapVecData[27], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[27]
node _T_3208 = eq(UInt<4>(0he), remapindex_27)
when _T_3208 :
connect remapVecData[27], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[27]
node _T_3209 = eq(UInt<4>(0hf), remapindex_27)
when _T_3209 :
connect remapVecData[27], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[27]
node _T_3210 = eq(UInt<5>(0h10), remapindex_27)
when _T_3210 :
connect remapVecData[27], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[27]
node _T_3211 = eq(UInt<5>(0h11), remapindex_27)
when _T_3211 :
connect remapVecData[27], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[27]
node _T_3212 = eq(UInt<5>(0h12), remapindex_27)
when _T_3212 :
connect remapVecData[27], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[27]
node _T_3213 = eq(UInt<5>(0h13), remapindex_27)
when _T_3213 :
connect remapVecData[27], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[27]
node _T_3214 = eq(UInt<5>(0h14), remapindex_27)
when _T_3214 :
connect remapVecData[27], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[27]
node _T_3215 = eq(UInt<5>(0h15), remapindex_27)
when _T_3215 :
connect remapVecData[27], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[27]
node _T_3216 = eq(UInt<5>(0h16), remapindex_27)
when _T_3216 :
connect remapVecData[27], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[27]
node _T_3217 = eq(UInt<5>(0h17), remapindex_27)
when _T_3217 :
connect remapVecData[27], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[27]
node _T_3218 = eq(UInt<5>(0h18), remapindex_27)
when _T_3218 :
connect remapVecData[27], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[27]
node _T_3219 = eq(UInt<5>(0h19), remapindex_27)
when _T_3219 :
connect remapVecData[27], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[27]
node _T_3220 = eq(UInt<5>(0h1a), remapindex_27)
when _T_3220 :
connect remapVecData[27], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[27]
node _T_3221 = eq(UInt<5>(0h1b), remapindex_27)
when _T_3221 :
connect remapVecData[27], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[27]
node _T_3222 = eq(UInt<5>(0h1c), remapindex_27)
when _T_3222 :
connect remapVecData[27], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[27]
node _T_3223 = eq(UInt<5>(0h1d), remapindex_27)
when _T_3223 :
connect remapVecData[27], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[27]
node _T_3224 = eq(UInt<5>(0h1e), remapindex_27)
when _T_3224 :
connect remapVecData[27], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[27]
node _T_3225 = eq(UInt<5>(0h1f), remapindex_27)
when _T_3225 :
connect remapVecData[27], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[27]
node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index)
node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20))
node _T_3226 = eq(UInt<1>(0h0), remapindex_28)
when _T_3226 :
connect remapVecData[28], Queue64_UInt8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[28]
node _T_3227 = eq(UInt<1>(0h1), remapindex_28)
when _T_3227 :
connect remapVecData[28], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[28]
node _T_3228 = eq(UInt<2>(0h2), remapindex_28)
when _T_3228 :
connect remapVecData[28], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[28]
node _T_3229 = eq(UInt<2>(0h3), remapindex_28)
when _T_3229 :
connect remapVecData[28], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[28]
node _T_3230 = eq(UInt<3>(0h4), remapindex_28)
when _T_3230 :
connect remapVecData[28], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[28]
node _T_3231 = eq(UInt<3>(0h5), remapindex_28)
when _T_3231 :
connect remapVecData[28], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[28]
node _T_3232 = eq(UInt<3>(0h6), remapindex_28)
when _T_3232 :
connect remapVecData[28], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[28]
node _T_3233 = eq(UInt<3>(0h7), remapindex_28)
when _T_3233 :
connect remapVecData[28], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[28]
node _T_3234 = eq(UInt<4>(0h8), remapindex_28)
when _T_3234 :
connect remapVecData[28], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[28]
node _T_3235 = eq(UInt<4>(0h9), remapindex_28)
when _T_3235 :
connect remapVecData[28], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[28]
node _T_3236 = eq(UInt<4>(0ha), remapindex_28)
when _T_3236 :
connect remapVecData[28], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[28]
node _T_3237 = eq(UInt<4>(0hb), remapindex_28)
when _T_3237 :
connect remapVecData[28], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[28]
node _T_3238 = eq(UInt<4>(0hc), remapindex_28)
when _T_3238 :
connect remapVecData[28], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[28]
node _T_3239 = eq(UInt<4>(0hd), remapindex_28)
when _T_3239 :
connect remapVecData[28], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[28]
node _T_3240 = eq(UInt<4>(0he), remapindex_28)
when _T_3240 :
connect remapVecData[28], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[28]
node _T_3241 = eq(UInt<4>(0hf), remapindex_28)
when _T_3241 :
connect remapVecData[28], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[28]
node _T_3242 = eq(UInt<5>(0h10), remapindex_28)
when _T_3242 :
connect remapVecData[28], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[28]
node _T_3243 = eq(UInt<5>(0h11), remapindex_28)
when _T_3243 :
connect remapVecData[28], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[28]
node _T_3244 = eq(UInt<5>(0h12), remapindex_28)
when _T_3244 :
connect remapVecData[28], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[28]
node _T_3245 = eq(UInt<5>(0h13), remapindex_28)
when _T_3245 :
connect remapVecData[28], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[28]
node _T_3246 = eq(UInt<5>(0h14), remapindex_28)
when _T_3246 :
connect remapVecData[28], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[28]
node _T_3247 = eq(UInt<5>(0h15), remapindex_28)
when _T_3247 :
connect remapVecData[28], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[28]
node _T_3248 = eq(UInt<5>(0h16), remapindex_28)
when _T_3248 :
connect remapVecData[28], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[28]
node _T_3249 = eq(UInt<5>(0h17), remapindex_28)
when _T_3249 :
connect remapVecData[28], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[28]
node _T_3250 = eq(UInt<5>(0h18), remapindex_28)
when _T_3250 :
connect remapVecData[28], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[28]
node _T_3251 = eq(UInt<5>(0h19), remapindex_28)
when _T_3251 :
connect remapVecData[28], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[28]
node _T_3252 = eq(UInt<5>(0h1a), remapindex_28)
when _T_3252 :
connect remapVecData[28], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[28]
node _T_3253 = eq(UInt<5>(0h1b), remapindex_28)
when _T_3253 :
connect remapVecData[28], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[28]
node _T_3254 = eq(UInt<5>(0h1c), remapindex_28)
when _T_3254 :
connect remapVecData[28], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[28]
node _T_3255 = eq(UInt<5>(0h1d), remapindex_28)
when _T_3255 :
connect remapVecData[28], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[28]
node _T_3256 = eq(UInt<5>(0h1e), remapindex_28)
when _T_3256 :
connect remapVecData[28], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[28]
node _T_3257 = eq(UInt<5>(0h1f), remapindex_28)
when _T_3257 :
connect remapVecData[28], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[28]
node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index)
node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20))
node _T_3258 = eq(UInt<1>(0h0), remapindex_29)
when _T_3258 :
connect remapVecData[29], Queue64_UInt8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[29]
node _T_3259 = eq(UInt<1>(0h1), remapindex_29)
when _T_3259 :
connect remapVecData[29], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[29]
node _T_3260 = eq(UInt<2>(0h2), remapindex_29)
when _T_3260 :
connect remapVecData[29], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[29]
node _T_3261 = eq(UInt<2>(0h3), remapindex_29)
when _T_3261 :
connect remapVecData[29], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[29]
node _T_3262 = eq(UInt<3>(0h4), remapindex_29)
when _T_3262 :
connect remapVecData[29], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[29]
node _T_3263 = eq(UInt<3>(0h5), remapindex_29)
when _T_3263 :
connect remapVecData[29], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[29]
node _T_3264 = eq(UInt<3>(0h6), remapindex_29)
when _T_3264 :
connect remapVecData[29], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[29]
node _T_3265 = eq(UInt<3>(0h7), remapindex_29)
when _T_3265 :
connect remapVecData[29], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[29]
node _T_3266 = eq(UInt<4>(0h8), remapindex_29)
when _T_3266 :
connect remapVecData[29], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[29]
node _T_3267 = eq(UInt<4>(0h9), remapindex_29)
when _T_3267 :
connect remapVecData[29], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[29]
node _T_3268 = eq(UInt<4>(0ha), remapindex_29)
when _T_3268 :
connect remapVecData[29], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[29]
node _T_3269 = eq(UInt<4>(0hb), remapindex_29)
when _T_3269 :
connect remapVecData[29], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[29]
node _T_3270 = eq(UInt<4>(0hc), remapindex_29)
when _T_3270 :
connect remapVecData[29], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[29]
node _T_3271 = eq(UInt<4>(0hd), remapindex_29)
when _T_3271 :
connect remapVecData[29], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[29]
node _T_3272 = eq(UInt<4>(0he), remapindex_29)
when _T_3272 :
connect remapVecData[29], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[29]
node _T_3273 = eq(UInt<4>(0hf), remapindex_29)
when _T_3273 :
connect remapVecData[29], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[29]
node _T_3274 = eq(UInt<5>(0h10), remapindex_29)
when _T_3274 :
connect remapVecData[29], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[29]
node _T_3275 = eq(UInt<5>(0h11), remapindex_29)
when _T_3275 :
connect remapVecData[29], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[29]
node _T_3276 = eq(UInt<5>(0h12), remapindex_29)
when _T_3276 :
connect remapVecData[29], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[29]
node _T_3277 = eq(UInt<5>(0h13), remapindex_29)
when _T_3277 :
connect remapVecData[29], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[29]
node _T_3278 = eq(UInt<5>(0h14), remapindex_29)
when _T_3278 :
connect remapVecData[29], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[29]
node _T_3279 = eq(UInt<5>(0h15), remapindex_29)
when _T_3279 :
connect remapVecData[29], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[29]
node _T_3280 = eq(UInt<5>(0h16), remapindex_29)
when _T_3280 :
connect remapVecData[29], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[29]
node _T_3281 = eq(UInt<5>(0h17), remapindex_29)
when _T_3281 :
connect remapVecData[29], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[29]
node _T_3282 = eq(UInt<5>(0h18), remapindex_29)
when _T_3282 :
connect remapVecData[29], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[29]
node _T_3283 = eq(UInt<5>(0h19), remapindex_29)
when _T_3283 :
connect remapVecData[29], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[29]
node _T_3284 = eq(UInt<5>(0h1a), remapindex_29)
when _T_3284 :
connect remapVecData[29], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[29]
node _T_3285 = eq(UInt<5>(0h1b), remapindex_29)
when _T_3285 :
connect remapVecData[29], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[29]
node _T_3286 = eq(UInt<5>(0h1c), remapindex_29)
when _T_3286 :
connect remapVecData[29], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[29]
node _T_3287 = eq(UInt<5>(0h1d), remapindex_29)
when _T_3287 :
connect remapVecData[29], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[29]
node _T_3288 = eq(UInt<5>(0h1e), remapindex_29)
when _T_3288 :
connect remapVecData[29], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[29]
node _T_3289 = eq(UInt<5>(0h1f), remapindex_29)
when _T_3289 :
connect remapVecData[29], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[29]
node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index)
node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20))
node _T_3290 = eq(UInt<1>(0h0), remapindex_30)
when _T_3290 :
connect remapVecData[30], Queue64_UInt8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[30]
node _T_3291 = eq(UInt<1>(0h1), remapindex_30)
when _T_3291 :
connect remapVecData[30], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[30]
node _T_3292 = eq(UInt<2>(0h2), remapindex_30)
when _T_3292 :
connect remapVecData[30], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[30]
node _T_3293 = eq(UInt<2>(0h3), remapindex_30)
when _T_3293 :
connect remapVecData[30], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[30]
node _T_3294 = eq(UInt<3>(0h4), remapindex_30)
when _T_3294 :
connect remapVecData[30], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[30]
node _T_3295 = eq(UInt<3>(0h5), remapindex_30)
when _T_3295 :
connect remapVecData[30], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[30]
node _T_3296 = eq(UInt<3>(0h6), remapindex_30)
when _T_3296 :
connect remapVecData[30], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[30]
node _T_3297 = eq(UInt<3>(0h7), remapindex_30)
when _T_3297 :
connect remapVecData[30], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[30]
node _T_3298 = eq(UInt<4>(0h8), remapindex_30)
when _T_3298 :
connect remapVecData[30], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[30]
node _T_3299 = eq(UInt<4>(0h9), remapindex_30)
when _T_3299 :
connect remapVecData[30], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[30]
node _T_3300 = eq(UInt<4>(0ha), remapindex_30)
when _T_3300 :
connect remapVecData[30], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[30]
node _T_3301 = eq(UInt<4>(0hb), remapindex_30)
when _T_3301 :
connect remapVecData[30], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[30]
node _T_3302 = eq(UInt<4>(0hc), remapindex_30)
when _T_3302 :
connect remapVecData[30], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[30]
node _T_3303 = eq(UInt<4>(0hd), remapindex_30)
when _T_3303 :
connect remapVecData[30], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[30]
node _T_3304 = eq(UInt<4>(0he), remapindex_30)
when _T_3304 :
connect remapVecData[30], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[30]
node _T_3305 = eq(UInt<4>(0hf), remapindex_30)
when _T_3305 :
connect remapVecData[30], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[30]
node _T_3306 = eq(UInt<5>(0h10), remapindex_30)
when _T_3306 :
connect remapVecData[30], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[30]
node _T_3307 = eq(UInt<5>(0h11), remapindex_30)
when _T_3307 :
connect remapVecData[30], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[30]
node _T_3308 = eq(UInt<5>(0h12), remapindex_30)
when _T_3308 :
connect remapVecData[30], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[30]
node _T_3309 = eq(UInt<5>(0h13), remapindex_30)
when _T_3309 :
connect remapVecData[30], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[30]
node _T_3310 = eq(UInt<5>(0h14), remapindex_30)
when _T_3310 :
connect remapVecData[30], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[30]
node _T_3311 = eq(UInt<5>(0h15), remapindex_30)
when _T_3311 :
connect remapVecData[30], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[30]
node _T_3312 = eq(UInt<5>(0h16), remapindex_30)
when _T_3312 :
connect remapVecData[30], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[30]
node _T_3313 = eq(UInt<5>(0h17), remapindex_30)
when _T_3313 :
connect remapVecData[30], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[30]
node _T_3314 = eq(UInt<5>(0h18), remapindex_30)
when _T_3314 :
connect remapVecData[30], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[30]
node _T_3315 = eq(UInt<5>(0h19), remapindex_30)
when _T_3315 :
connect remapVecData[30], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[30]
node _T_3316 = eq(UInt<5>(0h1a), remapindex_30)
when _T_3316 :
connect remapVecData[30], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[30]
node _T_3317 = eq(UInt<5>(0h1b), remapindex_30)
when _T_3317 :
connect remapVecData[30], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[30]
node _T_3318 = eq(UInt<5>(0h1c), remapindex_30)
when _T_3318 :
connect remapVecData[30], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[30]
node _T_3319 = eq(UInt<5>(0h1d), remapindex_30)
when _T_3319 :
connect remapVecData[30], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[30]
node _T_3320 = eq(UInt<5>(0h1e), remapindex_30)
when _T_3320 :
connect remapVecData[30], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[30]
node _T_3321 = eq(UInt<5>(0h1f), remapindex_30)
when _T_3321 :
connect remapVecData[30], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[30]
node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index)
node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20))
node _T_3322 = eq(UInt<1>(0h0), remapindex_31)
when _T_3322 :
connect remapVecData[31], Queue64_UInt8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[31]
node _T_3323 = eq(UInt<1>(0h1), remapindex_31)
when _T_3323 :
connect remapVecData[31], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[31]
node _T_3324 = eq(UInt<2>(0h2), remapindex_31)
when _T_3324 :
connect remapVecData[31], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[31]
node _T_3325 = eq(UInt<2>(0h3), remapindex_31)
when _T_3325 :
connect remapVecData[31], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[31]
node _T_3326 = eq(UInt<3>(0h4), remapindex_31)
when _T_3326 :
connect remapVecData[31], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[31]
node _T_3327 = eq(UInt<3>(0h5), remapindex_31)
when _T_3327 :
connect remapVecData[31], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[31]
node _T_3328 = eq(UInt<3>(0h6), remapindex_31)
when _T_3328 :
connect remapVecData[31], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[31]
node _T_3329 = eq(UInt<3>(0h7), remapindex_31)
when _T_3329 :
connect remapVecData[31], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[31]
node _T_3330 = eq(UInt<4>(0h8), remapindex_31)
when _T_3330 :
connect remapVecData[31], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[31]
node _T_3331 = eq(UInt<4>(0h9), remapindex_31)
when _T_3331 :
connect remapVecData[31], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[31]
node _T_3332 = eq(UInt<4>(0ha), remapindex_31)
when _T_3332 :
connect remapVecData[31], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[31]
node _T_3333 = eq(UInt<4>(0hb), remapindex_31)
when _T_3333 :
connect remapVecData[31], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[31]
node _T_3334 = eq(UInt<4>(0hc), remapindex_31)
when _T_3334 :
connect remapVecData[31], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[31]
node _T_3335 = eq(UInt<4>(0hd), remapindex_31)
when _T_3335 :
connect remapVecData[31], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[31]
node _T_3336 = eq(UInt<4>(0he), remapindex_31)
when _T_3336 :
connect remapVecData[31], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[31]
node _T_3337 = eq(UInt<4>(0hf), remapindex_31)
when _T_3337 :
connect remapVecData[31], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[31]
node _T_3338 = eq(UInt<5>(0h10), remapindex_31)
when _T_3338 :
connect remapVecData[31], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[31]
node _T_3339 = eq(UInt<5>(0h11), remapindex_31)
when _T_3339 :
connect remapVecData[31], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[31]
node _T_3340 = eq(UInt<5>(0h12), remapindex_31)
when _T_3340 :
connect remapVecData[31], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[31]
node _T_3341 = eq(UInt<5>(0h13), remapindex_31)
when _T_3341 :
connect remapVecData[31], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[31]
node _T_3342 = eq(UInt<5>(0h14), remapindex_31)
when _T_3342 :
connect remapVecData[31], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[31]
node _T_3343 = eq(UInt<5>(0h15), remapindex_31)
when _T_3343 :
connect remapVecData[31], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[31]
node _T_3344 = eq(UInt<5>(0h16), remapindex_31)
when _T_3344 :
connect remapVecData[31], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[31]
node _T_3345 = eq(UInt<5>(0h17), remapindex_31)
when _T_3345 :
connect remapVecData[31], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[31]
node _T_3346 = eq(UInt<5>(0h18), remapindex_31)
when _T_3346 :
connect remapVecData[31], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[31]
node _T_3347 = eq(UInt<5>(0h19), remapindex_31)
when _T_3347 :
connect remapVecData[31], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[31]
node _T_3348 = eq(UInt<5>(0h1a), remapindex_31)
when _T_3348 :
connect remapVecData[31], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[31]
node _T_3349 = eq(UInt<5>(0h1b), remapindex_31)
when _T_3349 :
connect remapVecData[31], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[31]
node _T_3350 = eq(UInt<5>(0h1c), remapindex_31)
when _T_3350 :
connect remapVecData[31], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[31]
node _T_3351 = eq(UInt<5>(0h1d), remapindex_31)
when _T_3351 :
connect remapVecData[31], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[31]
node _T_3352 = eq(UInt<5>(0h1e), remapindex_31)
when _T_3352 :
connect remapVecData[31], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[31]
node _T_3353 = eq(UInt<5>(0h1f), remapindex_31)
when _T_3353 :
connect remapVecData[31], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[31]
node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0])
node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2])
node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo)
node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4])
node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6])
node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo)
node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo)
node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8])
node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10])
node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo)
node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12])
node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14])
node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo)
node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo)
node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo)
node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16])
node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18])
node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo)
node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20])
node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22])
node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo)
node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo)
node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24])
node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26])
node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo)
node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28])
node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30])
node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo)
node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo)
node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo)
node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo)
connect io.consumer.output_data, _io_consumer_output_data_T
node _buf_last_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _buf_last_T_1 = tail(_buf_last_T, 1)
node buf_last = eq(_buf_last_T_1, buf_info_queue.io.deq.bits.len_bytes)
node _count_valids_T = add(remapVecValids[0], remapVecValids[1])
node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2])
node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3])
node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4])
node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5])
node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6])
node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7])
node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8])
node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9])
node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10])
node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11])
node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12])
node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13])
node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14])
node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15])
node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16])
node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17])
node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18])
node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19])
node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20])
node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21])
node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22])
node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23])
node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24])
node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25])
node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26])
node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27])
node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28])
node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29])
node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30])
node count_valids = add(_count_valids_T_29, remapVecValids[31])
node _unconsumed_bytes_so_far_T = sub(buf_info_queue.io.deq.bits.len_bytes, len_already_consumed)
node unconsumed_bytes_so_far = tail(_unconsumed_bytes_so_far_T, 1)
node _enough_data_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _enough_data_T_1 = eq(count_valids, UInt<6>(0h20))
node _enough_data_T_2 = geq(count_valids, unconsumed_bytes_so_far)
node enough_data = mux(_enough_data_T, _enough_data_T_1, _enough_data_T_2)
node _io_consumer_available_output_bytes_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _io_consumer_available_output_bytes_T_1 = mux(_io_consumer_available_output_bytes_T, UInt<6>(0h20), unconsumed_bytes_so_far)
connect io.consumer.available_output_bytes, _io_consumer_available_output_bytes_T_1
node _io_consumer_output_last_chunk_T = leq(unconsumed_bytes_so_far, UInt<6>(0h20))
connect io.consumer.output_last_chunk, _io_consumer_output_last_chunk_T
node _T_3354 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3355 = and(_T_3354, enough_data)
when _T_3355 :
regreset loginfo_cycles_44 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_88 = add(loginfo_cycles_44, UInt<1>(0h1))
node _loginfo_cycles_T_89 = tail(_loginfo_cycles_T_88, 1)
connect loginfo_cycles_44, _loginfo_cycles_T_89
node _T_3356 = asUInt(reset)
node _T_3357 = eq(_T_3356, UInt<1>(0h0))
when _T_3357 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_44) : printf_88
node _T_3358 = asUInt(reset)
node _T_3359 = eq(_T_3358, UInt<1>(0h0))
when _T_3359 :
printf(clock, UInt<1>(0h1), "MEMLOADER READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_89
node _io_consumer_output_valid_T = and(buf_info_queue.io.deq.valid, enough_data)
connect io.consumer.output_valid, _io_consumer_output_valid_T
node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes)
node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, enough_data)
node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_2)
connect remapVecReadys[0], _remapVecReadys_0_T_3
node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes)
node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, enough_data)
node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_2)
connect remapVecReadys[1], _remapVecReadys_1_T_3
node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes)
node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, enough_data)
node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_2)
connect remapVecReadys[2], _remapVecReadys_2_T_3
node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes)
node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, enough_data)
node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_2)
connect remapVecReadys[3], _remapVecReadys_3_T_3
node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes)
node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, enough_data)
node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_2)
connect remapVecReadys[4], _remapVecReadys_4_T_3
node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes)
node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, enough_data)
node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_2)
connect remapVecReadys[5], _remapVecReadys_5_T_3
node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes)
node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, enough_data)
node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_2)
connect remapVecReadys[6], _remapVecReadys_6_T_3
node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes)
node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, enough_data)
node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_2)
connect remapVecReadys[7], _remapVecReadys_7_T_3
node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes)
node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, enough_data)
node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_2)
connect remapVecReadys[8], _remapVecReadys_8_T_3
node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes)
node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, enough_data)
node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_2)
connect remapVecReadys[9], _remapVecReadys_9_T_3
node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes)
node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, enough_data)
node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_2)
connect remapVecReadys[10], _remapVecReadys_10_T_3
node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes)
node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, enough_data)
node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_2)
connect remapVecReadys[11], _remapVecReadys_11_T_3
node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes)
node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, enough_data)
node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_2)
connect remapVecReadys[12], _remapVecReadys_12_T_3
node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes)
node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, enough_data)
node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_2)
connect remapVecReadys[13], _remapVecReadys_13_T_3
node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes)
node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, enough_data)
node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_2)
connect remapVecReadys[14], _remapVecReadys_14_T_3
node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes)
node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, enough_data)
node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_2)
connect remapVecReadys[15], _remapVecReadys_15_T_3
node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes)
node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, enough_data)
node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_2)
connect remapVecReadys[16], _remapVecReadys_16_T_3
node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes)
node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, enough_data)
node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_2)
connect remapVecReadys[17], _remapVecReadys_17_T_3
node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes)
node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, enough_data)
node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_2)
connect remapVecReadys[18], _remapVecReadys_18_T_3
node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes)
node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, enough_data)
node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_2)
connect remapVecReadys[19], _remapVecReadys_19_T_3
node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes)
node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, enough_data)
node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_2)
connect remapVecReadys[20], _remapVecReadys_20_T_3
node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes)
node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, enough_data)
node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_2)
connect remapVecReadys[21], _remapVecReadys_21_T_3
node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes)
node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, enough_data)
node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_2)
connect remapVecReadys[22], _remapVecReadys_22_T_3
node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes)
node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, enough_data)
node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_2)
connect remapVecReadys[23], _remapVecReadys_23_T_3
node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes)
node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, enough_data)
node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_2)
connect remapVecReadys[24], _remapVecReadys_24_T_3
node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes)
node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, enough_data)
node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_2)
connect remapVecReadys[25], _remapVecReadys_25_T_3
node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes)
node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, enough_data)
node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_2)
connect remapVecReadys[26], _remapVecReadys_26_T_3
node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes)
node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, enough_data)
node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_2)
connect remapVecReadys[27], _remapVecReadys_27_T_3
node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes)
node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, enough_data)
node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_2)
connect remapVecReadys[28], _remapVecReadys_28_T_3
node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes)
node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, enough_data)
node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_2)
connect remapVecReadys[29], _remapVecReadys_29_T_3
node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes)
node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, enough_data)
node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_2)
connect remapVecReadys[30], _remapVecReadys_30_T_3
node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes)
node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, enough_data)
node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_2)
connect remapVecReadys[31], _remapVecReadys_31_T_3
node _T_3360 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3361 = and(_T_3360, enough_data)
when _T_3361 :
node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes)
node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20))
connect read_start_index, _read_start_index_T_1
node _buf_info_queue_io_deq_ready_T = and(io.consumer.output_ready, enough_data)
node _buf_info_queue_io_deq_ready_T_1 = and(_buf_info_queue_io_deq_ready_T, buf_last)
connect buf_info_queue.io.deq.ready, _buf_info_queue_io_deq_ready_T_1
node _T_3362 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3363 = and(_T_3362, enough_data)
when _T_3363 :
when buf_last :
connect len_already_consumed, UInt<1>(0h0)
else :
node _len_already_consumed_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _len_already_consumed_T_1 = tail(_len_already_consumed_T, 1)
connect len_already_consumed, _len_already_consumed_T_1 | module MemLoader_2( // @[MemLoader.scala:15:7]
input clock, // @[MemLoader.scala:15:7]
input reset, // @[MemLoader.scala:15:7]
input io_l2helperUser_req_ready, // @[MemLoader.scala:18:14]
output io_l2helperUser_req_valid, // @[MemLoader.scala:18:14]
output [70:0] io_l2helperUser_req_bits_addr, // @[MemLoader.scala:18:14]
output io_l2helperUser_resp_ready, // @[MemLoader.scala:18:14]
input io_l2helperUser_resp_valid, // @[MemLoader.scala:18:14]
input [255:0] io_l2helperUser_resp_bits_data, // @[MemLoader.scala:18:14]
input io_l2helperUser_no_memops_inflight, // @[MemLoader.scala:18:14]
output io_src_info_ready, // @[MemLoader.scala:18:14]
input io_src_info_valid, // @[MemLoader.scala:18:14]
input [63:0] io_src_info_bits_ip, // @[MemLoader.scala:18:14]
input [63:0] io_src_info_bits_isize, // @[MemLoader.scala:18:14]
input [5:0] io_consumer_user_consumed_bytes, // @[MemLoader.scala:18:14]
output [5:0] io_consumer_available_output_bytes, // @[MemLoader.scala:18:14]
output io_consumer_output_valid, // @[MemLoader.scala:18:14]
input io_consumer_output_ready, // @[MemLoader.scala:18:14]
output [255:0] io_consumer_output_data, // @[MemLoader.scala:18:14]
output io_consumer_output_last_chunk // @[MemLoader.scala:18:14]
);
wire _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_31_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_31_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_30_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_30_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_29_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_29_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_28_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_28_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_27_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_27_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_26_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_26_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_25_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_25_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_24_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_24_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_23_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_23_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_22_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_22_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_21_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_21_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_20_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_20_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_19_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_19_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_18_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_18_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_17_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_17_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_16_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_16_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_15_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_15_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_14_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_14_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_13_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_13_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_12_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_12_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_11_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_11_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_10_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_10_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_9_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_9_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_8_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_8_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_7_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_7_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_6_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_6_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_5_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_5_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_4_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_4_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_3_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_3_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_2_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_2_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_1_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_1_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_io_deq_bits; // @[MemLoader.scala:106:52]
wire _load_info_queue_io_enq_ready; // @[MemLoader.scala:28:31]
wire _load_info_queue_io_deq_valid; // @[MemLoader.scala:28:31]
wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[MemLoader.scala:28:31]
wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[MemLoader.scala:28:31]
wire _buf_info_queue_io_enq_ready; // @[MemLoader.scala:26:30]
wire _buf_info_queue_io_deq_valid; // @[MemLoader.scala:26:30]
wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30]
wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[MemLoader.scala:15:7]
wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[MemLoader.scala:15:7]
wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[MemLoader.scala:15:7]
wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[MemLoader.scala:15:7]
wire io_src_info_valid_0 = io_src_info_valid; // @[MemLoader.scala:15:7]
wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[MemLoader.scala:15:7]
wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[MemLoader.scala:15:7]
wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[MemLoader.scala:15:7]
wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[MemLoader.scala:15:7]
wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[MemLoader.scala:15:7]
wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_req_bits_cmd = 1'h0; // @[MemLoader.scala:15:7]
wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:100:62]
wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _io_consumer_output_valid_T; // @[Misc.scala:26:53]
wire [255:0] _io_consumer_output_data_T; // @[MemLoader.scala:186:33]
wire _io_consumer_output_last_chunk_T; // @[MemLoader.scala:201:61]
wire [70:0] io_l2helperUser_req_bits_addr_0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_req_valid_0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_resp_ready_0; // @[MemLoader.scala:15:7]
wire io_src_info_ready_0; // @[MemLoader.scala:15:7]
wire [5:0] io_consumer_available_output_bytes_0; // @[MemLoader.scala:15:7]
wire io_consumer_output_valid_0; // @[MemLoader.scala:15:7]
wire [255:0] io_consumer_output_data_0; // @[MemLoader.scala:15:7]
wire io_consumer_output_last_chunk_0; // @[MemLoader.scala:15:7]
wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[MemLoader.scala:15:7, :32:51]
wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0} + {1'h0, base_addr_start_index}; // @[MemLoader.scala:15:7, :32:51, :33:35]
wire [64:0] _aligned_loadlen_T; // @[MemLoader.scala:33:35]
assign _aligned_loadlen_T = _GEN; // @[MemLoader.scala:33:35]
wire [64:0] _base_addr_end_index_T; // @[MemLoader.scala:34:39]
assign _base_addr_end_index_T = _GEN; // @[MemLoader.scala:33:35, :34:39]
wire [64:0] _base_addr_end_index_inclusive_T; // @[MemLoader.scala:35:49]
assign _base_addr_end_index_inclusive_T = _GEN; // @[MemLoader.scala:33:35, :35:49]
wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[MemLoader.scala:33:35]
wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[MemLoader.scala:34:39]
wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[MemLoader.scala:34:{39,64}]
wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[MemLoader.scala:35:49]
wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[MemLoader.scala:35:{49,73}]
wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[MemLoader.scala:35:73]
wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[MemLoader.scala:35:{73,80}]
wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[MemLoader.scala:33:35, :36:38]
wire extra_word = |_extra_word_T; // @[MemLoader.scala:36:{38,48}]
wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[MemLoader.scala:15:7, :38:50]
wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[MemLoader.scala:38:{50,58}]
wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[MemLoader.scala:33:35, :39:40]
wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[MemLoader.scala:36:48, :39:{40,48}]
wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[MemLoader.scala:39:48]
wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[MemLoader.scala:39:48, :40:47]
wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[MemLoader.scala:40:47]
reg print_not_done; // @[MemLoader.scala:43:31]
wire _T = io_src_info_valid_0 & print_not_done; // @[MemLoader.scala:15:7, :43:31, :45:27]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] addrinc; // @[MemLoader.scala:74:24]
wire _GEN_0 = addrinc == 64'h0; // @[MemLoader.scala:74:24, :76:57]
wire _load_info_queue_io_enq_bits_start_byte_T; // @[MemLoader.scala:76:57]
assign _load_info_queue_io_enq_bits_start_byte_T = _GEN_0; // @[MemLoader.scala:76:57]
wire _buf_info_queue_io_enq_valid_T; // @[MemLoader.scala:95:53]
assign _buf_info_queue_io_enq_valid_T = _GEN_0; // @[MemLoader.scala:76:57, :95:53]
wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[MemLoader.scala:32:51, :76:{48,57}]
wire _T_44 = addrinc == words_to_load_minus_one; // @[MemLoader.scala:40:47, :74:24, :77:55]
wire _load_info_queue_io_enq_bits_end_byte_T; // @[MemLoader.scala:77:55]
assign _load_info_queue_io_enq_bits_end_byte_T = _T_44; // @[MemLoader.scala:77:55]
wire _io_src_info_ready_T; // @[MemLoader.scala:92:53]
assign _io_src_info_ready_T = _T_44; // @[MemLoader.scala:77:55, :92:53]
wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[MemLoader.scala:35:80, :77:{46,55}]
wire _T_46 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18]
wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53]
assign _buf_info_queue_io_enq_valid_T_1 = _T_46; // @[Misc.scala:26:53, :29:18]
wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
assign _load_info_queue_io_enq_valid_T = _T_46; // @[Misc.scala:26:53, :29:18]
wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[MemLoader.scala:74:24, :83:24]
wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[MemLoader.scala:83:24]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53]
assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[MemLoader.scala:74:24, :100:73]
wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, base_addr_bytes_aligned} + {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[MemLoader.scala:38:58, :100:{62,73}]
assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[MemLoader.scala:100:62]
assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:15:7, :100:62]
wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
reg [5:0] write_start_index; // @[MemLoader.scala:105:34]
wire [7:0] align_shamt = {_load_info_queue_io_deq_bits_start_byte, 3'h0}; // @[MemLoader.scala:28:31, :108:61]
wire [255:0] memresp_bits_shifted = io_l2helperUser_resp_bits_data_0 >> align_shamt; // @[MemLoader.scala:15:7, :108:61, :109:61]
wire [6:0] _idx_T = {1'h0, write_start_index}; // @[MemLoader.scala:105:34, :116:34]
wire [6:0] _GEN_1 = _idx_T % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx = _GEN_1[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_2 = _idx_T_1 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_1 = _GEN_2[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_3 = _idx_T_2 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_2 = _GEN_3[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_4 = _idx_T_3 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_3 = _GEN_4[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_5 = _idx_T_4 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_4 = _GEN_5[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_6 = _idx_T_5 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_5 = _GEN_6[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_7 = _idx_T_6 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_6 = _GEN_7[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_8 = _idx_T_7 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_7 = _GEN_8[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_9 = _idx_T_8 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_8 = _GEN_9[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_10 = _idx_T_9 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_9 = _GEN_10[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_11 = _idx_T_10 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_10 = _GEN_11[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_12 = _idx_T_11 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_11 = _GEN_12[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_13 = _idx_T_12 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_12 = _GEN_13[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_14 = _idx_T_13 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_13 = _GEN_14[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_15 = _idx_T_14 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_14 = _GEN_15[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_16 = _idx_T_15 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_15 = _GEN_16[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_17 = _idx_T_16 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_16 = _GEN_17[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_18 = _idx_T_17 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_17 = _GEN_18[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_19 = _idx_T_18 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_18 = _GEN_19[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_20 = _idx_T_19 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_19 = _GEN_20[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_21 = _idx_T_20 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_20 = _GEN_21[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_22 = _idx_T_21 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_21 = _GEN_22[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_23 = _idx_T_22 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_22 = _GEN_23[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_24 = _idx_T_23 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_23 = _GEN_24[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_25 = _idx_T_24 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_24 = _GEN_25[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_26 = _idx_T_25 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_25 = _GEN_26[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_27 = _idx_T_26 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_26 = _GEN_27[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_28 = _idx_T_27 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_27 = _GEN_28[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_29 = _idx_T_28 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_28 = _GEN_29[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_30 = _idx_T_29 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_29 = _GEN_30[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_31 = _idx_T_30 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_30 = _GEN_31[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_32 = _idx_T_31 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_31 = _GEN_32[5:0]; // @[MemLoader.scala:116:48]
wire [5:0] _len_to_write_T = {1'h0, _load_info_queue_io_deq_bits_end_byte} - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[MemLoader.scala:28:31, :124:60]
wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[MemLoader.scala:124:60]
wire [5:0] len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[MemLoader.scala:124:{60,102}]
wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, len_to_write}; // @[MemLoader.scala:116:34, :124:102, :126:47]
wire [6:0] _GEN_33 = wrap_len_index_wide % 7'h20; // @[MemLoader.scala:126:47, :127:48]
wire [5:0] wrap_len_index_end = _GEN_33[5:0]; // @[MemLoader.scala:127:48]
wire wrapped = |(wrap_len_index_wide[6:5]); // @[MemLoader.scala:126:47, :128:37]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
wire _all_queues_ready_T = _Queue64_UInt8_io_enq_ready & _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire all_queues_ready = _all_queues_ready_T_29 & _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _resp_fire_allqueues_T = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18]
wire _GEN_34 = write_start_index == 6'h0; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T; // @[MemLoader.scala:151:41]
assign _use_this_queue_T = _GEN_34; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_3; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_3 = _GEN_34; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_1 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_4 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_35 = write_start_index < 6'h2; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_6; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_6 = _GEN_35; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_9; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_9 = _GEN_35; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_36 = write_start_index < 6'h3; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_12; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_12 = _GEN_36; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_15; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_15 = _GEN_36; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_37 = wrap_len_index_end > 6'h2; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_13; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_13 = _GEN_37; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_16; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_16 = _GEN_37; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_38 = write_start_index < 6'h4; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_18; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_18 = _GEN_38; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_21; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_21 = _GEN_38; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_39 = write_start_index < 6'h5; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_24; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_24 = _GEN_39; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_27; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_27 = _GEN_39; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_40 = wrap_len_index_end > 6'h4; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_25; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_25 = _GEN_40; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_28; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_28 = _GEN_40; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_41 = write_start_index < 6'h6; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_30; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_30 = _GEN_41; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_33; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_33 = _GEN_41; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_42 = wrap_len_index_end > 6'h5; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_31; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_31 = _GEN_42; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_34; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_34 = _GEN_42; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_43 = write_start_index < 6'h7; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_36; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_36 = _GEN_43; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_39; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_39 = _GEN_43; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_44 = wrap_len_index_end > 6'h6; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_37; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_37 = _GEN_44; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_40; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_40 = _GEN_44; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_45 = write_start_index < 6'h8; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_42; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_42 = _GEN_45; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_45; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_45 = _GEN_45; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_46 = write_start_index < 6'h9; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_48; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_48 = _GEN_46; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_51; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_51 = _GEN_46; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_47 = wrap_len_index_end > 6'h8; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_49; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_49 = _GEN_47; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_52; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_52 = _GEN_47; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_48 = write_start_index < 6'hA; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_54; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_54 = _GEN_48; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_57; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_57 = _GEN_48; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_49 = wrap_len_index_end > 6'h9; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_55; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_55 = _GEN_49; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_58; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_58 = _GEN_49; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_50 = write_start_index < 6'hB; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_60; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_60 = _GEN_50; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_63; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_63 = _GEN_50; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_51 = wrap_len_index_end > 6'hA; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_61; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_61 = _GEN_51; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_64; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_64 = _GEN_51; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_52 = write_start_index < 6'hC; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_66; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_66 = _GEN_52; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_69; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_69 = _GEN_52; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_53 = wrap_len_index_end > 6'hB; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_67; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_67 = _GEN_53; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_70; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_70 = _GEN_53; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_54 = write_start_index < 6'hD; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_72; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_72 = _GEN_54; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_75; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_75 = _GEN_54; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_55 = wrap_len_index_end > 6'hC; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_73; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_73 = _GEN_55; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_76; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_76 = _GEN_55; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_56 = write_start_index < 6'hE; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_78; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_78 = _GEN_56; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_81; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_81 = _GEN_56; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_57 = wrap_len_index_end > 6'hD; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_79; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_79 = _GEN_57; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_82; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_82 = _GEN_57; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_58 = write_start_index < 6'hF; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_84; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_84 = _GEN_58; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_87; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_87 = _GEN_58; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_59 = wrap_len_index_end > 6'hE; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_85; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_85 = _GEN_59; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_88; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_88 = _GEN_59; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_60 = write_start_index < 6'h10; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_90; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_90 = _GEN_60; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_93; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_93 = _GEN_60; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_61 = write_start_index < 6'h11; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_96; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_96 = _GEN_61; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_99; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_99 = _GEN_61; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_62 = wrap_len_index_end > 6'h10; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_97; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_97 = _GEN_62; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_100; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_100 = _GEN_62; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_63 = write_start_index < 6'h12; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_102; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_102 = _GEN_63; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_105; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_105 = _GEN_63; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_64 = wrap_len_index_end > 6'h11; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_103; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_103 = _GEN_64; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_106; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_106 = _GEN_64; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_65 = write_start_index < 6'h13; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_108; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_108 = _GEN_65; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_111; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_111 = _GEN_65; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_66 = wrap_len_index_end > 6'h12; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_109; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_109 = _GEN_66; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_112; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_112 = _GEN_66; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_67 = write_start_index < 6'h14; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_114; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_114 = _GEN_67; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_117; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_117 = _GEN_67; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_68 = wrap_len_index_end > 6'h13; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_115; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_115 = _GEN_68; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_118; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_118 = _GEN_68; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_69 = write_start_index < 6'h15; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_120; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_120 = _GEN_69; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_123; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_123 = _GEN_69; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_70 = wrap_len_index_end > 6'h14; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_121; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_121 = _GEN_70; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_124; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_124 = _GEN_70; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_71 = write_start_index < 6'h16; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_126; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_126 = _GEN_71; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_129; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_129 = _GEN_71; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_72 = wrap_len_index_end > 6'h15; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_127; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_127 = _GEN_72; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_130; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_130 = _GEN_72; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_73 = write_start_index < 6'h17; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_132; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_132 = _GEN_73; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_135; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_135 = _GEN_73; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_74 = wrap_len_index_end > 6'h16; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_133; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_133 = _GEN_74; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_136; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_136 = _GEN_74; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_75 = write_start_index < 6'h18; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_138; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_138 = _GEN_75; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_141; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_141 = _GEN_75; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_76 = wrap_len_index_end > 6'h17; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_139; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_139 = _GEN_76; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_142; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_142 = _GEN_76; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_77 = write_start_index < 6'h19; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_144; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_144 = _GEN_77; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_147; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_147 = _GEN_77; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_78 = wrap_len_index_end > 6'h18; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_145; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_145 = _GEN_78; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_148; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_148 = _GEN_78; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_79 = write_start_index < 6'h1A; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_150; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_150 = _GEN_79; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_153; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_153 = _GEN_79; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_80 = wrap_len_index_end > 6'h19; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_151; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_151 = _GEN_80; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_154; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_154 = _GEN_80; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_81 = write_start_index < 6'h1B; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_156; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_156 = _GEN_81; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_159; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_159 = _GEN_81; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_82 = wrap_len_index_end > 6'h1A; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_157; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_157 = _GEN_82; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_160; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_160 = _GEN_82; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_83 = write_start_index < 6'h1C; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_162; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_162 = _GEN_83; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_165; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_165 = _GEN_83; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_84 = wrap_len_index_end > 6'h1B; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_163; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_163 = _GEN_84; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_166; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_166 = _GEN_84; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_85 = write_start_index < 6'h1D; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_168; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_168 = _GEN_85; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_171; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_171 = _GEN_85; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_86 = wrap_len_index_end > 6'h1C; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_169; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_169 = _GEN_86; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_172; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_172 = _GEN_86; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_87 = write_start_index < 6'h1E; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_174; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_174 = _GEN_87; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_177; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_177 = _GEN_87; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_88 = wrap_len_index_end > 6'h1D; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_175; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_175 = _GEN_88; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_178; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_178 = _GEN_88; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_89 = write_start_index < 6'h1F; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_180; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_180 = _GEN_89; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_183; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_183 = _GEN_89; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_90 = wrap_len_index_end > 6'h1E; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_181; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_181 = _GEN_90; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_184; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_184 = _GEN_90; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41, :152:41]
wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38]
reg [5:0] read_start_index; // @[MemLoader.scala:163:33]
reg [63:0] len_already_consumed; // @[MemLoader.scala:164:37]
wire [7:0] remapVecData_0; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_1; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_2; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_3; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_4; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_5; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_6; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_7; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_8; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_9; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_10; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_11; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_12; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_13; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_14; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_15; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_16; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_17; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_18; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_19; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_20; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_21; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_22; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_23; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_24; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_25; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_26; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_27; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_28; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_29; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_30; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_31; // @[MemLoader.scala:166:26]
wire remapVecValids_0; // @[MemLoader.scala:167:28]
wire remapVecValids_1; // @[MemLoader.scala:167:28]
wire remapVecValids_2; // @[MemLoader.scala:167:28]
wire remapVecValids_3; // @[MemLoader.scala:167:28]
wire remapVecValids_4; // @[MemLoader.scala:167:28]
wire remapVecValids_5; // @[MemLoader.scala:167:28]
wire remapVecValids_6; // @[MemLoader.scala:167:28]
wire remapVecValids_7; // @[MemLoader.scala:167:28]
wire remapVecValids_8; // @[MemLoader.scala:167:28]
wire remapVecValids_9; // @[MemLoader.scala:167:28]
wire remapVecValids_10; // @[MemLoader.scala:167:28]
wire remapVecValids_11; // @[MemLoader.scala:167:28]
wire remapVecValids_12; // @[MemLoader.scala:167:28]
wire remapVecValids_13; // @[MemLoader.scala:167:28]
wire remapVecValids_14; // @[MemLoader.scala:167:28]
wire remapVecValids_15; // @[MemLoader.scala:167:28]
wire remapVecValids_16; // @[MemLoader.scala:167:28]
wire remapVecValids_17; // @[MemLoader.scala:167:28]
wire remapVecValids_18; // @[MemLoader.scala:167:28]
wire remapVecValids_19; // @[MemLoader.scala:167:28]
wire remapVecValids_20; // @[MemLoader.scala:167:28]
wire remapVecValids_21; // @[MemLoader.scala:167:28]
wire remapVecValids_22; // @[MemLoader.scala:167:28]
wire remapVecValids_23; // @[MemLoader.scala:167:28]
wire remapVecValids_24; // @[MemLoader.scala:167:28]
wire remapVecValids_25; // @[MemLoader.scala:167:28]
wire remapVecValids_26; // @[MemLoader.scala:167:28]
wire remapVecValids_27; // @[MemLoader.scala:167:28]
wire remapVecValids_28; // @[MemLoader.scala:167:28]
wire remapVecValids_29; // @[MemLoader.scala:167:28]
wire remapVecValids_30; // @[MemLoader.scala:167:28]
wire remapVecValids_31; // @[MemLoader.scala:167:28]
wire _remapVecReadys_0_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_1_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_2_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_3_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_4_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_5_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_6_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_7_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_8_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_9_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_10_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_11_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_12_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_13_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_14_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_15_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_16_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_17_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_18_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_19_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_20_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_21_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_22_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_23_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_24_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_25_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_26_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_27_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_28_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_29_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_30_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_31_T_3; // @[MemLoader.scala:217:78]
wire remapVecReadys_0; // @[MemLoader.scala:168:28]
wire remapVecReadys_1; // @[MemLoader.scala:168:28]
wire remapVecReadys_2; // @[MemLoader.scala:168:28]
wire remapVecReadys_3; // @[MemLoader.scala:168:28]
wire remapVecReadys_4; // @[MemLoader.scala:168:28]
wire remapVecReadys_5; // @[MemLoader.scala:168:28]
wire remapVecReadys_6; // @[MemLoader.scala:168:28]
wire remapVecReadys_7; // @[MemLoader.scala:168:28]
wire remapVecReadys_8; // @[MemLoader.scala:168:28]
wire remapVecReadys_9; // @[MemLoader.scala:168:28]
wire remapVecReadys_10; // @[MemLoader.scala:168:28]
wire remapVecReadys_11; // @[MemLoader.scala:168:28]
wire remapVecReadys_12; // @[MemLoader.scala:168:28]
wire remapVecReadys_13; // @[MemLoader.scala:168:28]
wire remapVecReadys_14; // @[MemLoader.scala:168:28]
wire remapVecReadys_15; // @[MemLoader.scala:168:28]
wire remapVecReadys_16; // @[MemLoader.scala:168:28]
wire remapVecReadys_17; // @[MemLoader.scala:168:28]
wire remapVecReadys_18; // @[MemLoader.scala:168:28]
wire remapVecReadys_19; // @[MemLoader.scala:168:28]
wire remapVecReadys_20; // @[MemLoader.scala:168:28]
wire remapVecReadys_21; // @[MemLoader.scala:168:28]
wire remapVecReadys_22; // @[MemLoader.scala:168:28]
wire remapVecReadys_23; // @[MemLoader.scala:168:28]
wire remapVecReadys_24; // @[MemLoader.scala:168:28]
wire remapVecReadys_25; // @[MemLoader.scala:168:28]
wire remapVecReadys_26; // @[MemLoader.scala:168:28]
wire remapVecReadys_27; // @[MemLoader.scala:168:28]
wire remapVecReadys_28; // @[MemLoader.scala:168:28]
wire remapVecReadys_29; // @[MemLoader.scala:168:28]
wire remapVecReadys_30; // @[MemLoader.scala:168:28]
wire remapVecReadys_31; // @[MemLoader.scala:168:28]
wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[MemLoader.scala:163:33, :177:33]
wire [6:0] _GEN_91 = _remapindex_T % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex = _GEN_91[5:0]; // @[MemLoader.scala:177:54]
wire _T_2330 = remapindex == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2331 = remapindex == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2332 = remapindex == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2333 = remapindex == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2334 = remapindex == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2335 = remapindex == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2336 = remapindex == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2337 = remapindex == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2338 = remapindex == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2339 = remapindex == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2340 = remapindex == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2341 = remapindex == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2342 = remapindex == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2343 = remapindex == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2344 = remapindex == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2345 = remapindex == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2346 = remapindex == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2347 = remapindex == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2348 = remapindex == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2349 = remapindex == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2350 = remapindex == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2351 = remapindex == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2352 = remapindex == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2353 = remapindex == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2354 = remapindex == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2355 = remapindex == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2356 = remapindex == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2357 = remapindex == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2358 = remapindex == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2359 = remapindex == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2360 = remapindex == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2361 = remapindex == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_bits : _T_2360 ? _Queue64_UInt8_30_io_deq_bits : _T_2359 ? _Queue64_UInt8_29_io_deq_bits : _T_2358 ? _Queue64_UInt8_28_io_deq_bits : _T_2357 ? _Queue64_UInt8_27_io_deq_bits : _T_2356 ? _Queue64_UInt8_26_io_deq_bits : _T_2355 ? _Queue64_UInt8_25_io_deq_bits : _T_2354 ? _Queue64_UInt8_24_io_deq_bits : _T_2353 ? _Queue64_UInt8_23_io_deq_bits : _T_2352 ? _Queue64_UInt8_22_io_deq_bits : _T_2351 ? _Queue64_UInt8_21_io_deq_bits : _T_2350 ? _Queue64_UInt8_20_io_deq_bits : _T_2349 ? _Queue64_UInt8_19_io_deq_bits : _T_2348 ? _Queue64_UInt8_18_io_deq_bits : _T_2347 ? _Queue64_UInt8_17_io_deq_bits : _T_2346 ? _Queue64_UInt8_16_io_deq_bits : _T_2345 ? _Queue64_UInt8_15_io_deq_bits : _T_2344 ? _Queue64_UInt8_14_io_deq_bits : _T_2343 ? _Queue64_UInt8_13_io_deq_bits : _T_2342 ? _Queue64_UInt8_12_io_deq_bits : _T_2341 ? _Queue64_UInt8_11_io_deq_bits : _T_2340 ? _Queue64_UInt8_10_io_deq_bits : _T_2339 ? _Queue64_UInt8_9_io_deq_bits : _T_2338 ? _Queue64_UInt8_8_io_deq_bits : _T_2337 ? _Queue64_UInt8_7_io_deq_bits : _T_2336 ? _Queue64_UInt8_6_io_deq_bits : _T_2335 ? _Queue64_UInt8_5_io_deq_bits : _T_2334 ? _Queue64_UInt8_4_io_deq_bits : _T_2333 ? _Queue64_UInt8_3_io_deq_bits : _T_2332 ? _Queue64_UInt8_2_io_deq_bits : _T_2331 ? _Queue64_UInt8_1_io_deq_bits : _T_2330 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_valid : _T_2360 ? _Queue64_UInt8_30_io_deq_valid : _T_2359 ? _Queue64_UInt8_29_io_deq_valid : _T_2358 ? _Queue64_UInt8_28_io_deq_valid : _T_2357 ? _Queue64_UInt8_27_io_deq_valid : _T_2356 ? _Queue64_UInt8_26_io_deq_valid : _T_2355 ? _Queue64_UInt8_25_io_deq_valid : _T_2354 ? _Queue64_UInt8_24_io_deq_valid : _T_2353 ? _Queue64_UInt8_23_io_deq_valid : _T_2352 ? _Queue64_UInt8_22_io_deq_valid : _T_2351 ? _Queue64_UInt8_21_io_deq_valid : _T_2350 ? _Queue64_UInt8_20_io_deq_valid : _T_2349 ? _Queue64_UInt8_19_io_deq_valid : _T_2348 ? _Queue64_UInt8_18_io_deq_valid : _T_2347 ? _Queue64_UInt8_17_io_deq_valid : _T_2346 ? _Queue64_UInt8_16_io_deq_valid : _T_2345 ? _Queue64_UInt8_15_io_deq_valid : _T_2344 ? _Queue64_UInt8_14_io_deq_valid : _T_2343 ? _Queue64_UInt8_13_io_deq_valid : _T_2342 ? _Queue64_UInt8_12_io_deq_valid : _T_2341 ? _Queue64_UInt8_11_io_deq_valid : _T_2340 ? _Queue64_UInt8_10_io_deq_valid : _T_2339 ? _Queue64_UInt8_9_io_deq_valid : _T_2338 ? _Queue64_UInt8_8_io_deq_valid : _T_2337 ? _Queue64_UInt8_7_io_deq_valid : _T_2336 ? _Queue64_UInt8_6_io_deq_valid : _T_2335 ? _Queue64_UInt8_5_io_deq_valid : _T_2334 ? _Queue64_UInt8_4_io_deq_valid : _T_2333 ? _Queue64_UInt8_3_io_deq_valid : _T_2332 ? _Queue64_UInt8_2_io_deq_valid : _T_2331 ? _Queue64_UInt8_1_io_deq_valid : _T_2330 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_92 = _remapindex_T_1 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_1 = _GEN_92[5:0]; // @[MemLoader.scala:177:54]
wire _T_2362 = remapindex_1 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2363 = remapindex_1 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2364 = remapindex_1 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2365 = remapindex_1 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2366 = remapindex_1 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2367 = remapindex_1 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2368 = remapindex_1 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2369 = remapindex_1 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2370 = remapindex_1 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2371 = remapindex_1 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2372 = remapindex_1 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2373 = remapindex_1 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2374 = remapindex_1 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2375 = remapindex_1 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2376 = remapindex_1 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2377 = remapindex_1 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2378 = remapindex_1 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2379 = remapindex_1 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2380 = remapindex_1 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2381 = remapindex_1 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2382 = remapindex_1 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2383 = remapindex_1 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2384 = remapindex_1 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2385 = remapindex_1 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2386 = remapindex_1 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2387 = remapindex_1 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2388 = remapindex_1 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2389 = remapindex_1 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2390 = remapindex_1 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2391 = remapindex_1 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2392 = remapindex_1 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2393 = remapindex_1 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_bits : _T_2392 ? _Queue64_UInt8_30_io_deq_bits : _T_2391 ? _Queue64_UInt8_29_io_deq_bits : _T_2390 ? _Queue64_UInt8_28_io_deq_bits : _T_2389 ? _Queue64_UInt8_27_io_deq_bits : _T_2388 ? _Queue64_UInt8_26_io_deq_bits : _T_2387 ? _Queue64_UInt8_25_io_deq_bits : _T_2386 ? _Queue64_UInt8_24_io_deq_bits : _T_2385 ? _Queue64_UInt8_23_io_deq_bits : _T_2384 ? _Queue64_UInt8_22_io_deq_bits : _T_2383 ? _Queue64_UInt8_21_io_deq_bits : _T_2382 ? _Queue64_UInt8_20_io_deq_bits : _T_2381 ? _Queue64_UInt8_19_io_deq_bits : _T_2380 ? _Queue64_UInt8_18_io_deq_bits : _T_2379 ? _Queue64_UInt8_17_io_deq_bits : _T_2378 ? _Queue64_UInt8_16_io_deq_bits : _T_2377 ? _Queue64_UInt8_15_io_deq_bits : _T_2376 ? _Queue64_UInt8_14_io_deq_bits : _T_2375 ? _Queue64_UInt8_13_io_deq_bits : _T_2374 ? _Queue64_UInt8_12_io_deq_bits : _T_2373 ? _Queue64_UInt8_11_io_deq_bits : _T_2372 ? _Queue64_UInt8_10_io_deq_bits : _T_2371 ? _Queue64_UInt8_9_io_deq_bits : _T_2370 ? _Queue64_UInt8_8_io_deq_bits : _T_2369 ? _Queue64_UInt8_7_io_deq_bits : _T_2368 ? _Queue64_UInt8_6_io_deq_bits : _T_2367 ? _Queue64_UInt8_5_io_deq_bits : _T_2366 ? _Queue64_UInt8_4_io_deq_bits : _T_2365 ? _Queue64_UInt8_3_io_deq_bits : _T_2364 ? _Queue64_UInt8_2_io_deq_bits : _T_2363 ? _Queue64_UInt8_1_io_deq_bits : _T_2362 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_valid : _T_2392 ? _Queue64_UInt8_30_io_deq_valid : _T_2391 ? _Queue64_UInt8_29_io_deq_valid : _T_2390 ? _Queue64_UInt8_28_io_deq_valid : _T_2389 ? _Queue64_UInt8_27_io_deq_valid : _T_2388 ? _Queue64_UInt8_26_io_deq_valid : _T_2387 ? _Queue64_UInt8_25_io_deq_valid : _T_2386 ? _Queue64_UInt8_24_io_deq_valid : _T_2385 ? _Queue64_UInt8_23_io_deq_valid : _T_2384 ? _Queue64_UInt8_22_io_deq_valid : _T_2383 ? _Queue64_UInt8_21_io_deq_valid : _T_2382 ? _Queue64_UInt8_20_io_deq_valid : _T_2381 ? _Queue64_UInt8_19_io_deq_valid : _T_2380 ? _Queue64_UInt8_18_io_deq_valid : _T_2379 ? _Queue64_UInt8_17_io_deq_valid : _T_2378 ? _Queue64_UInt8_16_io_deq_valid : _T_2377 ? _Queue64_UInt8_15_io_deq_valid : _T_2376 ? _Queue64_UInt8_14_io_deq_valid : _T_2375 ? _Queue64_UInt8_13_io_deq_valid : _T_2374 ? _Queue64_UInt8_12_io_deq_valid : _T_2373 ? _Queue64_UInt8_11_io_deq_valid : _T_2372 ? _Queue64_UInt8_10_io_deq_valid : _T_2371 ? _Queue64_UInt8_9_io_deq_valid : _T_2370 ? _Queue64_UInt8_8_io_deq_valid : _T_2369 ? _Queue64_UInt8_7_io_deq_valid : _T_2368 ? _Queue64_UInt8_6_io_deq_valid : _T_2367 ? _Queue64_UInt8_5_io_deq_valid : _T_2366 ? _Queue64_UInt8_4_io_deq_valid : _T_2365 ? _Queue64_UInt8_3_io_deq_valid : _T_2364 ? _Queue64_UInt8_2_io_deq_valid : _T_2363 ? _Queue64_UInt8_1_io_deq_valid : _T_2362 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_93 = _remapindex_T_2 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_2 = _GEN_93[5:0]; // @[MemLoader.scala:177:54]
wire _T_2394 = remapindex_2 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2395 = remapindex_2 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2396 = remapindex_2 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2397 = remapindex_2 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2398 = remapindex_2 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2399 = remapindex_2 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2400 = remapindex_2 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2401 = remapindex_2 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2402 = remapindex_2 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2403 = remapindex_2 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2404 = remapindex_2 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2405 = remapindex_2 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2406 = remapindex_2 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2407 = remapindex_2 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2408 = remapindex_2 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2409 = remapindex_2 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2410 = remapindex_2 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2411 = remapindex_2 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2412 = remapindex_2 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2413 = remapindex_2 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2414 = remapindex_2 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2415 = remapindex_2 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2416 = remapindex_2 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2417 = remapindex_2 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2418 = remapindex_2 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2419 = remapindex_2 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2420 = remapindex_2 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2421 = remapindex_2 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2422 = remapindex_2 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2423 = remapindex_2 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2424 = remapindex_2 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2425 = remapindex_2 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_bits : _T_2424 ? _Queue64_UInt8_30_io_deq_bits : _T_2423 ? _Queue64_UInt8_29_io_deq_bits : _T_2422 ? _Queue64_UInt8_28_io_deq_bits : _T_2421 ? _Queue64_UInt8_27_io_deq_bits : _T_2420 ? _Queue64_UInt8_26_io_deq_bits : _T_2419 ? _Queue64_UInt8_25_io_deq_bits : _T_2418 ? _Queue64_UInt8_24_io_deq_bits : _T_2417 ? _Queue64_UInt8_23_io_deq_bits : _T_2416 ? _Queue64_UInt8_22_io_deq_bits : _T_2415 ? _Queue64_UInt8_21_io_deq_bits : _T_2414 ? _Queue64_UInt8_20_io_deq_bits : _T_2413 ? _Queue64_UInt8_19_io_deq_bits : _T_2412 ? _Queue64_UInt8_18_io_deq_bits : _T_2411 ? _Queue64_UInt8_17_io_deq_bits : _T_2410 ? _Queue64_UInt8_16_io_deq_bits : _T_2409 ? _Queue64_UInt8_15_io_deq_bits : _T_2408 ? _Queue64_UInt8_14_io_deq_bits : _T_2407 ? _Queue64_UInt8_13_io_deq_bits : _T_2406 ? _Queue64_UInt8_12_io_deq_bits : _T_2405 ? _Queue64_UInt8_11_io_deq_bits : _T_2404 ? _Queue64_UInt8_10_io_deq_bits : _T_2403 ? _Queue64_UInt8_9_io_deq_bits : _T_2402 ? _Queue64_UInt8_8_io_deq_bits : _T_2401 ? _Queue64_UInt8_7_io_deq_bits : _T_2400 ? _Queue64_UInt8_6_io_deq_bits : _T_2399 ? _Queue64_UInt8_5_io_deq_bits : _T_2398 ? _Queue64_UInt8_4_io_deq_bits : _T_2397 ? _Queue64_UInt8_3_io_deq_bits : _T_2396 ? _Queue64_UInt8_2_io_deq_bits : _T_2395 ? _Queue64_UInt8_1_io_deq_bits : _T_2394 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_valid : _T_2424 ? _Queue64_UInt8_30_io_deq_valid : _T_2423 ? _Queue64_UInt8_29_io_deq_valid : _T_2422 ? _Queue64_UInt8_28_io_deq_valid : _T_2421 ? _Queue64_UInt8_27_io_deq_valid : _T_2420 ? _Queue64_UInt8_26_io_deq_valid : _T_2419 ? _Queue64_UInt8_25_io_deq_valid : _T_2418 ? _Queue64_UInt8_24_io_deq_valid : _T_2417 ? _Queue64_UInt8_23_io_deq_valid : _T_2416 ? _Queue64_UInt8_22_io_deq_valid : _T_2415 ? _Queue64_UInt8_21_io_deq_valid : _T_2414 ? _Queue64_UInt8_20_io_deq_valid : _T_2413 ? _Queue64_UInt8_19_io_deq_valid : _T_2412 ? _Queue64_UInt8_18_io_deq_valid : _T_2411 ? _Queue64_UInt8_17_io_deq_valid : _T_2410 ? _Queue64_UInt8_16_io_deq_valid : _T_2409 ? _Queue64_UInt8_15_io_deq_valid : _T_2408 ? _Queue64_UInt8_14_io_deq_valid : _T_2407 ? _Queue64_UInt8_13_io_deq_valid : _T_2406 ? _Queue64_UInt8_12_io_deq_valid : _T_2405 ? _Queue64_UInt8_11_io_deq_valid : _T_2404 ? _Queue64_UInt8_10_io_deq_valid : _T_2403 ? _Queue64_UInt8_9_io_deq_valid : _T_2402 ? _Queue64_UInt8_8_io_deq_valid : _T_2401 ? _Queue64_UInt8_7_io_deq_valid : _T_2400 ? _Queue64_UInt8_6_io_deq_valid : _T_2399 ? _Queue64_UInt8_5_io_deq_valid : _T_2398 ? _Queue64_UInt8_4_io_deq_valid : _T_2397 ? _Queue64_UInt8_3_io_deq_valid : _T_2396 ? _Queue64_UInt8_2_io_deq_valid : _T_2395 ? _Queue64_UInt8_1_io_deq_valid : _T_2394 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_94 = _remapindex_T_3 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_3 = _GEN_94[5:0]; // @[MemLoader.scala:177:54]
wire _T_2426 = remapindex_3 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2427 = remapindex_3 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2428 = remapindex_3 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2429 = remapindex_3 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2430 = remapindex_3 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2431 = remapindex_3 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2432 = remapindex_3 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2433 = remapindex_3 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2434 = remapindex_3 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2435 = remapindex_3 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2436 = remapindex_3 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2437 = remapindex_3 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2438 = remapindex_3 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2439 = remapindex_3 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2440 = remapindex_3 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2441 = remapindex_3 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2442 = remapindex_3 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2443 = remapindex_3 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2444 = remapindex_3 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2445 = remapindex_3 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2446 = remapindex_3 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2447 = remapindex_3 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2448 = remapindex_3 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2449 = remapindex_3 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2450 = remapindex_3 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2451 = remapindex_3 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2452 = remapindex_3 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2453 = remapindex_3 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2454 = remapindex_3 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2455 = remapindex_3 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2456 = remapindex_3 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2457 = remapindex_3 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_bits : _T_2456 ? _Queue64_UInt8_30_io_deq_bits : _T_2455 ? _Queue64_UInt8_29_io_deq_bits : _T_2454 ? _Queue64_UInt8_28_io_deq_bits : _T_2453 ? _Queue64_UInt8_27_io_deq_bits : _T_2452 ? _Queue64_UInt8_26_io_deq_bits : _T_2451 ? _Queue64_UInt8_25_io_deq_bits : _T_2450 ? _Queue64_UInt8_24_io_deq_bits : _T_2449 ? _Queue64_UInt8_23_io_deq_bits : _T_2448 ? _Queue64_UInt8_22_io_deq_bits : _T_2447 ? _Queue64_UInt8_21_io_deq_bits : _T_2446 ? _Queue64_UInt8_20_io_deq_bits : _T_2445 ? _Queue64_UInt8_19_io_deq_bits : _T_2444 ? _Queue64_UInt8_18_io_deq_bits : _T_2443 ? _Queue64_UInt8_17_io_deq_bits : _T_2442 ? _Queue64_UInt8_16_io_deq_bits : _T_2441 ? _Queue64_UInt8_15_io_deq_bits : _T_2440 ? _Queue64_UInt8_14_io_deq_bits : _T_2439 ? _Queue64_UInt8_13_io_deq_bits : _T_2438 ? _Queue64_UInt8_12_io_deq_bits : _T_2437 ? _Queue64_UInt8_11_io_deq_bits : _T_2436 ? _Queue64_UInt8_10_io_deq_bits : _T_2435 ? _Queue64_UInt8_9_io_deq_bits : _T_2434 ? _Queue64_UInt8_8_io_deq_bits : _T_2433 ? _Queue64_UInt8_7_io_deq_bits : _T_2432 ? _Queue64_UInt8_6_io_deq_bits : _T_2431 ? _Queue64_UInt8_5_io_deq_bits : _T_2430 ? _Queue64_UInt8_4_io_deq_bits : _T_2429 ? _Queue64_UInt8_3_io_deq_bits : _T_2428 ? _Queue64_UInt8_2_io_deq_bits : _T_2427 ? _Queue64_UInt8_1_io_deq_bits : _T_2426 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_valid : _T_2456 ? _Queue64_UInt8_30_io_deq_valid : _T_2455 ? _Queue64_UInt8_29_io_deq_valid : _T_2454 ? _Queue64_UInt8_28_io_deq_valid : _T_2453 ? _Queue64_UInt8_27_io_deq_valid : _T_2452 ? _Queue64_UInt8_26_io_deq_valid : _T_2451 ? _Queue64_UInt8_25_io_deq_valid : _T_2450 ? _Queue64_UInt8_24_io_deq_valid : _T_2449 ? _Queue64_UInt8_23_io_deq_valid : _T_2448 ? _Queue64_UInt8_22_io_deq_valid : _T_2447 ? _Queue64_UInt8_21_io_deq_valid : _T_2446 ? _Queue64_UInt8_20_io_deq_valid : _T_2445 ? _Queue64_UInt8_19_io_deq_valid : _T_2444 ? _Queue64_UInt8_18_io_deq_valid : _T_2443 ? _Queue64_UInt8_17_io_deq_valid : _T_2442 ? _Queue64_UInt8_16_io_deq_valid : _T_2441 ? _Queue64_UInt8_15_io_deq_valid : _T_2440 ? _Queue64_UInt8_14_io_deq_valid : _T_2439 ? _Queue64_UInt8_13_io_deq_valid : _T_2438 ? _Queue64_UInt8_12_io_deq_valid : _T_2437 ? _Queue64_UInt8_11_io_deq_valid : _T_2436 ? _Queue64_UInt8_10_io_deq_valid : _T_2435 ? _Queue64_UInt8_9_io_deq_valid : _T_2434 ? _Queue64_UInt8_8_io_deq_valid : _T_2433 ? _Queue64_UInt8_7_io_deq_valid : _T_2432 ? _Queue64_UInt8_6_io_deq_valid : _T_2431 ? _Queue64_UInt8_5_io_deq_valid : _T_2430 ? _Queue64_UInt8_4_io_deq_valid : _T_2429 ? _Queue64_UInt8_3_io_deq_valid : _T_2428 ? _Queue64_UInt8_2_io_deq_valid : _T_2427 ? _Queue64_UInt8_1_io_deq_valid : _T_2426 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_95 = _remapindex_T_4 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_4 = _GEN_95[5:0]; // @[MemLoader.scala:177:54]
wire _T_2458 = remapindex_4 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2459 = remapindex_4 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2460 = remapindex_4 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2461 = remapindex_4 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2462 = remapindex_4 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2463 = remapindex_4 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2464 = remapindex_4 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2465 = remapindex_4 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2466 = remapindex_4 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2467 = remapindex_4 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2468 = remapindex_4 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2469 = remapindex_4 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2470 = remapindex_4 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2471 = remapindex_4 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2472 = remapindex_4 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2473 = remapindex_4 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2474 = remapindex_4 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2475 = remapindex_4 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2476 = remapindex_4 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2477 = remapindex_4 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2478 = remapindex_4 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2479 = remapindex_4 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2480 = remapindex_4 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2481 = remapindex_4 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2482 = remapindex_4 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2483 = remapindex_4 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2484 = remapindex_4 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2485 = remapindex_4 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2486 = remapindex_4 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2487 = remapindex_4 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2488 = remapindex_4 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2489 = remapindex_4 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_bits : _T_2488 ? _Queue64_UInt8_30_io_deq_bits : _T_2487 ? _Queue64_UInt8_29_io_deq_bits : _T_2486 ? _Queue64_UInt8_28_io_deq_bits : _T_2485 ? _Queue64_UInt8_27_io_deq_bits : _T_2484 ? _Queue64_UInt8_26_io_deq_bits : _T_2483 ? _Queue64_UInt8_25_io_deq_bits : _T_2482 ? _Queue64_UInt8_24_io_deq_bits : _T_2481 ? _Queue64_UInt8_23_io_deq_bits : _T_2480 ? _Queue64_UInt8_22_io_deq_bits : _T_2479 ? _Queue64_UInt8_21_io_deq_bits : _T_2478 ? _Queue64_UInt8_20_io_deq_bits : _T_2477 ? _Queue64_UInt8_19_io_deq_bits : _T_2476 ? _Queue64_UInt8_18_io_deq_bits : _T_2475 ? _Queue64_UInt8_17_io_deq_bits : _T_2474 ? _Queue64_UInt8_16_io_deq_bits : _T_2473 ? _Queue64_UInt8_15_io_deq_bits : _T_2472 ? _Queue64_UInt8_14_io_deq_bits : _T_2471 ? _Queue64_UInt8_13_io_deq_bits : _T_2470 ? _Queue64_UInt8_12_io_deq_bits : _T_2469 ? _Queue64_UInt8_11_io_deq_bits : _T_2468 ? _Queue64_UInt8_10_io_deq_bits : _T_2467 ? _Queue64_UInt8_9_io_deq_bits : _T_2466 ? _Queue64_UInt8_8_io_deq_bits : _T_2465 ? _Queue64_UInt8_7_io_deq_bits : _T_2464 ? _Queue64_UInt8_6_io_deq_bits : _T_2463 ? _Queue64_UInt8_5_io_deq_bits : _T_2462 ? _Queue64_UInt8_4_io_deq_bits : _T_2461 ? _Queue64_UInt8_3_io_deq_bits : _T_2460 ? _Queue64_UInt8_2_io_deq_bits : _T_2459 ? _Queue64_UInt8_1_io_deq_bits : _T_2458 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_valid : _T_2488 ? _Queue64_UInt8_30_io_deq_valid : _T_2487 ? _Queue64_UInt8_29_io_deq_valid : _T_2486 ? _Queue64_UInt8_28_io_deq_valid : _T_2485 ? _Queue64_UInt8_27_io_deq_valid : _T_2484 ? _Queue64_UInt8_26_io_deq_valid : _T_2483 ? _Queue64_UInt8_25_io_deq_valid : _T_2482 ? _Queue64_UInt8_24_io_deq_valid : _T_2481 ? _Queue64_UInt8_23_io_deq_valid : _T_2480 ? _Queue64_UInt8_22_io_deq_valid : _T_2479 ? _Queue64_UInt8_21_io_deq_valid : _T_2478 ? _Queue64_UInt8_20_io_deq_valid : _T_2477 ? _Queue64_UInt8_19_io_deq_valid : _T_2476 ? _Queue64_UInt8_18_io_deq_valid : _T_2475 ? _Queue64_UInt8_17_io_deq_valid : _T_2474 ? _Queue64_UInt8_16_io_deq_valid : _T_2473 ? _Queue64_UInt8_15_io_deq_valid : _T_2472 ? _Queue64_UInt8_14_io_deq_valid : _T_2471 ? _Queue64_UInt8_13_io_deq_valid : _T_2470 ? _Queue64_UInt8_12_io_deq_valid : _T_2469 ? _Queue64_UInt8_11_io_deq_valid : _T_2468 ? _Queue64_UInt8_10_io_deq_valid : _T_2467 ? _Queue64_UInt8_9_io_deq_valid : _T_2466 ? _Queue64_UInt8_8_io_deq_valid : _T_2465 ? _Queue64_UInt8_7_io_deq_valid : _T_2464 ? _Queue64_UInt8_6_io_deq_valid : _T_2463 ? _Queue64_UInt8_5_io_deq_valid : _T_2462 ? _Queue64_UInt8_4_io_deq_valid : _T_2461 ? _Queue64_UInt8_3_io_deq_valid : _T_2460 ? _Queue64_UInt8_2_io_deq_valid : _T_2459 ? _Queue64_UInt8_1_io_deq_valid : _T_2458 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_96 = _remapindex_T_5 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_5 = _GEN_96[5:0]; // @[MemLoader.scala:177:54]
wire _T_2490 = remapindex_5 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2491 = remapindex_5 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2492 = remapindex_5 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2493 = remapindex_5 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2494 = remapindex_5 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2495 = remapindex_5 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2496 = remapindex_5 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2497 = remapindex_5 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2498 = remapindex_5 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2499 = remapindex_5 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2500 = remapindex_5 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2501 = remapindex_5 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2502 = remapindex_5 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2503 = remapindex_5 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2504 = remapindex_5 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2505 = remapindex_5 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2506 = remapindex_5 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2507 = remapindex_5 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2508 = remapindex_5 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2509 = remapindex_5 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2510 = remapindex_5 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2511 = remapindex_5 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2512 = remapindex_5 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2513 = remapindex_5 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2514 = remapindex_5 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2515 = remapindex_5 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2516 = remapindex_5 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2517 = remapindex_5 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2518 = remapindex_5 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2519 = remapindex_5 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2520 = remapindex_5 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2521 = remapindex_5 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_bits : _T_2520 ? _Queue64_UInt8_30_io_deq_bits : _T_2519 ? _Queue64_UInt8_29_io_deq_bits : _T_2518 ? _Queue64_UInt8_28_io_deq_bits : _T_2517 ? _Queue64_UInt8_27_io_deq_bits : _T_2516 ? _Queue64_UInt8_26_io_deq_bits : _T_2515 ? _Queue64_UInt8_25_io_deq_bits : _T_2514 ? _Queue64_UInt8_24_io_deq_bits : _T_2513 ? _Queue64_UInt8_23_io_deq_bits : _T_2512 ? _Queue64_UInt8_22_io_deq_bits : _T_2511 ? _Queue64_UInt8_21_io_deq_bits : _T_2510 ? _Queue64_UInt8_20_io_deq_bits : _T_2509 ? _Queue64_UInt8_19_io_deq_bits : _T_2508 ? _Queue64_UInt8_18_io_deq_bits : _T_2507 ? _Queue64_UInt8_17_io_deq_bits : _T_2506 ? _Queue64_UInt8_16_io_deq_bits : _T_2505 ? _Queue64_UInt8_15_io_deq_bits : _T_2504 ? _Queue64_UInt8_14_io_deq_bits : _T_2503 ? _Queue64_UInt8_13_io_deq_bits : _T_2502 ? _Queue64_UInt8_12_io_deq_bits : _T_2501 ? _Queue64_UInt8_11_io_deq_bits : _T_2500 ? _Queue64_UInt8_10_io_deq_bits : _T_2499 ? _Queue64_UInt8_9_io_deq_bits : _T_2498 ? _Queue64_UInt8_8_io_deq_bits : _T_2497 ? _Queue64_UInt8_7_io_deq_bits : _T_2496 ? _Queue64_UInt8_6_io_deq_bits : _T_2495 ? _Queue64_UInt8_5_io_deq_bits : _T_2494 ? _Queue64_UInt8_4_io_deq_bits : _T_2493 ? _Queue64_UInt8_3_io_deq_bits : _T_2492 ? _Queue64_UInt8_2_io_deq_bits : _T_2491 ? _Queue64_UInt8_1_io_deq_bits : _T_2490 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_valid : _T_2520 ? _Queue64_UInt8_30_io_deq_valid : _T_2519 ? _Queue64_UInt8_29_io_deq_valid : _T_2518 ? _Queue64_UInt8_28_io_deq_valid : _T_2517 ? _Queue64_UInt8_27_io_deq_valid : _T_2516 ? _Queue64_UInt8_26_io_deq_valid : _T_2515 ? _Queue64_UInt8_25_io_deq_valid : _T_2514 ? _Queue64_UInt8_24_io_deq_valid : _T_2513 ? _Queue64_UInt8_23_io_deq_valid : _T_2512 ? _Queue64_UInt8_22_io_deq_valid : _T_2511 ? _Queue64_UInt8_21_io_deq_valid : _T_2510 ? _Queue64_UInt8_20_io_deq_valid : _T_2509 ? _Queue64_UInt8_19_io_deq_valid : _T_2508 ? _Queue64_UInt8_18_io_deq_valid : _T_2507 ? _Queue64_UInt8_17_io_deq_valid : _T_2506 ? _Queue64_UInt8_16_io_deq_valid : _T_2505 ? _Queue64_UInt8_15_io_deq_valid : _T_2504 ? _Queue64_UInt8_14_io_deq_valid : _T_2503 ? _Queue64_UInt8_13_io_deq_valid : _T_2502 ? _Queue64_UInt8_12_io_deq_valid : _T_2501 ? _Queue64_UInt8_11_io_deq_valid : _T_2500 ? _Queue64_UInt8_10_io_deq_valid : _T_2499 ? _Queue64_UInt8_9_io_deq_valid : _T_2498 ? _Queue64_UInt8_8_io_deq_valid : _T_2497 ? _Queue64_UInt8_7_io_deq_valid : _T_2496 ? _Queue64_UInt8_6_io_deq_valid : _T_2495 ? _Queue64_UInt8_5_io_deq_valid : _T_2494 ? _Queue64_UInt8_4_io_deq_valid : _T_2493 ? _Queue64_UInt8_3_io_deq_valid : _T_2492 ? _Queue64_UInt8_2_io_deq_valid : _T_2491 ? _Queue64_UInt8_1_io_deq_valid : _T_2490 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_97 = _remapindex_T_6 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_6 = _GEN_97[5:0]; // @[MemLoader.scala:177:54]
wire _T_2522 = remapindex_6 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2523 = remapindex_6 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2524 = remapindex_6 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2525 = remapindex_6 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2526 = remapindex_6 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2527 = remapindex_6 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2528 = remapindex_6 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2529 = remapindex_6 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2530 = remapindex_6 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2531 = remapindex_6 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2532 = remapindex_6 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2533 = remapindex_6 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2534 = remapindex_6 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2535 = remapindex_6 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2536 = remapindex_6 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2537 = remapindex_6 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2538 = remapindex_6 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2539 = remapindex_6 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2540 = remapindex_6 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2541 = remapindex_6 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2542 = remapindex_6 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2543 = remapindex_6 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2544 = remapindex_6 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2545 = remapindex_6 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2546 = remapindex_6 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2547 = remapindex_6 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2548 = remapindex_6 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2549 = remapindex_6 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2550 = remapindex_6 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2551 = remapindex_6 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2552 = remapindex_6 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2553 = remapindex_6 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_bits : _T_2552 ? _Queue64_UInt8_30_io_deq_bits : _T_2551 ? _Queue64_UInt8_29_io_deq_bits : _T_2550 ? _Queue64_UInt8_28_io_deq_bits : _T_2549 ? _Queue64_UInt8_27_io_deq_bits : _T_2548 ? _Queue64_UInt8_26_io_deq_bits : _T_2547 ? _Queue64_UInt8_25_io_deq_bits : _T_2546 ? _Queue64_UInt8_24_io_deq_bits : _T_2545 ? _Queue64_UInt8_23_io_deq_bits : _T_2544 ? _Queue64_UInt8_22_io_deq_bits : _T_2543 ? _Queue64_UInt8_21_io_deq_bits : _T_2542 ? _Queue64_UInt8_20_io_deq_bits : _T_2541 ? _Queue64_UInt8_19_io_deq_bits : _T_2540 ? _Queue64_UInt8_18_io_deq_bits : _T_2539 ? _Queue64_UInt8_17_io_deq_bits : _T_2538 ? _Queue64_UInt8_16_io_deq_bits : _T_2537 ? _Queue64_UInt8_15_io_deq_bits : _T_2536 ? _Queue64_UInt8_14_io_deq_bits : _T_2535 ? _Queue64_UInt8_13_io_deq_bits : _T_2534 ? _Queue64_UInt8_12_io_deq_bits : _T_2533 ? _Queue64_UInt8_11_io_deq_bits : _T_2532 ? _Queue64_UInt8_10_io_deq_bits : _T_2531 ? _Queue64_UInt8_9_io_deq_bits : _T_2530 ? _Queue64_UInt8_8_io_deq_bits : _T_2529 ? _Queue64_UInt8_7_io_deq_bits : _T_2528 ? _Queue64_UInt8_6_io_deq_bits : _T_2527 ? _Queue64_UInt8_5_io_deq_bits : _T_2526 ? _Queue64_UInt8_4_io_deq_bits : _T_2525 ? _Queue64_UInt8_3_io_deq_bits : _T_2524 ? _Queue64_UInt8_2_io_deq_bits : _T_2523 ? _Queue64_UInt8_1_io_deq_bits : _T_2522 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_valid : _T_2552 ? _Queue64_UInt8_30_io_deq_valid : _T_2551 ? _Queue64_UInt8_29_io_deq_valid : _T_2550 ? _Queue64_UInt8_28_io_deq_valid : _T_2549 ? _Queue64_UInt8_27_io_deq_valid : _T_2548 ? _Queue64_UInt8_26_io_deq_valid : _T_2547 ? _Queue64_UInt8_25_io_deq_valid : _T_2546 ? _Queue64_UInt8_24_io_deq_valid : _T_2545 ? _Queue64_UInt8_23_io_deq_valid : _T_2544 ? _Queue64_UInt8_22_io_deq_valid : _T_2543 ? _Queue64_UInt8_21_io_deq_valid : _T_2542 ? _Queue64_UInt8_20_io_deq_valid : _T_2541 ? _Queue64_UInt8_19_io_deq_valid : _T_2540 ? _Queue64_UInt8_18_io_deq_valid : _T_2539 ? _Queue64_UInt8_17_io_deq_valid : _T_2538 ? _Queue64_UInt8_16_io_deq_valid : _T_2537 ? _Queue64_UInt8_15_io_deq_valid : _T_2536 ? _Queue64_UInt8_14_io_deq_valid : _T_2535 ? _Queue64_UInt8_13_io_deq_valid : _T_2534 ? _Queue64_UInt8_12_io_deq_valid : _T_2533 ? _Queue64_UInt8_11_io_deq_valid : _T_2532 ? _Queue64_UInt8_10_io_deq_valid : _T_2531 ? _Queue64_UInt8_9_io_deq_valid : _T_2530 ? _Queue64_UInt8_8_io_deq_valid : _T_2529 ? _Queue64_UInt8_7_io_deq_valid : _T_2528 ? _Queue64_UInt8_6_io_deq_valid : _T_2527 ? _Queue64_UInt8_5_io_deq_valid : _T_2526 ? _Queue64_UInt8_4_io_deq_valid : _T_2525 ? _Queue64_UInt8_3_io_deq_valid : _T_2524 ? _Queue64_UInt8_2_io_deq_valid : _T_2523 ? _Queue64_UInt8_1_io_deq_valid : _T_2522 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_98 = _remapindex_T_7 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_7 = _GEN_98[5:0]; // @[MemLoader.scala:177:54]
wire _T_2554 = remapindex_7 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2555 = remapindex_7 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2556 = remapindex_7 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2557 = remapindex_7 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2558 = remapindex_7 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2559 = remapindex_7 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2560 = remapindex_7 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2561 = remapindex_7 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2562 = remapindex_7 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2563 = remapindex_7 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2564 = remapindex_7 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2565 = remapindex_7 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2566 = remapindex_7 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2567 = remapindex_7 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2568 = remapindex_7 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2569 = remapindex_7 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2570 = remapindex_7 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2571 = remapindex_7 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2572 = remapindex_7 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2573 = remapindex_7 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2574 = remapindex_7 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2575 = remapindex_7 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2576 = remapindex_7 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2577 = remapindex_7 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2578 = remapindex_7 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2579 = remapindex_7 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2580 = remapindex_7 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2581 = remapindex_7 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2582 = remapindex_7 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2583 = remapindex_7 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2584 = remapindex_7 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2585 = remapindex_7 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_bits : _T_2584 ? _Queue64_UInt8_30_io_deq_bits : _T_2583 ? _Queue64_UInt8_29_io_deq_bits : _T_2582 ? _Queue64_UInt8_28_io_deq_bits : _T_2581 ? _Queue64_UInt8_27_io_deq_bits : _T_2580 ? _Queue64_UInt8_26_io_deq_bits : _T_2579 ? _Queue64_UInt8_25_io_deq_bits : _T_2578 ? _Queue64_UInt8_24_io_deq_bits : _T_2577 ? _Queue64_UInt8_23_io_deq_bits : _T_2576 ? _Queue64_UInt8_22_io_deq_bits : _T_2575 ? _Queue64_UInt8_21_io_deq_bits : _T_2574 ? _Queue64_UInt8_20_io_deq_bits : _T_2573 ? _Queue64_UInt8_19_io_deq_bits : _T_2572 ? _Queue64_UInt8_18_io_deq_bits : _T_2571 ? _Queue64_UInt8_17_io_deq_bits : _T_2570 ? _Queue64_UInt8_16_io_deq_bits : _T_2569 ? _Queue64_UInt8_15_io_deq_bits : _T_2568 ? _Queue64_UInt8_14_io_deq_bits : _T_2567 ? _Queue64_UInt8_13_io_deq_bits : _T_2566 ? _Queue64_UInt8_12_io_deq_bits : _T_2565 ? _Queue64_UInt8_11_io_deq_bits : _T_2564 ? _Queue64_UInt8_10_io_deq_bits : _T_2563 ? _Queue64_UInt8_9_io_deq_bits : _T_2562 ? _Queue64_UInt8_8_io_deq_bits : _T_2561 ? _Queue64_UInt8_7_io_deq_bits : _T_2560 ? _Queue64_UInt8_6_io_deq_bits : _T_2559 ? _Queue64_UInt8_5_io_deq_bits : _T_2558 ? _Queue64_UInt8_4_io_deq_bits : _T_2557 ? _Queue64_UInt8_3_io_deq_bits : _T_2556 ? _Queue64_UInt8_2_io_deq_bits : _T_2555 ? _Queue64_UInt8_1_io_deq_bits : _T_2554 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_valid : _T_2584 ? _Queue64_UInt8_30_io_deq_valid : _T_2583 ? _Queue64_UInt8_29_io_deq_valid : _T_2582 ? _Queue64_UInt8_28_io_deq_valid : _T_2581 ? _Queue64_UInt8_27_io_deq_valid : _T_2580 ? _Queue64_UInt8_26_io_deq_valid : _T_2579 ? _Queue64_UInt8_25_io_deq_valid : _T_2578 ? _Queue64_UInt8_24_io_deq_valid : _T_2577 ? _Queue64_UInt8_23_io_deq_valid : _T_2576 ? _Queue64_UInt8_22_io_deq_valid : _T_2575 ? _Queue64_UInt8_21_io_deq_valid : _T_2574 ? _Queue64_UInt8_20_io_deq_valid : _T_2573 ? _Queue64_UInt8_19_io_deq_valid : _T_2572 ? _Queue64_UInt8_18_io_deq_valid : _T_2571 ? _Queue64_UInt8_17_io_deq_valid : _T_2570 ? _Queue64_UInt8_16_io_deq_valid : _T_2569 ? _Queue64_UInt8_15_io_deq_valid : _T_2568 ? _Queue64_UInt8_14_io_deq_valid : _T_2567 ? _Queue64_UInt8_13_io_deq_valid : _T_2566 ? _Queue64_UInt8_12_io_deq_valid : _T_2565 ? _Queue64_UInt8_11_io_deq_valid : _T_2564 ? _Queue64_UInt8_10_io_deq_valid : _T_2563 ? _Queue64_UInt8_9_io_deq_valid : _T_2562 ? _Queue64_UInt8_8_io_deq_valid : _T_2561 ? _Queue64_UInt8_7_io_deq_valid : _T_2560 ? _Queue64_UInt8_6_io_deq_valid : _T_2559 ? _Queue64_UInt8_5_io_deq_valid : _T_2558 ? _Queue64_UInt8_4_io_deq_valid : _T_2557 ? _Queue64_UInt8_3_io_deq_valid : _T_2556 ? _Queue64_UInt8_2_io_deq_valid : _T_2555 ? _Queue64_UInt8_1_io_deq_valid : _T_2554 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_99 = _remapindex_T_8 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_8 = _GEN_99[5:0]; // @[MemLoader.scala:177:54]
wire _T_2586 = remapindex_8 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2587 = remapindex_8 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2588 = remapindex_8 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2589 = remapindex_8 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2590 = remapindex_8 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2591 = remapindex_8 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2592 = remapindex_8 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2593 = remapindex_8 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2594 = remapindex_8 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2595 = remapindex_8 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2596 = remapindex_8 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2597 = remapindex_8 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2598 = remapindex_8 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2599 = remapindex_8 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2600 = remapindex_8 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2601 = remapindex_8 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2602 = remapindex_8 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2603 = remapindex_8 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2604 = remapindex_8 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2605 = remapindex_8 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2606 = remapindex_8 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2607 = remapindex_8 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2608 = remapindex_8 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2609 = remapindex_8 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2610 = remapindex_8 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2611 = remapindex_8 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2612 = remapindex_8 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2613 = remapindex_8 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2614 = remapindex_8 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2615 = remapindex_8 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2616 = remapindex_8 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2617 = remapindex_8 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_bits : _T_2616 ? _Queue64_UInt8_30_io_deq_bits : _T_2615 ? _Queue64_UInt8_29_io_deq_bits : _T_2614 ? _Queue64_UInt8_28_io_deq_bits : _T_2613 ? _Queue64_UInt8_27_io_deq_bits : _T_2612 ? _Queue64_UInt8_26_io_deq_bits : _T_2611 ? _Queue64_UInt8_25_io_deq_bits : _T_2610 ? _Queue64_UInt8_24_io_deq_bits : _T_2609 ? _Queue64_UInt8_23_io_deq_bits : _T_2608 ? _Queue64_UInt8_22_io_deq_bits : _T_2607 ? _Queue64_UInt8_21_io_deq_bits : _T_2606 ? _Queue64_UInt8_20_io_deq_bits : _T_2605 ? _Queue64_UInt8_19_io_deq_bits : _T_2604 ? _Queue64_UInt8_18_io_deq_bits : _T_2603 ? _Queue64_UInt8_17_io_deq_bits : _T_2602 ? _Queue64_UInt8_16_io_deq_bits : _T_2601 ? _Queue64_UInt8_15_io_deq_bits : _T_2600 ? _Queue64_UInt8_14_io_deq_bits : _T_2599 ? _Queue64_UInt8_13_io_deq_bits : _T_2598 ? _Queue64_UInt8_12_io_deq_bits : _T_2597 ? _Queue64_UInt8_11_io_deq_bits : _T_2596 ? _Queue64_UInt8_10_io_deq_bits : _T_2595 ? _Queue64_UInt8_9_io_deq_bits : _T_2594 ? _Queue64_UInt8_8_io_deq_bits : _T_2593 ? _Queue64_UInt8_7_io_deq_bits : _T_2592 ? _Queue64_UInt8_6_io_deq_bits : _T_2591 ? _Queue64_UInt8_5_io_deq_bits : _T_2590 ? _Queue64_UInt8_4_io_deq_bits : _T_2589 ? _Queue64_UInt8_3_io_deq_bits : _T_2588 ? _Queue64_UInt8_2_io_deq_bits : _T_2587 ? _Queue64_UInt8_1_io_deq_bits : _T_2586 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_valid : _T_2616 ? _Queue64_UInt8_30_io_deq_valid : _T_2615 ? _Queue64_UInt8_29_io_deq_valid : _T_2614 ? _Queue64_UInt8_28_io_deq_valid : _T_2613 ? _Queue64_UInt8_27_io_deq_valid : _T_2612 ? _Queue64_UInt8_26_io_deq_valid : _T_2611 ? _Queue64_UInt8_25_io_deq_valid : _T_2610 ? _Queue64_UInt8_24_io_deq_valid : _T_2609 ? _Queue64_UInt8_23_io_deq_valid : _T_2608 ? _Queue64_UInt8_22_io_deq_valid : _T_2607 ? _Queue64_UInt8_21_io_deq_valid : _T_2606 ? _Queue64_UInt8_20_io_deq_valid : _T_2605 ? _Queue64_UInt8_19_io_deq_valid : _T_2604 ? _Queue64_UInt8_18_io_deq_valid : _T_2603 ? _Queue64_UInt8_17_io_deq_valid : _T_2602 ? _Queue64_UInt8_16_io_deq_valid : _T_2601 ? _Queue64_UInt8_15_io_deq_valid : _T_2600 ? _Queue64_UInt8_14_io_deq_valid : _T_2599 ? _Queue64_UInt8_13_io_deq_valid : _T_2598 ? _Queue64_UInt8_12_io_deq_valid : _T_2597 ? _Queue64_UInt8_11_io_deq_valid : _T_2596 ? _Queue64_UInt8_10_io_deq_valid : _T_2595 ? _Queue64_UInt8_9_io_deq_valid : _T_2594 ? _Queue64_UInt8_8_io_deq_valid : _T_2593 ? _Queue64_UInt8_7_io_deq_valid : _T_2592 ? _Queue64_UInt8_6_io_deq_valid : _T_2591 ? _Queue64_UInt8_5_io_deq_valid : _T_2590 ? _Queue64_UInt8_4_io_deq_valid : _T_2589 ? _Queue64_UInt8_3_io_deq_valid : _T_2588 ? _Queue64_UInt8_2_io_deq_valid : _T_2587 ? _Queue64_UInt8_1_io_deq_valid : _T_2586 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_100 = _remapindex_T_9 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_9 = _GEN_100[5:0]; // @[MemLoader.scala:177:54]
wire _T_2618 = remapindex_9 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2619 = remapindex_9 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2620 = remapindex_9 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2621 = remapindex_9 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2622 = remapindex_9 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2623 = remapindex_9 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2624 = remapindex_9 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2625 = remapindex_9 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2626 = remapindex_9 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2627 = remapindex_9 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2628 = remapindex_9 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2629 = remapindex_9 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2630 = remapindex_9 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2631 = remapindex_9 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2632 = remapindex_9 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2633 = remapindex_9 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2634 = remapindex_9 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2635 = remapindex_9 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2636 = remapindex_9 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2637 = remapindex_9 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2638 = remapindex_9 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2639 = remapindex_9 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2640 = remapindex_9 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2641 = remapindex_9 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2642 = remapindex_9 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2643 = remapindex_9 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2644 = remapindex_9 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2645 = remapindex_9 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2646 = remapindex_9 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2647 = remapindex_9 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2648 = remapindex_9 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2649 = remapindex_9 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_bits : _T_2648 ? _Queue64_UInt8_30_io_deq_bits : _T_2647 ? _Queue64_UInt8_29_io_deq_bits : _T_2646 ? _Queue64_UInt8_28_io_deq_bits : _T_2645 ? _Queue64_UInt8_27_io_deq_bits : _T_2644 ? _Queue64_UInt8_26_io_deq_bits : _T_2643 ? _Queue64_UInt8_25_io_deq_bits : _T_2642 ? _Queue64_UInt8_24_io_deq_bits : _T_2641 ? _Queue64_UInt8_23_io_deq_bits : _T_2640 ? _Queue64_UInt8_22_io_deq_bits : _T_2639 ? _Queue64_UInt8_21_io_deq_bits : _T_2638 ? _Queue64_UInt8_20_io_deq_bits : _T_2637 ? _Queue64_UInt8_19_io_deq_bits : _T_2636 ? _Queue64_UInt8_18_io_deq_bits : _T_2635 ? _Queue64_UInt8_17_io_deq_bits : _T_2634 ? _Queue64_UInt8_16_io_deq_bits : _T_2633 ? _Queue64_UInt8_15_io_deq_bits : _T_2632 ? _Queue64_UInt8_14_io_deq_bits : _T_2631 ? _Queue64_UInt8_13_io_deq_bits : _T_2630 ? _Queue64_UInt8_12_io_deq_bits : _T_2629 ? _Queue64_UInt8_11_io_deq_bits : _T_2628 ? _Queue64_UInt8_10_io_deq_bits : _T_2627 ? _Queue64_UInt8_9_io_deq_bits : _T_2626 ? _Queue64_UInt8_8_io_deq_bits : _T_2625 ? _Queue64_UInt8_7_io_deq_bits : _T_2624 ? _Queue64_UInt8_6_io_deq_bits : _T_2623 ? _Queue64_UInt8_5_io_deq_bits : _T_2622 ? _Queue64_UInt8_4_io_deq_bits : _T_2621 ? _Queue64_UInt8_3_io_deq_bits : _T_2620 ? _Queue64_UInt8_2_io_deq_bits : _T_2619 ? _Queue64_UInt8_1_io_deq_bits : _T_2618 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_valid : _T_2648 ? _Queue64_UInt8_30_io_deq_valid : _T_2647 ? _Queue64_UInt8_29_io_deq_valid : _T_2646 ? _Queue64_UInt8_28_io_deq_valid : _T_2645 ? _Queue64_UInt8_27_io_deq_valid : _T_2644 ? _Queue64_UInt8_26_io_deq_valid : _T_2643 ? _Queue64_UInt8_25_io_deq_valid : _T_2642 ? _Queue64_UInt8_24_io_deq_valid : _T_2641 ? _Queue64_UInt8_23_io_deq_valid : _T_2640 ? _Queue64_UInt8_22_io_deq_valid : _T_2639 ? _Queue64_UInt8_21_io_deq_valid : _T_2638 ? _Queue64_UInt8_20_io_deq_valid : _T_2637 ? _Queue64_UInt8_19_io_deq_valid : _T_2636 ? _Queue64_UInt8_18_io_deq_valid : _T_2635 ? _Queue64_UInt8_17_io_deq_valid : _T_2634 ? _Queue64_UInt8_16_io_deq_valid : _T_2633 ? _Queue64_UInt8_15_io_deq_valid : _T_2632 ? _Queue64_UInt8_14_io_deq_valid : _T_2631 ? _Queue64_UInt8_13_io_deq_valid : _T_2630 ? _Queue64_UInt8_12_io_deq_valid : _T_2629 ? _Queue64_UInt8_11_io_deq_valid : _T_2628 ? _Queue64_UInt8_10_io_deq_valid : _T_2627 ? _Queue64_UInt8_9_io_deq_valid : _T_2626 ? _Queue64_UInt8_8_io_deq_valid : _T_2625 ? _Queue64_UInt8_7_io_deq_valid : _T_2624 ? _Queue64_UInt8_6_io_deq_valid : _T_2623 ? _Queue64_UInt8_5_io_deq_valid : _T_2622 ? _Queue64_UInt8_4_io_deq_valid : _T_2621 ? _Queue64_UInt8_3_io_deq_valid : _T_2620 ? _Queue64_UInt8_2_io_deq_valid : _T_2619 ? _Queue64_UInt8_1_io_deq_valid : _T_2618 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_101 = _remapindex_T_10 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_10 = _GEN_101[5:0]; // @[MemLoader.scala:177:54]
wire _T_2650 = remapindex_10 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2651 = remapindex_10 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2652 = remapindex_10 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2653 = remapindex_10 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2654 = remapindex_10 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2655 = remapindex_10 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2656 = remapindex_10 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2657 = remapindex_10 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2658 = remapindex_10 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2659 = remapindex_10 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2660 = remapindex_10 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2661 = remapindex_10 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2662 = remapindex_10 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2663 = remapindex_10 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2664 = remapindex_10 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2665 = remapindex_10 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2666 = remapindex_10 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2667 = remapindex_10 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2668 = remapindex_10 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2669 = remapindex_10 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2670 = remapindex_10 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2671 = remapindex_10 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2672 = remapindex_10 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2673 = remapindex_10 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2674 = remapindex_10 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2675 = remapindex_10 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2676 = remapindex_10 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2677 = remapindex_10 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2678 = remapindex_10 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2679 = remapindex_10 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2680 = remapindex_10 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2681 = remapindex_10 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_bits : _T_2680 ? _Queue64_UInt8_30_io_deq_bits : _T_2679 ? _Queue64_UInt8_29_io_deq_bits : _T_2678 ? _Queue64_UInt8_28_io_deq_bits : _T_2677 ? _Queue64_UInt8_27_io_deq_bits : _T_2676 ? _Queue64_UInt8_26_io_deq_bits : _T_2675 ? _Queue64_UInt8_25_io_deq_bits : _T_2674 ? _Queue64_UInt8_24_io_deq_bits : _T_2673 ? _Queue64_UInt8_23_io_deq_bits : _T_2672 ? _Queue64_UInt8_22_io_deq_bits : _T_2671 ? _Queue64_UInt8_21_io_deq_bits : _T_2670 ? _Queue64_UInt8_20_io_deq_bits : _T_2669 ? _Queue64_UInt8_19_io_deq_bits : _T_2668 ? _Queue64_UInt8_18_io_deq_bits : _T_2667 ? _Queue64_UInt8_17_io_deq_bits : _T_2666 ? _Queue64_UInt8_16_io_deq_bits : _T_2665 ? _Queue64_UInt8_15_io_deq_bits : _T_2664 ? _Queue64_UInt8_14_io_deq_bits : _T_2663 ? _Queue64_UInt8_13_io_deq_bits : _T_2662 ? _Queue64_UInt8_12_io_deq_bits : _T_2661 ? _Queue64_UInt8_11_io_deq_bits : _T_2660 ? _Queue64_UInt8_10_io_deq_bits : _T_2659 ? _Queue64_UInt8_9_io_deq_bits : _T_2658 ? _Queue64_UInt8_8_io_deq_bits : _T_2657 ? _Queue64_UInt8_7_io_deq_bits : _T_2656 ? _Queue64_UInt8_6_io_deq_bits : _T_2655 ? _Queue64_UInt8_5_io_deq_bits : _T_2654 ? _Queue64_UInt8_4_io_deq_bits : _T_2653 ? _Queue64_UInt8_3_io_deq_bits : _T_2652 ? _Queue64_UInt8_2_io_deq_bits : _T_2651 ? _Queue64_UInt8_1_io_deq_bits : _T_2650 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_valid : _T_2680 ? _Queue64_UInt8_30_io_deq_valid : _T_2679 ? _Queue64_UInt8_29_io_deq_valid : _T_2678 ? _Queue64_UInt8_28_io_deq_valid : _T_2677 ? _Queue64_UInt8_27_io_deq_valid : _T_2676 ? _Queue64_UInt8_26_io_deq_valid : _T_2675 ? _Queue64_UInt8_25_io_deq_valid : _T_2674 ? _Queue64_UInt8_24_io_deq_valid : _T_2673 ? _Queue64_UInt8_23_io_deq_valid : _T_2672 ? _Queue64_UInt8_22_io_deq_valid : _T_2671 ? _Queue64_UInt8_21_io_deq_valid : _T_2670 ? _Queue64_UInt8_20_io_deq_valid : _T_2669 ? _Queue64_UInt8_19_io_deq_valid : _T_2668 ? _Queue64_UInt8_18_io_deq_valid : _T_2667 ? _Queue64_UInt8_17_io_deq_valid : _T_2666 ? _Queue64_UInt8_16_io_deq_valid : _T_2665 ? _Queue64_UInt8_15_io_deq_valid : _T_2664 ? _Queue64_UInt8_14_io_deq_valid : _T_2663 ? _Queue64_UInt8_13_io_deq_valid : _T_2662 ? _Queue64_UInt8_12_io_deq_valid : _T_2661 ? _Queue64_UInt8_11_io_deq_valid : _T_2660 ? _Queue64_UInt8_10_io_deq_valid : _T_2659 ? _Queue64_UInt8_9_io_deq_valid : _T_2658 ? _Queue64_UInt8_8_io_deq_valid : _T_2657 ? _Queue64_UInt8_7_io_deq_valid : _T_2656 ? _Queue64_UInt8_6_io_deq_valid : _T_2655 ? _Queue64_UInt8_5_io_deq_valid : _T_2654 ? _Queue64_UInt8_4_io_deq_valid : _T_2653 ? _Queue64_UInt8_3_io_deq_valid : _T_2652 ? _Queue64_UInt8_2_io_deq_valid : _T_2651 ? _Queue64_UInt8_1_io_deq_valid : _T_2650 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_102 = _remapindex_T_11 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_11 = _GEN_102[5:0]; // @[MemLoader.scala:177:54]
wire _T_2682 = remapindex_11 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2683 = remapindex_11 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2684 = remapindex_11 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2685 = remapindex_11 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2686 = remapindex_11 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2687 = remapindex_11 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2688 = remapindex_11 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2689 = remapindex_11 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2690 = remapindex_11 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2691 = remapindex_11 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2692 = remapindex_11 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2693 = remapindex_11 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2694 = remapindex_11 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2695 = remapindex_11 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2696 = remapindex_11 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2697 = remapindex_11 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2698 = remapindex_11 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2699 = remapindex_11 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2700 = remapindex_11 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2701 = remapindex_11 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2702 = remapindex_11 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2703 = remapindex_11 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2704 = remapindex_11 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2705 = remapindex_11 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2706 = remapindex_11 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2707 = remapindex_11 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2708 = remapindex_11 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2709 = remapindex_11 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2710 = remapindex_11 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2711 = remapindex_11 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2712 = remapindex_11 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2713 = remapindex_11 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_bits : _T_2712 ? _Queue64_UInt8_30_io_deq_bits : _T_2711 ? _Queue64_UInt8_29_io_deq_bits : _T_2710 ? _Queue64_UInt8_28_io_deq_bits : _T_2709 ? _Queue64_UInt8_27_io_deq_bits : _T_2708 ? _Queue64_UInt8_26_io_deq_bits : _T_2707 ? _Queue64_UInt8_25_io_deq_bits : _T_2706 ? _Queue64_UInt8_24_io_deq_bits : _T_2705 ? _Queue64_UInt8_23_io_deq_bits : _T_2704 ? _Queue64_UInt8_22_io_deq_bits : _T_2703 ? _Queue64_UInt8_21_io_deq_bits : _T_2702 ? _Queue64_UInt8_20_io_deq_bits : _T_2701 ? _Queue64_UInt8_19_io_deq_bits : _T_2700 ? _Queue64_UInt8_18_io_deq_bits : _T_2699 ? _Queue64_UInt8_17_io_deq_bits : _T_2698 ? _Queue64_UInt8_16_io_deq_bits : _T_2697 ? _Queue64_UInt8_15_io_deq_bits : _T_2696 ? _Queue64_UInt8_14_io_deq_bits : _T_2695 ? _Queue64_UInt8_13_io_deq_bits : _T_2694 ? _Queue64_UInt8_12_io_deq_bits : _T_2693 ? _Queue64_UInt8_11_io_deq_bits : _T_2692 ? _Queue64_UInt8_10_io_deq_bits : _T_2691 ? _Queue64_UInt8_9_io_deq_bits : _T_2690 ? _Queue64_UInt8_8_io_deq_bits : _T_2689 ? _Queue64_UInt8_7_io_deq_bits : _T_2688 ? _Queue64_UInt8_6_io_deq_bits : _T_2687 ? _Queue64_UInt8_5_io_deq_bits : _T_2686 ? _Queue64_UInt8_4_io_deq_bits : _T_2685 ? _Queue64_UInt8_3_io_deq_bits : _T_2684 ? _Queue64_UInt8_2_io_deq_bits : _T_2683 ? _Queue64_UInt8_1_io_deq_bits : _T_2682 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_valid : _T_2712 ? _Queue64_UInt8_30_io_deq_valid : _T_2711 ? _Queue64_UInt8_29_io_deq_valid : _T_2710 ? _Queue64_UInt8_28_io_deq_valid : _T_2709 ? _Queue64_UInt8_27_io_deq_valid : _T_2708 ? _Queue64_UInt8_26_io_deq_valid : _T_2707 ? _Queue64_UInt8_25_io_deq_valid : _T_2706 ? _Queue64_UInt8_24_io_deq_valid : _T_2705 ? _Queue64_UInt8_23_io_deq_valid : _T_2704 ? _Queue64_UInt8_22_io_deq_valid : _T_2703 ? _Queue64_UInt8_21_io_deq_valid : _T_2702 ? _Queue64_UInt8_20_io_deq_valid : _T_2701 ? _Queue64_UInt8_19_io_deq_valid : _T_2700 ? _Queue64_UInt8_18_io_deq_valid : _T_2699 ? _Queue64_UInt8_17_io_deq_valid : _T_2698 ? _Queue64_UInt8_16_io_deq_valid : _T_2697 ? _Queue64_UInt8_15_io_deq_valid : _T_2696 ? _Queue64_UInt8_14_io_deq_valid : _T_2695 ? _Queue64_UInt8_13_io_deq_valid : _T_2694 ? _Queue64_UInt8_12_io_deq_valid : _T_2693 ? _Queue64_UInt8_11_io_deq_valid : _T_2692 ? _Queue64_UInt8_10_io_deq_valid : _T_2691 ? _Queue64_UInt8_9_io_deq_valid : _T_2690 ? _Queue64_UInt8_8_io_deq_valid : _T_2689 ? _Queue64_UInt8_7_io_deq_valid : _T_2688 ? _Queue64_UInt8_6_io_deq_valid : _T_2687 ? _Queue64_UInt8_5_io_deq_valid : _T_2686 ? _Queue64_UInt8_4_io_deq_valid : _T_2685 ? _Queue64_UInt8_3_io_deq_valid : _T_2684 ? _Queue64_UInt8_2_io_deq_valid : _T_2683 ? _Queue64_UInt8_1_io_deq_valid : _T_2682 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_103 = _remapindex_T_12 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_12 = _GEN_103[5:0]; // @[MemLoader.scala:177:54]
wire _T_2714 = remapindex_12 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2715 = remapindex_12 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2716 = remapindex_12 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2717 = remapindex_12 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2718 = remapindex_12 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2719 = remapindex_12 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2720 = remapindex_12 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2721 = remapindex_12 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2722 = remapindex_12 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2723 = remapindex_12 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2724 = remapindex_12 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2725 = remapindex_12 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2726 = remapindex_12 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2727 = remapindex_12 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2728 = remapindex_12 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2729 = remapindex_12 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2730 = remapindex_12 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2731 = remapindex_12 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2732 = remapindex_12 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2733 = remapindex_12 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2734 = remapindex_12 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2735 = remapindex_12 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2736 = remapindex_12 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2737 = remapindex_12 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2738 = remapindex_12 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2739 = remapindex_12 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2740 = remapindex_12 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2741 = remapindex_12 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2742 = remapindex_12 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2743 = remapindex_12 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2744 = remapindex_12 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2745 = remapindex_12 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_bits : _T_2744 ? _Queue64_UInt8_30_io_deq_bits : _T_2743 ? _Queue64_UInt8_29_io_deq_bits : _T_2742 ? _Queue64_UInt8_28_io_deq_bits : _T_2741 ? _Queue64_UInt8_27_io_deq_bits : _T_2740 ? _Queue64_UInt8_26_io_deq_bits : _T_2739 ? _Queue64_UInt8_25_io_deq_bits : _T_2738 ? _Queue64_UInt8_24_io_deq_bits : _T_2737 ? _Queue64_UInt8_23_io_deq_bits : _T_2736 ? _Queue64_UInt8_22_io_deq_bits : _T_2735 ? _Queue64_UInt8_21_io_deq_bits : _T_2734 ? _Queue64_UInt8_20_io_deq_bits : _T_2733 ? _Queue64_UInt8_19_io_deq_bits : _T_2732 ? _Queue64_UInt8_18_io_deq_bits : _T_2731 ? _Queue64_UInt8_17_io_deq_bits : _T_2730 ? _Queue64_UInt8_16_io_deq_bits : _T_2729 ? _Queue64_UInt8_15_io_deq_bits : _T_2728 ? _Queue64_UInt8_14_io_deq_bits : _T_2727 ? _Queue64_UInt8_13_io_deq_bits : _T_2726 ? _Queue64_UInt8_12_io_deq_bits : _T_2725 ? _Queue64_UInt8_11_io_deq_bits : _T_2724 ? _Queue64_UInt8_10_io_deq_bits : _T_2723 ? _Queue64_UInt8_9_io_deq_bits : _T_2722 ? _Queue64_UInt8_8_io_deq_bits : _T_2721 ? _Queue64_UInt8_7_io_deq_bits : _T_2720 ? _Queue64_UInt8_6_io_deq_bits : _T_2719 ? _Queue64_UInt8_5_io_deq_bits : _T_2718 ? _Queue64_UInt8_4_io_deq_bits : _T_2717 ? _Queue64_UInt8_3_io_deq_bits : _T_2716 ? _Queue64_UInt8_2_io_deq_bits : _T_2715 ? _Queue64_UInt8_1_io_deq_bits : _T_2714 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_valid : _T_2744 ? _Queue64_UInt8_30_io_deq_valid : _T_2743 ? _Queue64_UInt8_29_io_deq_valid : _T_2742 ? _Queue64_UInt8_28_io_deq_valid : _T_2741 ? _Queue64_UInt8_27_io_deq_valid : _T_2740 ? _Queue64_UInt8_26_io_deq_valid : _T_2739 ? _Queue64_UInt8_25_io_deq_valid : _T_2738 ? _Queue64_UInt8_24_io_deq_valid : _T_2737 ? _Queue64_UInt8_23_io_deq_valid : _T_2736 ? _Queue64_UInt8_22_io_deq_valid : _T_2735 ? _Queue64_UInt8_21_io_deq_valid : _T_2734 ? _Queue64_UInt8_20_io_deq_valid : _T_2733 ? _Queue64_UInt8_19_io_deq_valid : _T_2732 ? _Queue64_UInt8_18_io_deq_valid : _T_2731 ? _Queue64_UInt8_17_io_deq_valid : _T_2730 ? _Queue64_UInt8_16_io_deq_valid : _T_2729 ? _Queue64_UInt8_15_io_deq_valid : _T_2728 ? _Queue64_UInt8_14_io_deq_valid : _T_2727 ? _Queue64_UInt8_13_io_deq_valid : _T_2726 ? _Queue64_UInt8_12_io_deq_valid : _T_2725 ? _Queue64_UInt8_11_io_deq_valid : _T_2724 ? _Queue64_UInt8_10_io_deq_valid : _T_2723 ? _Queue64_UInt8_9_io_deq_valid : _T_2722 ? _Queue64_UInt8_8_io_deq_valid : _T_2721 ? _Queue64_UInt8_7_io_deq_valid : _T_2720 ? _Queue64_UInt8_6_io_deq_valid : _T_2719 ? _Queue64_UInt8_5_io_deq_valid : _T_2718 ? _Queue64_UInt8_4_io_deq_valid : _T_2717 ? _Queue64_UInt8_3_io_deq_valid : _T_2716 ? _Queue64_UInt8_2_io_deq_valid : _T_2715 ? _Queue64_UInt8_1_io_deq_valid : _T_2714 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_104 = _remapindex_T_13 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_13 = _GEN_104[5:0]; // @[MemLoader.scala:177:54]
wire _T_2746 = remapindex_13 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2747 = remapindex_13 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2748 = remapindex_13 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2749 = remapindex_13 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2750 = remapindex_13 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2751 = remapindex_13 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2752 = remapindex_13 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2753 = remapindex_13 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2754 = remapindex_13 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2755 = remapindex_13 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2756 = remapindex_13 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2757 = remapindex_13 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2758 = remapindex_13 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2759 = remapindex_13 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2760 = remapindex_13 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2761 = remapindex_13 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2762 = remapindex_13 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2763 = remapindex_13 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2764 = remapindex_13 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2765 = remapindex_13 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2766 = remapindex_13 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2767 = remapindex_13 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2768 = remapindex_13 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2769 = remapindex_13 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2770 = remapindex_13 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2771 = remapindex_13 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2772 = remapindex_13 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2773 = remapindex_13 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2774 = remapindex_13 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2775 = remapindex_13 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2776 = remapindex_13 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2777 = remapindex_13 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_bits : _T_2776 ? _Queue64_UInt8_30_io_deq_bits : _T_2775 ? _Queue64_UInt8_29_io_deq_bits : _T_2774 ? _Queue64_UInt8_28_io_deq_bits : _T_2773 ? _Queue64_UInt8_27_io_deq_bits : _T_2772 ? _Queue64_UInt8_26_io_deq_bits : _T_2771 ? _Queue64_UInt8_25_io_deq_bits : _T_2770 ? _Queue64_UInt8_24_io_deq_bits : _T_2769 ? _Queue64_UInt8_23_io_deq_bits : _T_2768 ? _Queue64_UInt8_22_io_deq_bits : _T_2767 ? _Queue64_UInt8_21_io_deq_bits : _T_2766 ? _Queue64_UInt8_20_io_deq_bits : _T_2765 ? _Queue64_UInt8_19_io_deq_bits : _T_2764 ? _Queue64_UInt8_18_io_deq_bits : _T_2763 ? _Queue64_UInt8_17_io_deq_bits : _T_2762 ? _Queue64_UInt8_16_io_deq_bits : _T_2761 ? _Queue64_UInt8_15_io_deq_bits : _T_2760 ? _Queue64_UInt8_14_io_deq_bits : _T_2759 ? _Queue64_UInt8_13_io_deq_bits : _T_2758 ? _Queue64_UInt8_12_io_deq_bits : _T_2757 ? _Queue64_UInt8_11_io_deq_bits : _T_2756 ? _Queue64_UInt8_10_io_deq_bits : _T_2755 ? _Queue64_UInt8_9_io_deq_bits : _T_2754 ? _Queue64_UInt8_8_io_deq_bits : _T_2753 ? _Queue64_UInt8_7_io_deq_bits : _T_2752 ? _Queue64_UInt8_6_io_deq_bits : _T_2751 ? _Queue64_UInt8_5_io_deq_bits : _T_2750 ? _Queue64_UInt8_4_io_deq_bits : _T_2749 ? _Queue64_UInt8_3_io_deq_bits : _T_2748 ? _Queue64_UInt8_2_io_deq_bits : _T_2747 ? _Queue64_UInt8_1_io_deq_bits : _T_2746 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_valid : _T_2776 ? _Queue64_UInt8_30_io_deq_valid : _T_2775 ? _Queue64_UInt8_29_io_deq_valid : _T_2774 ? _Queue64_UInt8_28_io_deq_valid : _T_2773 ? _Queue64_UInt8_27_io_deq_valid : _T_2772 ? _Queue64_UInt8_26_io_deq_valid : _T_2771 ? _Queue64_UInt8_25_io_deq_valid : _T_2770 ? _Queue64_UInt8_24_io_deq_valid : _T_2769 ? _Queue64_UInt8_23_io_deq_valid : _T_2768 ? _Queue64_UInt8_22_io_deq_valid : _T_2767 ? _Queue64_UInt8_21_io_deq_valid : _T_2766 ? _Queue64_UInt8_20_io_deq_valid : _T_2765 ? _Queue64_UInt8_19_io_deq_valid : _T_2764 ? _Queue64_UInt8_18_io_deq_valid : _T_2763 ? _Queue64_UInt8_17_io_deq_valid : _T_2762 ? _Queue64_UInt8_16_io_deq_valid : _T_2761 ? _Queue64_UInt8_15_io_deq_valid : _T_2760 ? _Queue64_UInt8_14_io_deq_valid : _T_2759 ? _Queue64_UInt8_13_io_deq_valid : _T_2758 ? _Queue64_UInt8_12_io_deq_valid : _T_2757 ? _Queue64_UInt8_11_io_deq_valid : _T_2756 ? _Queue64_UInt8_10_io_deq_valid : _T_2755 ? _Queue64_UInt8_9_io_deq_valid : _T_2754 ? _Queue64_UInt8_8_io_deq_valid : _T_2753 ? _Queue64_UInt8_7_io_deq_valid : _T_2752 ? _Queue64_UInt8_6_io_deq_valid : _T_2751 ? _Queue64_UInt8_5_io_deq_valid : _T_2750 ? _Queue64_UInt8_4_io_deq_valid : _T_2749 ? _Queue64_UInt8_3_io_deq_valid : _T_2748 ? _Queue64_UInt8_2_io_deq_valid : _T_2747 ? _Queue64_UInt8_1_io_deq_valid : _T_2746 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_105 = _remapindex_T_14 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_14 = _GEN_105[5:0]; // @[MemLoader.scala:177:54]
wire _T_2778 = remapindex_14 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2779 = remapindex_14 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2780 = remapindex_14 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2781 = remapindex_14 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2782 = remapindex_14 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2783 = remapindex_14 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2784 = remapindex_14 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2785 = remapindex_14 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2786 = remapindex_14 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2787 = remapindex_14 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2788 = remapindex_14 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2789 = remapindex_14 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2790 = remapindex_14 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2791 = remapindex_14 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2792 = remapindex_14 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2793 = remapindex_14 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2794 = remapindex_14 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2795 = remapindex_14 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2796 = remapindex_14 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2797 = remapindex_14 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2798 = remapindex_14 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2799 = remapindex_14 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2800 = remapindex_14 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2801 = remapindex_14 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2802 = remapindex_14 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2803 = remapindex_14 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2804 = remapindex_14 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2805 = remapindex_14 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2806 = remapindex_14 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2807 = remapindex_14 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2808 = remapindex_14 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2809 = remapindex_14 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_bits : _T_2808 ? _Queue64_UInt8_30_io_deq_bits : _T_2807 ? _Queue64_UInt8_29_io_deq_bits : _T_2806 ? _Queue64_UInt8_28_io_deq_bits : _T_2805 ? _Queue64_UInt8_27_io_deq_bits : _T_2804 ? _Queue64_UInt8_26_io_deq_bits : _T_2803 ? _Queue64_UInt8_25_io_deq_bits : _T_2802 ? _Queue64_UInt8_24_io_deq_bits : _T_2801 ? _Queue64_UInt8_23_io_deq_bits : _T_2800 ? _Queue64_UInt8_22_io_deq_bits : _T_2799 ? _Queue64_UInt8_21_io_deq_bits : _T_2798 ? _Queue64_UInt8_20_io_deq_bits : _T_2797 ? _Queue64_UInt8_19_io_deq_bits : _T_2796 ? _Queue64_UInt8_18_io_deq_bits : _T_2795 ? _Queue64_UInt8_17_io_deq_bits : _T_2794 ? _Queue64_UInt8_16_io_deq_bits : _T_2793 ? _Queue64_UInt8_15_io_deq_bits : _T_2792 ? _Queue64_UInt8_14_io_deq_bits : _T_2791 ? _Queue64_UInt8_13_io_deq_bits : _T_2790 ? _Queue64_UInt8_12_io_deq_bits : _T_2789 ? _Queue64_UInt8_11_io_deq_bits : _T_2788 ? _Queue64_UInt8_10_io_deq_bits : _T_2787 ? _Queue64_UInt8_9_io_deq_bits : _T_2786 ? _Queue64_UInt8_8_io_deq_bits : _T_2785 ? _Queue64_UInt8_7_io_deq_bits : _T_2784 ? _Queue64_UInt8_6_io_deq_bits : _T_2783 ? _Queue64_UInt8_5_io_deq_bits : _T_2782 ? _Queue64_UInt8_4_io_deq_bits : _T_2781 ? _Queue64_UInt8_3_io_deq_bits : _T_2780 ? _Queue64_UInt8_2_io_deq_bits : _T_2779 ? _Queue64_UInt8_1_io_deq_bits : _T_2778 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_valid : _T_2808 ? _Queue64_UInt8_30_io_deq_valid : _T_2807 ? _Queue64_UInt8_29_io_deq_valid : _T_2806 ? _Queue64_UInt8_28_io_deq_valid : _T_2805 ? _Queue64_UInt8_27_io_deq_valid : _T_2804 ? _Queue64_UInt8_26_io_deq_valid : _T_2803 ? _Queue64_UInt8_25_io_deq_valid : _T_2802 ? _Queue64_UInt8_24_io_deq_valid : _T_2801 ? _Queue64_UInt8_23_io_deq_valid : _T_2800 ? _Queue64_UInt8_22_io_deq_valid : _T_2799 ? _Queue64_UInt8_21_io_deq_valid : _T_2798 ? _Queue64_UInt8_20_io_deq_valid : _T_2797 ? _Queue64_UInt8_19_io_deq_valid : _T_2796 ? _Queue64_UInt8_18_io_deq_valid : _T_2795 ? _Queue64_UInt8_17_io_deq_valid : _T_2794 ? _Queue64_UInt8_16_io_deq_valid : _T_2793 ? _Queue64_UInt8_15_io_deq_valid : _T_2792 ? _Queue64_UInt8_14_io_deq_valid : _T_2791 ? _Queue64_UInt8_13_io_deq_valid : _T_2790 ? _Queue64_UInt8_12_io_deq_valid : _T_2789 ? _Queue64_UInt8_11_io_deq_valid : _T_2788 ? _Queue64_UInt8_10_io_deq_valid : _T_2787 ? _Queue64_UInt8_9_io_deq_valid : _T_2786 ? _Queue64_UInt8_8_io_deq_valid : _T_2785 ? _Queue64_UInt8_7_io_deq_valid : _T_2784 ? _Queue64_UInt8_6_io_deq_valid : _T_2783 ? _Queue64_UInt8_5_io_deq_valid : _T_2782 ? _Queue64_UInt8_4_io_deq_valid : _T_2781 ? _Queue64_UInt8_3_io_deq_valid : _T_2780 ? _Queue64_UInt8_2_io_deq_valid : _T_2779 ? _Queue64_UInt8_1_io_deq_valid : _T_2778 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_106 = _remapindex_T_15 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_15 = _GEN_106[5:0]; // @[MemLoader.scala:177:54]
wire _T_2810 = remapindex_15 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2811 = remapindex_15 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2812 = remapindex_15 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2813 = remapindex_15 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2814 = remapindex_15 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2815 = remapindex_15 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2816 = remapindex_15 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2817 = remapindex_15 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2818 = remapindex_15 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2819 = remapindex_15 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2820 = remapindex_15 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2821 = remapindex_15 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2822 = remapindex_15 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2823 = remapindex_15 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2824 = remapindex_15 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2825 = remapindex_15 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2826 = remapindex_15 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2827 = remapindex_15 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2828 = remapindex_15 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2829 = remapindex_15 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2830 = remapindex_15 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2831 = remapindex_15 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2832 = remapindex_15 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2833 = remapindex_15 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2834 = remapindex_15 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2835 = remapindex_15 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2836 = remapindex_15 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2837 = remapindex_15 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2838 = remapindex_15 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2839 = remapindex_15 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2840 = remapindex_15 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2841 = remapindex_15 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_bits : _T_2840 ? _Queue64_UInt8_30_io_deq_bits : _T_2839 ? _Queue64_UInt8_29_io_deq_bits : _T_2838 ? _Queue64_UInt8_28_io_deq_bits : _T_2837 ? _Queue64_UInt8_27_io_deq_bits : _T_2836 ? _Queue64_UInt8_26_io_deq_bits : _T_2835 ? _Queue64_UInt8_25_io_deq_bits : _T_2834 ? _Queue64_UInt8_24_io_deq_bits : _T_2833 ? _Queue64_UInt8_23_io_deq_bits : _T_2832 ? _Queue64_UInt8_22_io_deq_bits : _T_2831 ? _Queue64_UInt8_21_io_deq_bits : _T_2830 ? _Queue64_UInt8_20_io_deq_bits : _T_2829 ? _Queue64_UInt8_19_io_deq_bits : _T_2828 ? _Queue64_UInt8_18_io_deq_bits : _T_2827 ? _Queue64_UInt8_17_io_deq_bits : _T_2826 ? _Queue64_UInt8_16_io_deq_bits : _T_2825 ? _Queue64_UInt8_15_io_deq_bits : _T_2824 ? _Queue64_UInt8_14_io_deq_bits : _T_2823 ? _Queue64_UInt8_13_io_deq_bits : _T_2822 ? _Queue64_UInt8_12_io_deq_bits : _T_2821 ? _Queue64_UInt8_11_io_deq_bits : _T_2820 ? _Queue64_UInt8_10_io_deq_bits : _T_2819 ? _Queue64_UInt8_9_io_deq_bits : _T_2818 ? _Queue64_UInt8_8_io_deq_bits : _T_2817 ? _Queue64_UInt8_7_io_deq_bits : _T_2816 ? _Queue64_UInt8_6_io_deq_bits : _T_2815 ? _Queue64_UInt8_5_io_deq_bits : _T_2814 ? _Queue64_UInt8_4_io_deq_bits : _T_2813 ? _Queue64_UInt8_3_io_deq_bits : _T_2812 ? _Queue64_UInt8_2_io_deq_bits : _T_2811 ? _Queue64_UInt8_1_io_deq_bits : _T_2810 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_valid : _T_2840 ? _Queue64_UInt8_30_io_deq_valid : _T_2839 ? _Queue64_UInt8_29_io_deq_valid : _T_2838 ? _Queue64_UInt8_28_io_deq_valid : _T_2837 ? _Queue64_UInt8_27_io_deq_valid : _T_2836 ? _Queue64_UInt8_26_io_deq_valid : _T_2835 ? _Queue64_UInt8_25_io_deq_valid : _T_2834 ? _Queue64_UInt8_24_io_deq_valid : _T_2833 ? _Queue64_UInt8_23_io_deq_valid : _T_2832 ? _Queue64_UInt8_22_io_deq_valid : _T_2831 ? _Queue64_UInt8_21_io_deq_valid : _T_2830 ? _Queue64_UInt8_20_io_deq_valid : _T_2829 ? _Queue64_UInt8_19_io_deq_valid : _T_2828 ? _Queue64_UInt8_18_io_deq_valid : _T_2827 ? _Queue64_UInt8_17_io_deq_valid : _T_2826 ? _Queue64_UInt8_16_io_deq_valid : _T_2825 ? _Queue64_UInt8_15_io_deq_valid : _T_2824 ? _Queue64_UInt8_14_io_deq_valid : _T_2823 ? _Queue64_UInt8_13_io_deq_valid : _T_2822 ? _Queue64_UInt8_12_io_deq_valid : _T_2821 ? _Queue64_UInt8_11_io_deq_valid : _T_2820 ? _Queue64_UInt8_10_io_deq_valid : _T_2819 ? _Queue64_UInt8_9_io_deq_valid : _T_2818 ? _Queue64_UInt8_8_io_deq_valid : _T_2817 ? _Queue64_UInt8_7_io_deq_valid : _T_2816 ? _Queue64_UInt8_6_io_deq_valid : _T_2815 ? _Queue64_UInt8_5_io_deq_valid : _T_2814 ? _Queue64_UInt8_4_io_deq_valid : _T_2813 ? _Queue64_UInt8_3_io_deq_valid : _T_2812 ? _Queue64_UInt8_2_io_deq_valid : _T_2811 ? _Queue64_UInt8_1_io_deq_valid : _T_2810 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_107 = _remapindex_T_16 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_16 = _GEN_107[5:0]; // @[MemLoader.scala:177:54]
wire _T_2842 = remapindex_16 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2843 = remapindex_16 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2844 = remapindex_16 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2845 = remapindex_16 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2846 = remapindex_16 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2847 = remapindex_16 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2848 = remapindex_16 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2849 = remapindex_16 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2850 = remapindex_16 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2851 = remapindex_16 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2852 = remapindex_16 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2853 = remapindex_16 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2854 = remapindex_16 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2855 = remapindex_16 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2856 = remapindex_16 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2857 = remapindex_16 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2858 = remapindex_16 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2859 = remapindex_16 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2860 = remapindex_16 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2861 = remapindex_16 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2862 = remapindex_16 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2863 = remapindex_16 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2864 = remapindex_16 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2865 = remapindex_16 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2866 = remapindex_16 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2867 = remapindex_16 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2868 = remapindex_16 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2869 = remapindex_16 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2870 = remapindex_16 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2871 = remapindex_16 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2872 = remapindex_16 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2873 = remapindex_16 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_bits : _T_2872 ? _Queue64_UInt8_30_io_deq_bits : _T_2871 ? _Queue64_UInt8_29_io_deq_bits : _T_2870 ? _Queue64_UInt8_28_io_deq_bits : _T_2869 ? _Queue64_UInt8_27_io_deq_bits : _T_2868 ? _Queue64_UInt8_26_io_deq_bits : _T_2867 ? _Queue64_UInt8_25_io_deq_bits : _T_2866 ? _Queue64_UInt8_24_io_deq_bits : _T_2865 ? _Queue64_UInt8_23_io_deq_bits : _T_2864 ? _Queue64_UInt8_22_io_deq_bits : _T_2863 ? _Queue64_UInt8_21_io_deq_bits : _T_2862 ? _Queue64_UInt8_20_io_deq_bits : _T_2861 ? _Queue64_UInt8_19_io_deq_bits : _T_2860 ? _Queue64_UInt8_18_io_deq_bits : _T_2859 ? _Queue64_UInt8_17_io_deq_bits : _T_2858 ? _Queue64_UInt8_16_io_deq_bits : _T_2857 ? _Queue64_UInt8_15_io_deq_bits : _T_2856 ? _Queue64_UInt8_14_io_deq_bits : _T_2855 ? _Queue64_UInt8_13_io_deq_bits : _T_2854 ? _Queue64_UInt8_12_io_deq_bits : _T_2853 ? _Queue64_UInt8_11_io_deq_bits : _T_2852 ? _Queue64_UInt8_10_io_deq_bits : _T_2851 ? _Queue64_UInt8_9_io_deq_bits : _T_2850 ? _Queue64_UInt8_8_io_deq_bits : _T_2849 ? _Queue64_UInt8_7_io_deq_bits : _T_2848 ? _Queue64_UInt8_6_io_deq_bits : _T_2847 ? _Queue64_UInt8_5_io_deq_bits : _T_2846 ? _Queue64_UInt8_4_io_deq_bits : _T_2845 ? _Queue64_UInt8_3_io_deq_bits : _T_2844 ? _Queue64_UInt8_2_io_deq_bits : _T_2843 ? _Queue64_UInt8_1_io_deq_bits : _T_2842 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_valid : _T_2872 ? _Queue64_UInt8_30_io_deq_valid : _T_2871 ? _Queue64_UInt8_29_io_deq_valid : _T_2870 ? _Queue64_UInt8_28_io_deq_valid : _T_2869 ? _Queue64_UInt8_27_io_deq_valid : _T_2868 ? _Queue64_UInt8_26_io_deq_valid : _T_2867 ? _Queue64_UInt8_25_io_deq_valid : _T_2866 ? _Queue64_UInt8_24_io_deq_valid : _T_2865 ? _Queue64_UInt8_23_io_deq_valid : _T_2864 ? _Queue64_UInt8_22_io_deq_valid : _T_2863 ? _Queue64_UInt8_21_io_deq_valid : _T_2862 ? _Queue64_UInt8_20_io_deq_valid : _T_2861 ? _Queue64_UInt8_19_io_deq_valid : _T_2860 ? _Queue64_UInt8_18_io_deq_valid : _T_2859 ? _Queue64_UInt8_17_io_deq_valid : _T_2858 ? _Queue64_UInt8_16_io_deq_valid : _T_2857 ? _Queue64_UInt8_15_io_deq_valid : _T_2856 ? _Queue64_UInt8_14_io_deq_valid : _T_2855 ? _Queue64_UInt8_13_io_deq_valid : _T_2854 ? _Queue64_UInt8_12_io_deq_valid : _T_2853 ? _Queue64_UInt8_11_io_deq_valid : _T_2852 ? _Queue64_UInt8_10_io_deq_valid : _T_2851 ? _Queue64_UInt8_9_io_deq_valid : _T_2850 ? _Queue64_UInt8_8_io_deq_valid : _T_2849 ? _Queue64_UInt8_7_io_deq_valid : _T_2848 ? _Queue64_UInt8_6_io_deq_valid : _T_2847 ? _Queue64_UInt8_5_io_deq_valid : _T_2846 ? _Queue64_UInt8_4_io_deq_valid : _T_2845 ? _Queue64_UInt8_3_io_deq_valid : _T_2844 ? _Queue64_UInt8_2_io_deq_valid : _T_2843 ? _Queue64_UInt8_1_io_deq_valid : _T_2842 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_108 = _remapindex_T_17 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_17 = _GEN_108[5:0]; // @[MemLoader.scala:177:54]
wire _T_2874 = remapindex_17 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2875 = remapindex_17 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2876 = remapindex_17 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2877 = remapindex_17 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2878 = remapindex_17 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2879 = remapindex_17 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2880 = remapindex_17 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2881 = remapindex_17 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2882 = remapindex_17 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2883 = remapindex_17 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2884 = remapindex_17 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2885 = remapindex_17 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2886 = remapindex_17 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2887 = remapindex_17 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2888 = remapindex_17 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2889 = remapindex_17 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2890 = remapindex_17 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2891 = remapindex_17 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2892 = remapindex_17 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2893 = remapindex_17 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2894 = remapindex_17 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2895 = remapindex_17 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2896 = remapindex_17 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2897 = remapindex_17 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2898 = remapindex_17 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2899 = remapindex_17 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2900 = remapindex_17 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2901 = remapindex_17 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2902 = remapindex_17 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2903 = remapindex_17 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2904 = remapindex_17 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2905 = remapindex_17 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_bits : _T_2904 ? _Queue64_UInt8_30_io_deq_bits : _T_2903 ? _Queue64_UInt8_29_io_deq_bits : _T_2902 ? _Queue64_UInt8_28_io_deq_bits : _T_2901 ? _Queue64_UInt8_27_io_deq_bits : _T_2900 ? _Queue64_UInt8_26_io_deq_bits : _T_2899 ? _Queue64_UInt8_25_io_deq_bits : _T_2898 ? _Queue64_UInt8_24_io_deq_bits : _T_2897 ? _Queue64_UInt8_23_io_deq_bits : _T_2896 ? _Queue64_UInt8_22_io_deq_bits : _T_2895 ? _Queue64_UInt8_21_io_deq_bits : _T_2894 ? _Queue64_UInt8_20_io_deq_bits : _T_2893 ? _Queue64_UInt8_19_io_deq_bits : _T_2892 ? _Queue64_UInt8_18_io_deq_bits : _T_2891 ? _Queue64_UInt8_17_io_deq_bits : _T_2890 ? _Queue64_UInt8_16_io_deq_bits : _T_2889 ? _Queue64_UInt8_15_io_deq_bits : _T_2888 ? _Queue64_UInt8_14_io_deq_bits : _T_2887 ? _Queue64_UInt8_13_io_deq_bits : _T_2886 ? _Queue64_UInt8_12_io_deq_bits : _T_2885 ? _Queue64_UInt8_11_io_deq_bits : _T_2884 ? _Queue64_UInt8_10_io_deq_bits : _T_2883 ? _Queue64_UInt8_9_io_deq_bits : _T_2882 ? _Queue64_UInt8_8_io_deq_bits : _T_2881 ? _Queue64_UInt8_7_io_deq_bits : _T_2880 ? _Queue64_UInt8_6_io_deq_bits : _T_2879 ? _Queue64_UInt8_5_io_deq_bits : _T_2878 ? _Queue64_UInt8_4_io_deq_bits : _T_2877 ? _Queue64_UInt8_3_io_deq_bits : _T_2876 ? _Queue64_UInt8_2_io_deq_bits : _T_2875 ? _Queue64_UInt8_1_io_deq_bits : _T_2874 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_valid : _T_2904 ? _Queue64_UInt8_30_io_deq_valid : _T_2903 ? _Queue64_UInt8_29_io_deq_valid : _T_2902 ? _Queue64_UInt8_28_io_deq_valid : _T_2901 ? _Queue64_UInt8_27_io_deq_valid : _T_2900 ? _Queue64_UInt8_26_io_deq_valid : _T_2899 ? _Queue64_UInt8_25_io_deq_valid : _T_2898 ? _Queue64_UInt8_24_io_deq_valid : _T_2897 ? _Queue64_UInt8_23_io_deq_valid : _T_2896 ? _Queue64_UInt8_22_io_deq_valid : _T_2895 ? _Queue64_UInt8_21_io_deq_valid : _T_2894 ? _Queue64_UInt8_20_io_deq_valid : _T_2893 ? _Queue64_UInt8_19_io_deq_valid : _T_2892 ? _Queue64_UInt8_18_io_deq_valid : _T_2891 ? _Queue64_UInt8_17_io_deq_valid : _T_2890 ? _Queue64_UInt8_16_io_deq_valid : _T_2889 ? _Queue64_UInt8_15_io_deq_valid : _T_2888 ? _Queue64_UInt8_14_io_deq_valid : _T_2887 ? _Queue64_UInt8_13_io_deq_valid : _T_2886 ? _Queue64_UInt8_12_io_deq_valid : _T_2885 ? _Queue64_UInt8_11_io_deq_valid : _T_2884 ? _Queue64_UInt8_10_io_deq_valid : _T_2883 ? _Queue64_UInt8_9_io_deq_valid : _T_2882 ? _Queue64_UInt8_8_io_deq_valid : _T_2881 ? _Queue64_UInt8_7_io_deq_valid : _T_2880 ? _Queue64_UInt8_6_io_deq_valid : _T_2879 ? _Queue64_UInt8_5_io_deq_valid : _T_2878 ? _Queue64_UInt8_4_io_deq_valid : _T_2877 ? _Queue64_UInt8_3_io_deq_valid : _T_2876 ? _Queue64_UInt8_2_io_deq_valid : _T_2875 ? _Queue64_UInt8_1_io_deq_valid : _T_2874 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_109 = _remapindex_T_18 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_18 = _GEN_109[5:0]; // @[MemLoader.scala:177:54]
wire _T_2906 = remapindex_18 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2907 = remapindex_18 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2908 = remapindex_18 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2909 = remapindex_18 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2910 = remapindex_18 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2911 = remapindex_18 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2912 = remapindex_18 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2913 = remapindex_18 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2914 = remapindex_18 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2915 = remapindex_18 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2916 = remapindex_18 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2917 = remapindex_18 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2918 = remapindex_18 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2919 = remapindex_18 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2920 = remapindex_18 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2921 = remapindex_18 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2922 = remapindex_18 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2923 = remapindex_18 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2924 = remapindex_18 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2925 = remapindex_18 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2926 = remapindex_18 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2927 = remapindex_18 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2928 = remapindex_18 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2929 = remapindex_18 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2930 = remapindex_18 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2931 = remapindex_18 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2932 = remapindex_18 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2933 = remapindex_18 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2934 = remapindex_18 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2935 = remapindex_18 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2936 = remapindex_18 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2937 = remapindex_18 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_bits : _T_2936 ? _Queue64_UInt8_30_io_deq_bits : _T_2935 ? _Queue64_UInt8_29_io_deq_bits : _T_2934 ? _Queue64_UInt8_28_io_deq_bits : _T_2933 ? _Queue64_UInt8_27_io_deq_bits : _T_2932 ? _Queue64_UInt8_26_io_deq_bits : _T_2931 ? _Queue64_UInt8_25_io_deq_bits : _T_2930 ? _Queue64_UInt8_24_io_deq_bits : _T_2929 ? _Queue64_UInt8_23_io_deq_bits : _T_2928 ? _Queue64_UInt8_22_io_deq_bits : _T_2927 ? _Queue64_UInt8_21_io_deq_bits : _T_2926 ? _Queue64_UInt8_20_io_deq_bits : _T_2925 ? _Queue64_UInt8_19_io_deq_bits : _T_2924 ? _Queue64_UInt8_18_io_deq_bits : _T_2923 ? _Queue64_UInt8_17_io_deq_bits : _T_2922 ? _Queue64_UInt8_16_io_deq_bits : _T_2921 ? _Queue64_UInt8_15_io_deq_bits : _T_2920 ? _Queue64_UInt8_14_io_deq_bits : _T_2919 ? _Queue64_UInt8_13_io_deq_bits : _T_2918 ? _Queue64_UInt8_12_io_deq_bits : _T_2917 ? _Queue64_UInt8_11_io_deq_bits : _T_2916 ? _Queue64_UInt8_10_io_deq_bits : _T_2915 ? _Queue64_UInt8_9_io_deq_bits : _T_2914 ? _Queue64_UInt8_8_io_deq_bits : _T_2913 ? _Queue64_UInt8_7_io_deq_bits : _T_2912 ? _Queue64_UInt8_6_io_deq_bits : _T_2911 ? _Queue64_UInt8_5_io_deq_bits : _T_2910 ? _Queue64_UInt8_4_io_deq_bits : _T_2909 ? _Queue64_UInt8_3_io_deq_bits : _T_2908 ? _Queue64_UInt8_2_io_deq_bits : _T_2907 ? _Queue64_UInt8_1_io_deq_bits : _T_2906 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_valid : _T_2936 ? _Queue64_UInt8_30_io_deq_valid : _T_2935 ? _Queue64_UInt8_29_io_deq_valid : _T_2934 ? _Queue64_UInt8_28_io_deq_valid : _T_2933 ? _Queue64_UInt8_27_io_deq_valid : _T_2932 ? _Queue64_UInt8_26_io_deq_valid : _T_2931 ? _Queue64_UInt8_25_io_deq_valid : _T_2930 ? _Queue64_UInt8_24_io_deq_valid : _T_2929 ? _Queue64_UInt8_23_io_deq_valid : _T_2928 ? _Queue64_UInt8_22_io_deq_valid : _T_2927 ? _Queue64_UInt8_21_io_deq_valid : _T_2926 ? _Queue64_UInt8_20_io_deq_valid : _T_2925 ? _Queue64_UInt8_19_io_deq_valid : _T_2924 ? _Queue64_UInt8_18_io_deq_valid : _T_2923 ? _Queue64_UInt8_17_io_deq_valid : _T_2922 ? _Queue64_UInt8_16_io_deq_valid : _T_2921 ? _Queue64_UInt8_15_io_deq_valid : _T_2920 ? _Queue64_UInt8_14_io_deq_valid : _T_2919 ? _Queue64_UInt8_13_io_deq_valid : _T_2918 ? _Queue64_UInt8_12_io_deq_valid : _T_2917 ? _Queue64_UInt8_11_io_deq_valid : _T_2916 ? _Queue64_UInt8_10_io_deq_valid : _T_2915 ? _Queue64_UInt8_9_io_deq_valid : _T_2914 ? _Queue64_UInt8_8_io_deq_valid : _T_2913 ? _Queue64_UInt8_7_io_deq_valid : _T_2912 ? _Queue64_UInt8_6_io_deq_valid : _T_2911 ? _Queue64_UInt8_5_io_deq_valid : _T_2910 ? _Queue64_UInt8_4_io_deq_valid : _T_2909 ? _Queue64_UInt8_3_io_deq_valid : _T_2908 ? _Queue64_UInt8_2_io_deq_valid : _T_2907 ? _Queue64_UInt8_1_io_deq_valid : _T_2906 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_110 = _remapindex_T_19 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_19 = _GEN_110[5:0]; // @[MemLoader.scala:177:54]
wire _T_2938 = remapindex_19 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2939 = remapindex_19 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2940 = remapindex_19 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2941 = remapindex_19 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2942 = remapindex_19 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2943 = remapindex_19 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2944 = remapindex_19 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2945 = remapindex_19 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2946 = remapindex_19 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2947 = remapindex_19 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2948 = remapindex_19 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2949 = remapindex_19 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2950 = remapindex_19 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2951 = remapindex_19 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2952 = remapindex_19 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2953 = remapindex_19 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2954 = remapindex_19 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2955 = remapindex_19 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2956 = remapindex_19 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2957 = remapindex_19 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2958 = remapindex_19 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2959 = remapindex_19 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2960 = remapindex_19 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2961 = remapindex_19 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2962 = remapindex_19 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2963 = remapindex_19 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2964 = remapindex_19 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2965 = remapindex_19 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2966 = remapindex_19 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2967 = remapindex_19 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2968 = remapindex_19 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2969 = remapindex_19 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_bits : _T_2968 ? _Queue64_UInt8_30_io_deq_bits : _T_2967 ? _Queue64_UInt8_29_io_deq_bits : _T_2966 ? _Queue64_UInt8_28_io_deq_bits : _T_2965 ? _Queue64_UInt8_27_io_deq_bits : _T_2964 ? _Queue64_UInt8_26_io_deq_bits : _T_2963 ? _Queue64_UInt8_25_io_deq_bits : _T_2962 ? _Queue64_UInt8_24_io_deq_bits : _T_2961 ? _Queue64_UInt8_23_io_deq_bits : _T_2960 ? _Queue64_UInt8_22_io_deq_bits : _T_2959 ? _Queue64_UInt8_21_io_deq_bits : _T_2958 ? _Queue64_UInt8_20_io_deq_bits : _T_2957 ? _Queue64_UInt8_19_io_deq_bits : _T_2956 ? _Queue64_UInt8_18_io_deq_bits : _T_2955 ? _Queue64_UInt8_17_io_deq_bits : _T_2954 ? _Queue64_UInt8_16_io_deq_bits : _T_2953 ? _Queue64_UInt8_15_io_deq_bits : _T_2952 ? _Queue64_UInt8_14_io_deq_bits : _T_2951 ? _Queue64_UInt8_13_io_deq_bits : _T_2950 ? _Queue64_UInt8_12_io_deq_bits : _T_2949 ? _Queue64_UInt8_11_io_deq_bits : _T_2948 ? _Queue64_UInt8_10_io_deq_bits : _T_2947 ? _Queue64_UInt8_9_io_deq_bits : _T_2946 ? _Queue64_UInt8_8_io_deq_bits : _T_2945 ? _Queue64_UInt8_7_io_deq_bits : _T_2944 ? _Queue64_UInt8_6_io_deq_bits : _T_2943 ? _Queue64_UInt8_5_io_deq_bits : _T_2942 ? _Queue64_UInt8_4_io_deq_bits : _T_2941 ? _Queue64_UInt8_3_io_deq_bits : _T_2940 ? _Queue64_UInt8_2_io_deq_bits : _T_2939 ? _Queue64_UInt8_1_io_deq_bits : _T_2938 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_valid : _T_2968 ? _Queue64_UInt8_30_io_deq_valid : _T_2967 ? _Queue64_UInt8_29_io_deq_valid : _T_2966 ? _Queue64_UInt8_28_io_deq_valid : _T_2965 ? _Queue64_UInt8_27_io_deq_valid : _T_2964 ? _Queue64_UInt8_26_io_deq_valid : _T_2963 ? _Queue64_UInt8_25_io_deq_valid : _T_2962 ? _Queue64_UInt8_24_io_deq_valid : _T_2961 ? _Queue64_UInt8_23_io_deq_valid : _T_2960 ? _Queue64_UInt8_22_io_deq_valid : _T_2959 ? _Queue64_UInt8_21_io_deq_valid : _T_2958 ? _Queue64_UInt8_20_io_deq_valid : _T_2957 ? _Queue64_UInt8_19_io_deq_valid : _T_2956 ? _Queue64_UInt8_18_io_deq_valid : _T_2955 ? _Queue64_UInt8_17_io_deq_valid : _T_2954 ? _Queue64_UInt8_16_io_deq_valid : _T_2953 ? _Queue64_UInt8_15_io_deq_valid : _T_2952 ? _Queue64_UInt8_14_io_deq_valid : _T_2951 ? _Queue64_UInt8_13_io_deq_valid : _T_2950 ? _Queue64_UInt8_12_io_deq_valid : _T_2949 ? _Queue64_UInt8_11_io_deq_valid : _T_2948 ? _Queue64_UInt8_10_io_deq_valid : _T_2947 ? _Queue64_UInt8_9_io_deq_valid : _T_2946 ? _Queue64_UInt8_8_io_deq_valid : _T_2945 ? _Queue64_UInt8_7_io_deq_valid : _T_2944 ? _Queue64_UInt8_6_io_deq_valid : _T_2943 ? _Queue64_UInt8_5_io_deq_valid : _T_2942 ? _Queue64_UInt8_4_io_deq_valid : _T_2941 ? _Queue64_UInt8_3_io_deq_valid : _T_2940 ? _Queue64_UInt8_2_io_deq_valid : _T_2939 ? _Queue64_UInt8_1_io_deq_valid : _T_2938 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_111 = _remapindex_T_20 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_20 = _GEN_111[5:0]; // @[MemLoader.scala:177:54]
wire _T_2970 = remapindex_20 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2971 = remapindex_20 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2972 = remapindex_20 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2973 = remapindex_20 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2974 = remapindex_20 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2975 = remapindex_20 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2976 = remapindex_20 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2977 = remapindex_20 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2978 = remapindex_20 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2979 = remapindex_20 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2980 = remapindex_20 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2981 = remapindex_20 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2982 = remapindex_20 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2983 = remapindex_20 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2984 = remapindex_20 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2985 = remapindex_20 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2986 = remapindex_20 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2987 = remapindex_20 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2988 = remapindex_20 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2989 = remapindex_20 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2990 = remapindex_20 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2991 = remapindex_20 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2992 = remapindex_20 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2993 = remapindex_20 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2994 = remapindex_20 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2995 = remapindex_20 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2996 = remapindex_20 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2997 = remapindex_20 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2998 = remapindex_20 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2999 = remapindex_20 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3000 = remapindex_20 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3001 = remapindex_20 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_bits : _T_3000 ? _Queue64_UInt8_30_io_deq_bits : _T_2999 ? _Queue64_UInt8_29_io_deq_bits : _T_2998 ? _Queue64_UInt8_28_io_deq_bits : _T_2997 ? _Queue64_UInt8_27_io_deq_bits : _T_2996 ? _Queue64_UInt8_26_io_deq_bits : _T_2995 ? _Queue64_UInt8_25_io_deq_bits : _T_2994 ? _Queue64_UInt8_24_io_deq_bits : _T_2993 ? _Queue64_UInt8_23_io_deq_bits : _T_2992 ? _Queue64_UInt8_22_io_deq_bits : _T_2991 ? _Queue64_UInt8_21_io_deq_bits : _T_2990 ? _Queue64_UInt8_20_io_deq_bits : _T_2989 ? _Queue64_UInt8_19_io_deq_bits : _T_2988 ? _Queue64_UInt8_18_io_deq_bits : _T_2987 ? _Queue64_UInt8_17_io_deq_bits : _T_2986 ? _Queue64_UInt8_16_io_deq_bits : _T_2985 ? _Queue64_UInt8_15_io_deq_bits : _T_2984 ? _Queue64_UInt8_14_io_deq_bits : _T_2983 ? _Queue64_UInt8_13_io_deq_bits : _T_2982 ? _Queue64_UInt8_12_io_deq_bits : _T_2981 ? _Queue64_UInt8_11_io_deq_bits : _T_2980 ? _Queue64_UInt8_10_io_deq_bits : _T_2979 ? _Queue64_UInt8_9_io_deq_bits : _T_2978 ? _Queue64_UInt8_8_io_deq_bits : _T_2977 ? _Queue64_UInt8_7_io_deq_bits : _T_2976 ? _Queue64_UInt8_6_io_deq_bits : _T_2975 ? _Queue64_UInt8_5_io_deq_bits : _T_2974 ? _Queue64_UInt8_4_io_deq_bits : _T_2973 ? _Queue64_UInt8_3_io_deq_bits : _T_2972 ? _Queue64_UInt8_2_io_deq_bits : _T_2971 ? _Queue64_UInt8_1_io_deq_bits : _T_2970 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_valid : _T_3000 ? _Queue64_UInt8_30_io_deq_valid : _T_2999 ? _Queue64_UInt8_29_io_deq_valid : _T_2998 ? _Queue64_UInt8_28_io_deq_valid : _T_2997 ? _Queue64_UInt8_27_io_deq_valid : _T_2996 ? _Queue64_UInt8_26_io_deq_valid : _T_2995 ? _Queue64_UInt8_25_io_deq_valid : _T_2994 ? _Queue64_UInt8_24_io_deq_valid : _T_2993 ? _Queue64_UInt8_23_io_deq_valid : _T_2992 ? _Queue64_UInt8_22_io_deq_valid : _T_2991 ? _Queue64_UInt8_21_io_deq_valid : _T_2990 ? _Queue64_UInt8_20_io_deq_valid : _T_2989 ? _Queue64_UInt8_19_io_deq_valid : _T_2988 ? _Queue64_UInt8_18_io_deq_valid : _T_2987 ? _Queue64_UInt8_17_io_deq_valid : _T_2986 ? _Queue64_UInt8_16_io_deq_valid : _T_2985 ? _Queue64_UInt8_15_io_deq_valid : _T_2984 ? _Queue64_UInt8_14_io_deq_valid : _T_2983 ? _Queue64_UInt8_13_io_deq_valid : _T_2982 ? _Queue64_UInt8_12_io_deq_valid : _T_2981 ? _Queue64_UInt8_11_io_deq_valid : _T_2980 ? _Queue64_UInt8_10_io_deq_valid : _T_2979 ? _Queue64_UInt8_9_io_deq_valid : _T_2978 ? _Queue64_UInt8_8_io_deq_valid : _T_2977 ? _Queue64_UInt8_7_io_deq_valid : _T_2976 ? _Queue64_UInt8_6_io_deq_valid : _T_2975 ? _Queue64_UInt8_5_io_deq_valid : _T_2974 ? _Queue64_UInt8_4_io_deq_valid : _T_2973 ? _Queue64_UInt8_3_io_deq_valid : _T_2972 ? _Queue64_UInt8_2_io_deq_valid : _T_2971 ? _Queue64_UInt8_1_io_deq_valid : _T_2970 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_112 = _remapindex_T_21 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_21 = _GEN_112[5:0]; // @[MemLoader.scala:177:54]
wire _T_3002 = remapindex_21 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3003 = remapindex_21 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3004 = remapindex_21 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3005 = remapindex_21 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3006 = remapindex_21 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3007 = remapindex_21 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3008 = remapindex_21 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3009 = remapindex_21 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3010 = remapindex_21 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3011 = remapindex_21 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3012 = remapindex_21 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3013 = remapindex_21 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3014 = remapindex_21 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3015 = remapindex_21 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3016 = remapindex_21 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3017 = remapindex_21 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3018 = remapindex_21 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3019 = remapindex_21 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3020 = remapindex_21 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3021 = remapindex_21 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3022 = remapindex_21 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3023 = remapindex_21 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3024 = remapindex_21 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3025 = remapindex_21 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3026 = remapindex_21 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3027 = remapindex_21 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3028 = remapindex_21 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3029 = remapindex_21 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3030 = remapindex_21 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3031 = remapindex_21 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3032 = remapindex_21 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3033 = remapindex_21 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_bits : _T_3032 ? _Queue64_UInt8_30_io_deq_bits : _T_3031 ? _Queue64_UInt8_29_io_deq_bits : _T_3030 ? _Queue64_UInt8_28_io_deq_bits : _T_3029 ? _Queue64_UInt8_27_io_deq_bits : _T_3028 ? _Queue64_UInt8_26_io_deq_bits : _T_3027 ? _Queue64_UInt8_25_io_deq_bits : _T_3026 ? _Queue64_UInt8_24_io_deq_bits : _T_3025 ? _Queue64_UInt8_23_io_deq_bits : _T_3024 ? _Queue64_UInt8_22_io_deq_bits : _T_3023 ? _Queue64_UInt8_21_io_deq_bits : _T_3022 ? _Queue64_UInt8_20_io_deq_bits : _T_3021 ? _Queue64_UInt8_19_io_deq_bits : _T_3020 ? _Queue64_UInt8_18_io_deq_bits : _T_3019 ? _Queue64_UInt8_17_io_deq_bits : _T_3018 ? _Queue64_UInt8_16_io_deq_bits : _T_3017 ? _Queue64_UInt8_15_io_deq_bits : _T_3016 ? _Queue64_UInt8_14_io_deq_bits : _T_3015 ? _Queue64_UInt8_13_io_deq_bits : _T_3014 ? _Queue64_UInt8_12_io_deq_bits : _T_3013 ? _Queue64_UInt8_11_io_deq_bits : _T_3012 ? _Queue64_UInt8_10_io_deq_bits : _T_3011 ? _Queue64_UInt8_9_io_deq_bits : _T_3010 ? _Queue64_UInt8_8_io_deq_bits : _T_3009 ? _Queue64_UInt8_7_io_deq_bits : _T_3008 ? _Queue64_UInt8_6_io_deq_bits : _T_3007 ? _Queue64_UInt8_5_io_deq_bits : _T_3006 ? _Queue64_UInt8_4_io_deq_bits : _T_3005 ? _Queue64_UInt8_3_io_deq_bits : _T_3004 ? _Queue64_UInt8_2_io_deq_bits : _T_3003 ? _Queue64_UInt8_1_io_deq_bits : _T_3002 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_valid : _T_3032 ? _Queue64_UInt8_30_io_deq_valid : _T_3031 ? _Queue64_UInt8_29_io_deq_valid : _T_3030 ? _Queue64_UInt8_28_io_deq_valid : _T_3029 ? _Queue64_UInt8_27_io_deq_valid : _T_3028 ? _Queue64_UInt8_26_io_deq_valid : _T_3027 ? _Queue64_UInt8_25_io_deq_valid : _T_3026 ? _Queue64_UInt8_24_io_deq_valid : _T_3025 ? _Queue64_UInt8_23_io_deq_valid : _T_3024 ? _Queue64_UInt8_22_io_deq_valid : _T_3023 ? _Queue64_UInt8_21_io_deq_valid : _T_3022 ? _Queue64_UInt8_20_io_deq_valid : _T_3021 ? _Queue64_UInt8_19_io_deq_valid : _T_3020 ? _Queue64_UInt8_18_io_deq_valid : _T_3019 ? _Queue64_UInt8_17_io_deq_valid : _T_3018 ? _Queue64_UInt8_16_io_deq_valid : _T_3017 ? _Queue64_UInt8_15_io_deq_valid : _T_3016 ? _Queue64_UInt8_14_io_deq_valid : _T_3015 ? _Queue64_UInt8_13_io_deq_valid : _T_3014 ? _Queue64_UInt8_12_io_deq_valid : _T_3013 ? _Queue64_UInt8_11_io_deq_valid : _T_3012 ? _Queue64_UInt8_10_io_deq_valid : _T_3011 ? _Queue64_UInt8_9_io_deq_valid : _T_3010 ? _Queue64_UInt8_8_io_deq_valid : _T_3009 ? _Queue64_UInt8_7_io_deq_valid : _T_3008 ? _Queue64_UInt8_6_io_deq_valid : _T_3007 ? _Queue64_UInt8_5_io_deq_valid : _T_3006 ? _Queue64_UInt8_4_io_deq_valid : _T_3005 ? _Queue64_UInt8_3_io_deq_valid : _T_3004 ? _Queue64_UInt8_2_io_deq_valid : _T_3003 ? _Queue64_UInt8_1_io_deq_valid : _T_3002 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_113 = _remapindex_T_22 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_22 = _GEN_113[5:0]; // @[MemLoader.scala:177:54]
wire _T_3034 = remapindex_22 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3035 = remapindex_22 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3036 = remapindex_22 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3037 = remapindex_22 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3038 = remapindex_22 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3039 = remapindex_22 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3040 = remapindex_22 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3041 = remapindex_22 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3042 = remapindex_22 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3043 = remapindex_22 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3044 = remapindex_22 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3045 = remapindex_22 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3046 = remapindex_22 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3047 = remapindex_22 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3048 = remapindex_22 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3049 = remapindex_22 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3050 = remapindex_22 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3051 = remapindex_22 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3052 = remapindex_22 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3053 = remapindex_22 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3054 = remapindex_22 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3055 = remapindex_22 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3056 = remapindex_22 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3057 = remapindex_22 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3058 = remapindex_22 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3059 = remapindex_22 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3060 = remapindex_22 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3061 = remapindex_22 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3062 = remapindex_22 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3063 = remapindex_22 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3064 = remapindex_22 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3065 = remapindex_22 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_bits : _T_3064 ? _Queue64_UInt8_30_io_deq_bits : _T_3063 ? _Queue64_UInt8_29_io_deq_bits : _T_3062 ? _Queue64_UInt8_28_io_deq_bits : _T_3061 ? _Queue64_UInt8_27_io_deq_bits : _T_3060 ? _Queue64_UInt8_26_io_deq_bits : _T_3059 ? _Queue64_UInt8_25_io_deq_bits : _T_3058 ? _Queue64_UInt8_24_io_deq_bits : _T_3057 ? _Queue64_UInt8_23_io_deq_bits : _T_3056 ? _Queue64_UInt8_22_io_deq_bits : _T_3055 ? _Queue64_UInt8_21_io_deq_bits : _T_3054 ? _Queue64_UInt8_20_io_deq_bits : _T_3053 ? _Queue64_UInt8_19_io_deq_bits : _T_3052 ? _Queue64_UInt8_18_io_deq_bits : _T_3051 ? _Queue64_UInt8_17_io_deq_bits : _T_3050 ? _Queue64_UInt8_16_io_deq_bits : _T_3049 ? _Queue64_UInt8_15_io_deq_bits : _T_3048 ? _Queue64_UInt8_14_io_deq_bits : _T_3047 ? _Queue64_UInt8_13_io_deq_bits : _T_3046 ? _Queue64_UInt8_12_io_deq_bits : _T_3045 ? _Queue64_UInt8_11_io_deq_bits : _T_3044 ? _Queue64_UInt8_10_io_deq_bits : _T_3043 ? _Queue64_UInt8_9_io_deq_bits : _T_3042 ? _Queue64_UInt8_8_io_deq_bits : _T_3041 ? _Queue64_UInt8_7_io_deq_bits : _T_3040 ? _Queue64_UInt8_6_io_deq_bits : _T_3039 ? _Queue64_UInt8_5_io_deq_bits : _T_3038 ? _Queue64_UInt8_4_io_deq_bits : _T_3037 ? _Queue64_UInt8_3_io_deq_bits : _T_3036 ? _Queue64_UInt8_2_io_deq_bits : _T_3035 ? _Queue64_UInt8_1_io_deq_bits : _T_3034 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_valid : _T_3064 ? _Queue64_UInt8_30_io_deq_valid : _T_3063 ? _Queue64_UInt8_29_io_deq_valid : _T_3062 ? _Queue64_UInt8_28_io_deq_valid : _T_3061 ? _Queue64_UInt8_27_io_deq_valid : _T_3060 ? _Queue64_UInt8_26_io_deq_valid : _T_3059 ? _Queue64_UInt8_25_io_deq_valid : _T_3058 ? _Queue64_UInt8_24_io_deq_valid : _T_3057 ? _Queue64_UInt8_23_io_deq_valid : _T_3056 ? _Queue64_UInt8_22_io_deq_valid : _T_3055 ? _Queue64_UInt8_21_io_deq_valid : _T_3054 ? _Queue64_UInt8_20_io_deq_valid : _T_3053 ? _Queue64_UInt8_19_io_deq_valid : _T_3052 ? _Queue64_UInt8_18_io_deq_valid : _T_3051 ? _Queue64_UInt8_17_io_deq_valid : _T_3050 ? _Queue64_UInt8_16_io_deq_valid : _T_3049 ? _Queue64_UInt8_15_io_deq_valid : _T_3048 ? _Queue64_UInt8_14_io_deq_valid : _T_3047 ? _Queue64_UInt8_13_io_deq_valid : _T_3046 ? _Queue64_UInt8_12_io_deq_valid : _T_3045 ? _Queue64_UInt8_11_io_deq_valid : _T_3044 ? _Queue64_UInt8_10_io_deq_valid : _T_3043 ? _Queue64_UInt8_9_io_deq_valid : _T_3042 ? _Queue64_UInt8_8_io_deq_valid : _T_3041 ? _Queue64_UInt8_7_io_deq_valid : _T_3040 ? _Queue64_UInt8_6_io_deq_valid : _T_3039 ? _Queue64_UInt8_5_io_deq_valid : _T_3038 ? _Queue64_UInt8_4_io_deq_valid : _T_3037 ? _Queue64_UInt8_3_io_deq_valid : _T_3036 ? _Queue64_UInt8_2_io_deq_valid : _T_3035 ? _Queue64_UInt8_1_io_deq_valid : _T_3034 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_114 = _remapindex_T_23 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_23 = _GEN_114[5:0]; // @[MemLoader.scala:177:54]
wire _T_3066 = remapindex_23 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3067 = remapindex_23 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3068 = remapindex_23 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3069 = remapindex_23 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3070 = remapindex_23 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3071 = remapindex_23 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3072 = remapindex_23 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3073 = remapindex_23 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3074 = remapindex_23 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3075 = remapindex_23 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3076 = remapindex_23 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3077 = remapindex_23 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3078 = remapindex_23 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3079 = remapindex_23 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3080 = remapindex_23 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3081 = remapindex_23 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3082 = remapindex_23 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3083 = remapindex_23 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3084 = remapindex_23 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3085 = remapindex_23 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3086 = remapindex_23 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3087 = remapindex_23 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3088 = remapindex_23 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3089 = remapindex_23 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3090 = remapindex_23 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3091 = remapindex_23 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3092 = remapindex_23 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3093 = remapindex_23 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3094 = remapindex_23 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3095 = remapindex_23 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3096 = remapindex_23 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3097 = remapindex_23 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_bits : _T_3096 ? _Queue64_UInt8_30_io_deq_bits : _T_3095 ? _Queue64_UInt8_29_io_deq_bits : _T_3094 ? _Queue64_UInt8_28_io_deq_bits : _T_3093 ? _Queue64_UInt8_27_io_deq_bits : _T_3092 ? _Queue64_UInt8_26_io_deq_bits : _T_3091 ? _Queue64_UInt8_25_io_deq_bits : _T_3090 ? _Queue64_UInt8_24_io_deq_bits : _T_3089 ? _Queue64_UInt8_23_io_deq_bits : _T_3088 ? _Queue64_UInt8_22_io_deq_bits : _T_3087 ? _Queue64_UInt8_21_io_deq_bits : _T_3086 ? _Queue64_UInt8_20_io_deq_bits : _T_3085 ? _Queue64_UInt8_19_io_deq_bits : _T_3084 ? _Queue64_UInt8_18_io_deq_bits : _T_3083 ? _Queue64_UInt8_17_io_deq_bits : _T_3082 ? _Queue64_UInt8_16_io_deq_bits : _T_3081 ? _Queue64_UInt8_15_io_deq_bits : _T_3080 ? _Queue64_UInt8_14_io_deq_bits : _T_3079 ? _Queue64_UInt8_13_io_deq_bits : _T_3078 ? _Queue64_UInt8_12_io_deq_bits : _T_3077 ? _Queue64_UInt8_11_io_deq_bits : _T_3076 ? _Queue64_UInt8_10_io_deq_bits : _T_3075 ? _Queue64_UInt8_9_io_deq_bits : _T_3074 ? _Queue64_UInt8_8_io_deq_bits : _T_3073 ? _Queue64_UInt8_7_io_deq_bits : _T_3072 ? _Queue64_UInt8_6_io_deq_bits : _T_3071 ? _Queue64_UInt8_5_io_deq_bits : _T_3070 ? _Queue64_UInt8_4_io_deq_bits : _T_3069 ? _Queue64_UInt8_3_io_deq_bits : _T_3068 ? _Queue64_UInt8_2_io_deq_bits : _T_3067 ? _Queue64_UInt8_1_io_deq_bits : _T_3066 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_valid : _T_3096 ? _Queue64_UInt8_30_io_deq_valid : _T_3095 ? _Queue64_UInt8_29_io_deq_valid : _T_3094 ? _Queue64_UInt8_28_io_deq_valid : _T_3093 ? _Queue64_UInt8_27_io_deq_valid : _T_3092 ? _Queue64_UInt8_26_io_deq_valid : _T_3091 ? _Queue64_UInt8_25_io_deq_valid : _T_3090 ? _Queue64_UInt8_24_io_deq_valid : _T_3089 ? _Queue64_UInt8_23_io_deq_valid : _T_3088 ? _Queue64_UInt8_22_io_deq_valid : _T_3087 ? _Queue64_UInt8_21_io_deq_valid : _T_3086 ? _Queue64_UInt8_20_io_deq_valid : _T_3085 ? _Queue64_UInt8_19_io_deq_valid : _T_3084 ? _Queue64_UInt8_18_io_deq_valid : _T_3083 ? _Queue64_UInt8_17_io_deq_valid : _T_3082 ? _Queue64_UInt8_16_io_deq_valid : _T_3081 ? _Queue64_UInt8_15_io_deq_valid : _T_3080 ? _Queue64_UInt8_14_io_deq_valid : _T_3079 ? _Queue64_UInt8_13_io_deq_valid : _T_3078 ? _Queue64_UInt8_12_io_deq_valid : _T_3077 ? _Queue64_UInt8_11_io_deq_valid : _T_3076 ? _Queue64_UInt8_10_io_deq_valid : _T_3075 ? _Queue64_UInt8_9_io_deq_valid : _T_3074 ? _Queue64_UInt8_8_io_deq_valid : _T_3073 ? _Queue64_UInt8_7_io_deq_valid : _T_3072 ? _Queue64_UInt8_6_io_deq_valid : _T_3071 ? _Queue64_UInt8_5_io_deq_valid : _T_3070 ? _Queue64_UInt8_4_io_deq_valid : _T_3069 ? _Queue64_UInt8_3_io_deq_valid : _T_3068 ? _Queue64_UInt8_2_io_deq_valid : _T_3067 ? _Queue64_UInt8_1_io_deq_valid : _T_3066 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_115 = _remapindex_T_24 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_24 = _GEN_115[5:0]; // @[MemLoader.scala:177:54]
wire _T_3098 = remapindex_24 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3099 = remapindex_24 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3100 = remapindex_24 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3101 = remapindex_24 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3102 = remapindex_24 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3103 = remapindex_24 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3104 = remapindex_24 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3105 = remapindex_24 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3106 = remapindex_24 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3107 = remapindex_24 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3108 = remapindex_24 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3109 = remapindex_24 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3110 = remapindex_24 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3111 = remapindex_24 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3112 = remapindex_24 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3113 = remapindex_24 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3114 = remapindex_24 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3115 = remapindex_24 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3116 = remapindex_24 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3117 = remapindex_24 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3118 = remapindex_24 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3119 = remapindex_24 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3120 = remapindex_24 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3121 = remapindex_24 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3122 = remapindex_24 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3123 = remapindex_24 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3124 = remapindex_24 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3125 = remapindex_24 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3126 = remapindex_24 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3127 = remapindex_24 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3128 = remapindex_24 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3129 = remapindex_24 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_bits : _T_3128 ? _Queue64_UInt8_30_io_deq_bits : _T_3127 ? _Queue64_UInt8_29_io_deq_bits : _T_3126 ? _Queue64_UInt8_28_io_deq_bits : _T_3125 ? _Queue64_UInt8_27_io_deq_bits : _T_3124 ? _Queue64_UInt8_26_io_deq_bits : _T_3123 ? _Queue64_UInt8_25_io_deq_bits : _T_3122 ? _Queue64_UInt8_24_io_deq_bits : _T_3121 ? _Queue64_UInt8_23_io_deq_bits : _T_3120 ? _Queue64_UInt8_22_io_deq_bits : _T_3119 ? _Queue64_UInt8_21_io_deq_bits : _T_3118 ? _Queue64_UInt8_20_io_deq_bits : _T_3117 ? _Queue64_UInt8_19_io_deq_bits : _T_3116 ? _Queue64_UInt8_18_io_deq_bits : _T_3115 ? _Queue64_UInt8_17_io_deq_bits : _T_3114 ? _Queue64_UInt8_16_io_deq_bits : _T_3113 ? _Queue64_UInt8_15_io_deq_bits : _T_3112 ? _Queue64_UInt8_14_io_deq_bits : _T_3111 ? _Queue64_UInt8_13_io_deq_bits : _T_3110 ? _Queue64_UInt8_12_io_deq_bits : _T_3109 ? _Queue64_UInt8_11_io_deq_bits : _T_3108 ? _Queue64_UInt8_10_io_deq_bits : _T_3107 ? _Queue64_UInt8_9_io_deq_bits : _T_3106 ? _Queue64_UInt8_8_io_deq_bits : _T_3105 ? _Queue64_UInt8_7_io_deq_bits : _T_3104 ? _Queue64_UInt8_6_io_deq_bits : _T_3103 ? _Queue64_UInt8_5_io_deq_bits : _T_3102 ? _Queue64_UInt8_4_io_deq_bits : _T_3101 ? _Queue64_UInt8_3_io_deq_bits : _T_3100 ? _Queue64_UInt8_2_io_deq_bits : _T_3099 ? _Queue64_UInt8_1_io_deq_bits : _T_3098 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_valid : _T_3128 ? _Queue64_UInt8_30_io_deq_valid : _T_3127 ? _Queue64_UInt8_29_io_deq_valid : _T_3126 ? _Queue64_UInt8_28_io_deq_valid : _T_3125 ? _Queue64_UInt8_27_io_deq_valid : _T_3124 ? _Queue64_UInt8_26_io_deq_valid : _T_3123 ? _Queue64_UInt8_25_io_deq_valid : _T_3122 ? _Queue64_UInt8_24_io_deq_valid : _T_3121 ? _Queue64_UInt8_23_io_deq_valid : _T_3120 ? _Queue64_UInt8_22_io_deq_valid : _T_3119 ? _Queue64_UInt8_21_io_deq_valid : _T_3118 ? _Queue64_UInt8_20_io_deq_valid : _T_3117 ? _Queue64_UInt8_19_io_deq_valid : _T_3116 ? _Queue64_UInt8_18_io_deq_valid : _T_3115 ? _Queue64_UInt8_17_io_deq_valid : _T_3114 ? _Queue64_UInt8_16_io_deq_valid : _T_3113 ? _Queue64_UInt8_15_io_deq_valid : _T_3112 ? _Queue64_UInt8_14_io_deq_valid : _T_3111 ? _Queue64_UInt8_13_io_deq_valid : _T_3110 ? _Queue64_UInt8_12_io_deq_valid : _T_3109 ? _Queue64_UInt8_11_io_deq_valid : _T_3108 ? _Queue64_UInt8_10_io_deq_valid : _T_3107 ? _Queue64_UInt8_9_io_deq_valid : _T_3106 ? _Queue64_UInt8_8_io_deq_valid : _T_3105 ? _Queue64_UInt8_7_io_deq_valid : _T_3104 ? _Queue64_UInt8_6_io_deq_valid : _T_3103 ? _Queue64_UInt8_5_io_deq_valid : _T_3102 ? _Queue64_UInt8_4_io_deq_valid : _T_3101 ? _Queue64_UInt8_3_io_deq_valid : _T_3100 ? _Queue64_UInt8_2_io_deq_valid : _T_3099 ? _Queue64_UInt8_1_io_deq_valid : _T_3098 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_116 = _remapindex_T_25 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_25 = _GEN_116[5:0]; // @[MemLoader.scala:177:54]
wire _T_3130 = remapindex_25 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3131 = remapindex_25 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3132 = remapindex_25 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3133 = remapindex_25 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3134 = remapindex_25 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3135 = remapindex_25 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3136 = remapindex_25 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3137 = remapindex_25 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3138 = remapindex_25 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3139 = remapindex_25 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3140 = remapindex_25 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3141 = remapindex_25 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3142 = remapindex_25 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3143 = remapindex_25 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3144 = remapindex_25 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3145 = remapindex_25 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3146 = remapindex_25 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3147 = remapindex_25 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3148 = remapindex_25 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3149 = remapindex_25 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3150 = remapindex_25 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3151 = remapindex_25 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3152 = remapindex_25 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3153 = remapindex_25 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3154 = remapindex_25 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3155 = remapindex_25 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3156 = remapindex_25 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3157 = remapindex_25 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3158 = remapindex_25 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3159 = remapindex_25 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3160 = remapindex_25 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3161 = remapindex_25 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_bits : _T_3160 ? _Queue64_UInt8_30_io_deq_bits : _T_3159 ? _Queue64_UInt8_29_io_deq_bits : _T_3158 ? _Queue64_UInt8_28_io_deq_bits : _T_3157 ? _Queue64_UInt8_27_io_deq_bits : _T_3156 ? _Queue64_UInt8_26_io_deq_bits : _T_3155 ? _Queue64_UInt8_25_io_deq_bits : _T_3154 ? _Queue64_UInt8_24_io_deq_bits : _T_3153 ? _Queue64_UInt8_23_io_deq_bits : _T_3152 ? _Queue64_UInt8_22_io_deq_bits : _T_3151 ? _Queue64_UInt8_21_io_deq_bits : _T_3150 ? _Queue64_UInt8_20_io_deq_bits : _T_3149 ? _Queue64_UInt8_19_io_deq_bits : _T_3148 ? _Queue64_UInt8_18_io_deq_bits : _T_3147 ? _Queue64_UInt8_17_io_deq_bits : _T_3146 ? _Queue64_UInt8_16_io_deq_bits : _T_3145 ? _Queue64_UInt8_15_io_deq_bits : _T_3144 ? _Queue64_UInt8_14_io_deq_bits : _T_3143 ? _Queue64_UInt8_13_io_deq_bits : _T_3142 ? _Queue64_UInt8_12_io_deq_bits : _T_3141 ? _Queue64_UInt8_11_io_deq_bits : _T_3140 ? _Queue64_UInt8_10_io_deq_bits : _T_3139 ? _Queue64_UInt8_9_io_deq_bits : _T_3138 ? _Queue64_UInt8_8_io_deq_bits : _T_3137 ? _Queue64_UInt8_7_io_deq_bits : _T_3136 ? _Queue64_UInt8_6_io_deq_bits : _T_3135 ? _Queue64_UInt8_5_io_deq_bits : _T_3134 ? _Queue64_UInt8_4_io_deq_bits : _T_3133 ? _Queue64_UInt8_3_io_deq_bits : _T_3132 ? _Queue64_UInt8_2_io_deq_bits : _T_3131 ? _Queue64_UInt8_1_io_deq_bits : _T_3130 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_valid : _T_3160 ? _Queue64_UInt8_30_io_deq_valid : _T_3159 ? _Queue64_UInt8_29_io_deq_valid : _T_3158 ? _Queue64_UInt8_28_io_deq_valid : _T_3157 ? _Queue64_UInt8_27_io_deq_valid : _T_3156 ? _Queue64_UInt8_26_io_deq_valid : _T_3155 ? _Queue64_UInt8_25_io_deq_valid : _T_3154 ? _Queue64_UInt8_24_io_deq_valid : _T_3153 ? _Queue64_UInt8_23_io_deq_valid : _T_3152 ? _Queue64_UInt8_22_io_deq_valid : _T_3151 ? _Queue64_UInt8_21_io_deq_valid : _T_3150 ? _Queue64_UInt8_20_io_deq_valid : _T_3149 ? _Queue64_UInt8_19_io_deq_valid : _T_3148 ? _Queue64_UInt8_18_io_deq_valid : _T_3147 ? _Queue64_UInt8_17_io_deq_valid : _T_3146 ? _Queue64_UInt8_16_io_deq_valid : _T_3145 ? _Queue64_UInt8_15_io_deq_valid : _T_3144 ? _Queue64_UInt8_14_io_deq_valid : _T_3143 ? _Queue64_UInt8_13_io_deq_valid : _T_3142 ? _Queue64_UInt8_12_io_deq_valid : _T_3141 ? _Queue64_UInt8_11_io_deq_valid : _T_3140 ? _Queue64_UInt8_10_io_deq_valid : _T_3139 ? _Queue64_UInt8_9_io_deq_valid : _T_3138 ? _Queue64_UInt8_8_io_deq_valid : _T_3137 ? _Queue64_UInt8_7_io_deq_valid : _T_3136 ? _Queue64_UInt8_6_io_deq_valid : _T_3135 ? _Queue64_UInt8_5_io_deq_valid : _T_3134 ? _Queue64_UInt8_4_io_deq_valid : _T_3133 ? _Queue64_UInt8_3_io_deq_valid : _T_3132 ? _Queue64_UInt8_2_io_deq_valid : _T_3131 ? _Queue64_UInt8_1_io_deq_valid : _T_3130 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_117 = _remapindex_T_26 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_26 = _GEN_117[5:0]; // @[MemLoader.scala:177:54]
wire _T_3162 = remapindex_26 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3163 = remapindex_26 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3164 = remapindex_26 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3165 = remapindex_26 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3166 = remapindex_26 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3167 = remapindex_26 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3168 = remapindex_26 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3169 = remapindex_26 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3170 = remapindex_26 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3171 = remapindex_26 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3172 = remapindex_26 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3173 = remapindex_26 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3174 = remapindex_26 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3175 = remapindex_26 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3176 = remapindex_26 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3177 = remapindex_26 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3178 = remapindex_26 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3179 = remapindex_26 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3180 = remapindex_26 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3181 = remapindex_26 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3182 = remapindex_26 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3183 = remapindex_26 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3184 = remapindex_26 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3185 = remapindex_26 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3186 = remapindex_26 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3187 = remapindex_26 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3188 = remapindex_26 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3189 = remapindex_26 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3190 = remapindex_26 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3191 = remapindex_26 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3192 = remapindex_26 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3193 = remapindex_26 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_bits : _T_3192 ? _Queue64_UInt8_30_io_deq_bits : _T_3191 ? _Queue64_UInt8_29_io_deq_bits : _T_3190 ? _Queue64_UInt8_28_io_deq_bits : _T_3189 ? _Queue64_UInt8_27_io_deq_bits : _T_3188 ? _Queue64_UInt8_26_io_deq_bits : _T_3187 ? _Queue64_UInt8_25_io_deq_bits : _T_3186 ? _Queue64_UInt8_24_io_deq_bits : _T_3185 ? _Queue64_UInt8_23_io_deq_bits : _T_3184 ? _Queue64_UInt8_22_io_deq_bits : _T_3183 ? _Queue64_UInt8_21_io_deq_bits : _T_3182 ? _Queue64_UInt8_20_io_deq_bits : _T_3181 ? _Queue64_UInt8_19_io_deq_bits : _T_3180 ? _Queue64_UInt8_18_io_deq_bits : _T_3179 ? _Queue64_UInt8_17_io_deq_bits : _T_3178 ? _Queue64_UInt8_16_io_deq_bits : _T_3177 ? _Queue64_UInt8_15_io_deq_bits : _T_3176 ? _Queue64_UInt8_14_io_deq_bits : _T_3175 ? _Queue64_UInt8_13_io_deq_bits : _T_3174 ? _Queue64_UInt8_12_io_deq_bits : _T_3173 ? _Queue64_UInt8_11_io_deq_bits : _T_3172 ? _Queue64_UInt8_10_io_deq_bits : _T_3171 ? _Queue64_UInt8_9_io_deq_bits : _T_3170 ? _Queue64_UInt8_8_io_deq_bits : _T_3169 ? _Queue64_UInt8_7_io_deq_bits : _T_3168 ? _Queue64_UInt8_6_io_deq_bits : _T_3167 ? _Queue64_UInt8_5_io_deq_bits : _T_3166 ? _Queue64_UInt8_4_io_deq_bits : _T_3165 ? _Queue64_UInt8_3_io_deq_bits : _T_3164 ? _Queue64_UInt8_2_io_deq_bits : _T_3163 ? _Queue64_UInt8_1_io_deq_bits : _T_3162 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_valid : _T_3192 ? _Queue64_UInt8_30_io_deq_valid : _T_3191 ? _Queue64_UInt8_29_io_deq_valid : _T_3190 ? _Queue64_UInt8_28_io_deq_valid : _T_3189 ? _Queue64_UInt8_27_io_deq_valid : _T_3188 ? _Queue64_UInt8_26_io_deq_valid : _T_3187 ? _Queue64_UInt8_25_io_deq_valid : _T_3186 ? _Queue64_UInt8_24_io_deq_valid : _T_3185 ? _Queue64_UInt8_23_io_deq_valid : _T_3184 ? _Queue64_UInt8_22_io_deq_valid : _T_3183 ? _Queue64_UInt8_21_io_deq_valid : _T_3182 ? _Queue64_UInt8_20_io_deq_valid : _T_3181 ? _Queue64_UInt8_19_io_deq_valid : _T_3180 ? _Queue64_UInt8_18_io_deq_valid : _T_3179 ? _Queue64_UInt8_17_io_deq_valid : _T_3178 ? _Queue64_UInt8_16_io_deq_valid : _T_3177 ? _Queue64_UInt8_15_io_deq_valid : _T_3176 ? _Queue64_UInt8_14_io_deq_valid : _T_3175 ? _Queue64_UInt8_13_io_deq_valid : _T_3174 ? _Queue64_UInt8_12_io_deq_valid : _T_3173 ? _Queue64_UInt8_11_io_deq_valid : _T_3172 ? _Queue64_UInt8_10_io_deq_valid : _T_3171 ? _Queue64_UInt8_9_io_deq_valid : _T_3170 ? _Queue64_UInt8_8_io_deq_valid : _T_3169 ? _Queue64_UInt8_7_io_deq_valid : _T_3168 ? _Queue64_UInt8_6_io_deq_valid : _T_3167 ? _Queue64_UInt8_5_io_deq_valid : _T_3166 ? _Queue64_UInt8_4_io_deq_valid : _T_3165 ? _Queue64_UInt8_3_io_deq_valid : _T_3164 ? _Queue64_UInt8_2_io_deq_valid : _T_3163 ? _Queue64_UInt8_1_io_deq_valid : _T_3162 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_118 = _remapindex_T_27 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_27 = _GEN_118[5:0]; // @[MemLoader.scala:177:54]
wire _T_3194 = remapindex_27 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3195 = remapindex_27 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3196 = remapindex_27 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3197 = remapindex_27 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3198 = remapindex_27 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3199 = remapindex_27 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3200 = remapindex_27 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3201 = remapindex_27 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3202 = remapindex_27 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3203 = remapindex_27 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3204 = remapindex_27 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3205 = remapindex_27 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3206 = remapindex_27 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3207 = remapindex_27 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3208 = remapindex_27 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3209 = remapindex_27 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3210 = remapindex_27 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3211 = remapindex_27 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3212 = remapindex_27 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3213 = remapindex_27 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3214 = remapindex_27 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3215 = remapindex_27 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3216 = remapindex_27 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3217 = remapindex_27 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3218 = remapindex_27 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3219 = remapindex_27 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3220 = remapindex_27 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3221 = remapindex_27 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3222 = remapindex_27 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3223 = remapindex_27 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3224 = remapindex_27 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3225 = remapindex_27 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_bits : _T_3224 ? _Queue64_UInt8_30_io_deq_bits : _T_3223 ? _Queue64_UInt8_29_io_deq_bits : _T_3222 ? _Queue64_UInt8_28_io_deq_bits : _T_3221 ? _Queue64_UInt8_27_io_deq_bits : _T_3220 ? _Queue64_UInt8_26_io_deq_bits : _T_3219 ? _Queue64_UInt8_25_io_deq_bits : _T_3218 ? _Queue64_UInt8_24_io_deq_bits : _T_3217 ? _Queue64_UInt8_23_io_deq_bits : _T_3216 ? _Queue64_UInt8_22_io_deq_bits : _T_3215 ? _Queue64_UInt8_21_io_deq_bits : _T_3214 ? _Queue64_UInt8_20_io_deq_bits : _T_3213 ? _Queue64_UInt8_19_io_deq_bits : _T_3212 ? _Queue64_UInt8_18_io_deq_bits : _T_3211 ? _Queue64_UInt8_17_io_deq_bits : _T_3210 ? _Queue64_UInt8_16_io_deq_bits : _T_3209 ? _Queue64_UInt8_15_io_deq_bits : _T_3208 ? _Queue64_UInt8_14_io_deq_bits : _T_3207 ? _Queue64_UInt8_13_io_deq_bits : _T_3206 ? _Queue64_UInt8_12_io_deq_bits : _T_3205 ? _Queue64_UInt8_11_io_deq_bits : _T_3204 ? _Queue64_UInt8_10_io_deq_bits : _T_3203 ? _Queue64_UInt8_9_io_deq_bits : _T_3202 ? _Queue64_UInt8_8_io_deq_bits : _T_3201 ? _Queue64_UInt8_7_io_deq_bits : _T_3200 ? _Queue64_UInt8_6_io_deq_bits : _T_3199 ? _Queue64_UInt8_5_io_deq_bits : _T_3198 ? _Queue64_UInt8_4_io_deq_bits : _T_3197 ? _Queue64_UInt8_3_io_deq_bits : _T_3196 ? _Queue64_UInt8_2_io_deq_bits : _T_3195 ? _Queue64_UInt8_1_io_deq_bits : _T_3194 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_valid : _T_3224 ? _Queue64_UInt8_30_io_deq_valid : _T_3223 ? _Queue64_UInt8_29_io_deq_valid : _T_3222 ? _Queue64_UInt8_28_io_deq_valid : _T_3221 ? _Queue64_UInt8_27_io_deq_valid : _T_3220 ? _Queue64_UInt8_26_io_deq_valid : _T_3219 ? _Queue64_UInt8_25_io_deq_valid : _T_3218 ? _Queue64_UInt8_24_io_deq_valid : _T_3217 ? _Queue64_UInt8_23_io_deq_valid : _T_3216 ? _Queue64_UInt8_22_io_deq_valid : _T_3215 ? _Queue64_UInt8_21_io_deq_valid : _T_3214 ? _Queue64_UInt8_20_io_deq_valid : _T_3213 ? _Queue64_UInt8_19_io_deq_valid : _T_3212 ? _Queue64_UInt8_18_io_deq_valid : _T_3211 ? _Queue64_UInt8_17_io_deq_valid : _T_3210 ? _Queue64_UInt8_16_io_deq_valid : _T_3209 ? _Queue64_UInt8_15_io_deq_valid : _T_3208 ? _Queue64_UInt8_14_io_deq_valid : _T_3207 ? _Queue64_UInt8_13_io_deq_valid : _T_3206 ? _Queue64_UInt8_12_io_deq_valid : _T_3205 ? _Queue64_UInt8_11_io_deq_valid : _T_3204 ? _Queue64_UInt8_10_io_deq_valid : _T_3203 ? _Queue64_UInt8_9_io_deq_valid : _T_3202 ? _Queue64_UInt8_8_io_deq_valid : _T_3201 ? _Queue64_UInt8_7_io_deq_valid : _T_3200 ? _Queue64_UInt8_6_io_deq_valid : _T_3199 ? _Queue64_UInt8_5_io_deq_valid : _T_3198 ? _Queue64_UInt8_4_io_deq_valid : _T_3197 ? _Queue64_UInt8_3_io_deq_valid : _T_3196 ? _Queue64_UInt8_2_io_deq_valid : _T_3195 ? _Queue64_UInt8_1_io_deq_valid : _T_3194 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_119 = _remapindex_T_28 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_28 = _GEN_119[5:0]; // @[MemLoader.scala:177:54]
wire _T_3226 = remapindex_28 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3227 = remapindex_28 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3228 = remapindex_28 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3229 = remapindex_28 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3230 = remapindex_28 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3231 = remapindex_28 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3232 = remapindex_28 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3233 = remapindex_28 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3234 = remapindex_28 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3235 = remapindex_28 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3236 = remapindex_28 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3237 = remapindex_28 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3238 = remapindex_28 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3239 = remapindex_28 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3240 = remapindex_28 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3241 = remapindex_28 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3242 = remapindex_28 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3243 = remapindex_28 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3244 = remapindex_28 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3245 = remapindex_28 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3246 = remapindex_28 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3247 = remapindex_28 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3248 = remapindex_28 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3249 = remapindex_28 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3250 = remapindex_28 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3251 = remapindex_28 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3252 = remapindex_28 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3253 = remapindex_28 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3254 = remapindex_28 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3255 = remapindex_28 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3256 = remapindex_28 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3257 = remapindex_28 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_bits : _T_3256 ? _Queue64_UInt8_30_io_deq_bits : _T_3255 ? _Queue64_UInt8_29_io_deq_bits : _T_3254 ? _Queue64_UInt8_28_io_deq_bits : _T_3253 ? _Queue64_UInt8_27_io_deq_bits : _T_3252 ? _Queue64_UInt8_26_io_deq_bits : _T_3251 ? _Queue64_UInt8_25_io_deq_bits : _T_3250 ? _Queue64_UInt8_24_io_deq_bits : _T_3249 ? _Queue64_UInt8_23_io_deq_bits : _T_3248 ? _Queue64_UInt8_22_io_deq_bits : _T_3247 ? _Queue64_UInt8_21_io_deq_bits : _T_3246 ? _Queue64_UInt8_20_io_deq_bits : _T_3245 ? _Queue64_UInt8_19_io_deq_bits : _T_3244 ? _Queue64_UInt8_18_io_deq_bits : _T_3243 ? _Queue64_UInt8_17_io_deq_bits : _T_3242 ? _Queue64_UInt8_16_io_deq_bits : _T_3241 ? _Queue64_UInt8_15_io_deq_bits : _T_3240 ? _Queue64_UInt8_14_io_deq_bits : _T_3239 ? _Queue64_UInt8_13_io_deq_bits : _T_3238 ? _Queue64_UInt8_12_io_deq_bits : _T_3237 ? _Queue64_UInt8_11_io_deq_bits : _T_3236 ? _Queue64_UInt8_10_io_deq_bits : _T_3235 ? _Queue64_UInt8_9_io_deq_bits : _T_3234 ? _Queue64_UInt8_8_io_deq_bits : _T_3233 ? _Queue64_UInt8_7_io_deq_bits : _T_3232 ? _Queue64_UInt8_6_io_deq_bits : _T_3231 ? _Queue64_UInt8_5_io_deq_bits : _T_3230 ? _Queue64_UInt8_4_io_deq_bits : _T_3229 ? _Queue64_UInt8_3_io_deq_bits : _T_3228 ? _Queue64_UInt8_2_io_deq_bits : _T_3227 ? _Queue64_UInt8_1_io_deq_bits : _T_3226 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_valid : _T_3256 ? _Queue64_UInt8_30_io_deq_valid : _T_3255 ? _Queue64_UInt8_29_io_deq_valid : _T_3254 ? _Queue64_UInt8_28_io_deq_valid : _T_3253 ? _Queue64_UInt8_27_io_deq_valid : _T_3252 ? _Queue64_UInt8_26_io_deq_valid : _T_3251 ? _Queue64_UInt8_25_io_deq_valid : _T_3250 ? _Queue64_UInt8_24_io_deq_valid : _T_3249 ? _Queue64_UInt8_23_io_deq_valid : _T_3248 ? _Queue64_UInt8_22_io_deq_valid : _T_3247 ? _Queue64_UInt8_21_io_deq_valid : _T_3246 ? _Queue64_UInt8_20_io_deq_valid : _T_3245 ? _Queue64_UInt8_19_io_deq_valid : _T_3244 ? _Queue64_UInt8_18_io_deq_valid : _T_3243 ? _Queue64_UInt8_17_io_deq_valid : _T_3242 ? _Queue64_UInt8_16_io_deq_valid : _T_3241 ? _Queue64_UInt8_15_io_deq_valid : _T_3240 ? _Queue64_UInt8_14_io_deq_valid : _T_3239 ? _Queue64_UInt8_13_io_deq_valid : _T_3238 ? _Queue64_UInt8_12_io_deq_valid : _T_3237 ? _Queue64_UInt8_11_io_deq_valid : _T_3236 ? _Queue64_UInt8_10_io_deq_valid : _T_3235 ? _Queue64_UInt8_9_io_deq_valid : _T_3234 ? _Queue64_UInt8_8_io_deq_valid : _T_3233 ? _Queue64_UInt8_7_io_deq_valid : _T_3232 ? _Queue64_UInt8_6_io_deq_valid : _T_3231 ? _Queue64_UInt8_5_io_deq_valid : _T_3230 ? _Queue64_UInt8_4_io_deq_valid : _T_3229 ? _Queue64_UInt8_3_io_deq_valid : _T_3228 ? _Queue64_UInt8_2_io_deq_valid : _T_3227 ? _Queue64_UInt8_1_io_deq_valid : _T_3226 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_120 = _remapindex_T_29 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_29 = _GEN_120[5:0]; // @[MemLoader.scala:177:54]
wire _T_3258 = remapindex_29 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3259 = remapindex_29 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3260 = remapindex_29 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3261 = remapindex_29 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3262 = remapindex_29 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3263 = remapindex_29 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3264 = remapindex_29 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3265 = remapindex_29 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3266 = remapindex_29 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3267 = remapindex_29 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3268 = remapindex_29 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3269 = remapindex_29 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3270 = remapindex_29 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3271 = remapindex_29 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3272 = remapindex_29 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3273 = remapindex_29 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3274 = remapindex_29 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3275 = remapindex_29 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3276 = remapindex_29 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3277 = remapindex_29 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3278 = remapindex_29 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3279 = remapindex_29 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3280 = remapindex_29 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3281 = remapindex_29 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3282 = remapindex_29 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3283 = remapindex_29 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3284 = remapindex_29 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3285 = remapindex_29 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3286 = remapindex_29 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3287 = remapindex_29 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3288 = remapindex_29 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3289 = remapindex_29 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_bits : _T_3288 ? _Queue64_UInt8_30_io_deq_bits : _T_3287 ? _Queue64_UInt8_29_io_deq_bits : _T_3286 ? _Queue64_UInt8_28_io_deq_bits : _T_3285 ? _Queue64_UInt8_27_io_deq_bits : _T_3284 ? _Queue64_UInt8_26_io_deq_bits : _T_3283 ? _Queue64_UInt8_25_io_deq_bits : _T_3282 ? _Queue64_UInt8_24_io_deq_bits : _T_3281 ? _Queue64_UInt8_23_io_deq_bits : _T_3280 ? _Queue64_UInt8_22_io_deq_bits : _T_3279 ? _Queue64_UInt8_21_io_deq_bits : _T_3278 ? _Queue64_UInt8_20_io_deq_bits : _T_3277 ? _Queue64_UInt8_19_io_deq_bits : _T_3276 ? _Queue64_UInt8_18_io_deq_bits : _T_3275 ? _Queue64_UInt8_17_io_deq_bits : _T_3274 ? _Queue64_UInt8_16_io_deq_bits : _T_3273 ? _Queue64_UInt8_15_io_deq_bits : _T_3272 ? _Queue64_UInt8_14_io_deq_bits : _T_3271 ? _Queue64_UInt8_13_io_deq_bits : _T_3270 ? _Queue64_UInt8_12_io_deq_bits : _T_3269 ? _Queue64_UInt8_11_io_deq_bits : _T_3268 ? _Queue64_UInt8_10_io_deq_bits : _T_3267 ? _Queue64_UInt8_9_io_deq_bits : _T_3266 ? _Queue64_UInt8_8_io_deq_bits : _T_3265 ? _Queue64_UInt8_7_io_deq_bits : _T_3264 ? _Queue64_UInt8_6_io_deq_bits : _T_3263 ? _Queue64_UInt8_5_io_deq_bits : _T_3262 ? _Queue64_UInt8_4_io_deq_bits : _T_3261 ? _Queue64_UInt8_3_io_deq_bits : _T_3260 ? _Queue64_UInt8_2_io_deq_bits : _T_3259 ? _Queue64_UInt8_1_io_deq_bits : _T_3258 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_valid : _T_3288 ? _Queue64_UInt8_30_io_deq_valid : _T_3287 ? _Queue64_UInt8_29_io_deq_valid : _T_3286 ? _Queue64_UInt8_28_io_deq_valid : _T_3285 ? _Queue64_UInt8_27_io_deq_valid : _T_3284 ? _Queue64_UInt8_26_io_deq_valid : _T_3283 ? _Queue64_UInt8_25_io_deq_valid : _T_3282 ? _Queue64_UInt8_24_io_deq_valid : _T_3281 ? _Queue64_UInt8_23_io_deq_valid : _T_3280 ? _Queue64_UInt8_22_io_deq_valid : _T_3279 ? _Queue64_UInt8_21_io_deq_valid : _T_3278 ? _Queue64_UInt8_20_io_deq_valid : _T_3277 ? _Queue64_UInt8_19_io_deq_valid : _T_3276 ? _Queue64_UInt8_18_io_deq_valid : _T_3275 ? _Queue64_UInt8_17_io_deq_valid : _T_3274 ? _Queue64_UInt8_16_io_deq_valid : _T_3273 ? _Queue64_UInt8_15_io_deq_valid : _T_3272 ? _Queue64_UInt8_14_io_deq_valid : _T_3271 ? _Queue64_UInt8_13_io_deq_valid : _T_3270 ? _Queue64_UInt8_12_io_deq_valid : _T_3269 ? _Queue64_UInt8_11_io_deq_valid : _T_3268 ? _Queue64_UInt8_10_io_deq_valid : _T_3267 ? _Queue64_UInt8_9_io_deq_valid : _T_3266 ? _Queue64_UInt8_8_io_deq_valid : _T_3265 ? _Queue64_UInt8_7_io_deq_valid : _T_3264 ? _Queue64_UInt8_6_io_deq_valid : _T_3263 ? _Queue64_UInt8_5_io_deq_valid : _T_3262 ? _Queue64_UInt8_4_io_deq_valid : _T_3261 ? _Queue64_UInt8_3_io_deq_valid : _T_3260 ? _Queue64_UInt8_2_io_deq_valid : _T_3259 ? _Queue64_UInt8_1_io_deq_valid : _T_3258 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_121 = _remapindex_T_30 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_30 = _GEN_121[5:0]; // @[MemLoader.scala:177:54]
wire _T_3290 = remapindex_30 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3291 = remapindex_30 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3292 = remapindex_30 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3293 = remapindex_30 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3294 = remapindex_30 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3295 = remapindex_30 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3296 = remapindex_30 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3297 = remapindex_30 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3298 = remapindex_30 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3299 = remapindex_30 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3300 = remapindex_30 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3301 = remapindex_30 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3302 = remapindex_30 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3303 = remapindex_30 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3304 = remapindex_30 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3305 = remapindex_30 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3306 = remapindex_30 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3307 = remapindex_30 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3308 = remapindex_30 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3309 = remapindex_30 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3310 = remapindex_30 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3311 = remapindex_30 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3312 = remapindex_30 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3313 = remapindex_30 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3314 = remapindex_30 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3315 = remapindex_30 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3316 = remapindex_30 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3317 = remapindex_30 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3318 = remapindex_30 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3319 = remapindex_30 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3320 = remapindex_30 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3321 = remapindex_30 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_bits : _T_3320 ? _Queue64_UInt8_30_io_deq_bits : _T_3319 ? _Queue64_UInt8_29_io_deq_bits : _T_3318 ? _Queue64_UInt8_28_io_deq_bits : _T_3317 ? _Queue64_UInt8_27_io_deq_bits : _T_3316 ? _Queue64_UInt8_26_io_deq_bits : _T_3315 ? _Queue64_UInt8_25_io_deq_bits : _T_3314 ? _Queue64_UInt8_24_io_deq_bits : _T_3313 ? _Queue64_UInt8_23_io_deq_bits : _T_3312 ? _Queue64_UInt8_22_io_deq_bits : _T_3311 ? _Queue64_UInt8_21_io_deq_bits : _T_3310 ? _Queue64_UInt8_20_io_deq_bits : _T_3309 ? _Queue64_UInt8_19_io_deq_bits : _T_3308 ? _Queue64_UInt8_18_io_deq_bits : _T_3307 ? _Queue64_UInt8_17_io_deq_bits : _T_3306 ? _Queue64_UInt8_16_io_deq_bits : _T_3305 ? _Queue64_UInt8_15_io_deq_bits : _T_3304 ? _Queue64_UInt8_14_io_deq_bits : _T_3303 ? _Queue64_UInt8_13_io_deq_bits : _T_3302 ? _Queue64_UInt8_12_io_deq_bits : _T_3301 ? _Queue64_UInt8_11_io_deq_bits : _T_3300 ? _Queue64_UInt8_10_io_deq_bits : _T_3299 ? _Queue64_UInt8_9_io_deq_bits : _T_3298 ? _Queue64_UInt8_8_io_deq_bits : _T_3297 ? _Queue64_UInt8_7_io_deq_bits : _T_3296 ? _Queue64_UInt8_6_io_deq_bits : _T_3295 ? _Queue64_UInt8_5_io_deq_bits : _T_3294 ? _Queue64_UInt8_4_io_deq_bits : _T_3293 ? _Queue64_UInt8_3_io_deq_bits : _T_3292 ? _Queue64_UInt8_2_io_deq_bits : _T_3291 ? _Queue64_UInt8_1_io_deq_bits : _T_3290 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_valid : _T_3320 ? _Queue64_UInt8_30_io_deq_valid : _T_3319 ? _Queue64_UInt8_29_io_deq_valid : _T_3318 ? _Queue64_UInt8_28_io_deq_valid : _T_3317 ? _Queue64_UInt8_27_io_deq_valid : _T_3316 ? _Queue64_UInt8_26_io_deq_valid : _T_3315 ? _Queue64_UInt8_25_io_deq_valid : _T_3314 ? _Queue64_UInt8_24_io_deq_valid : _T_3313 ? _Queue64_UInt8_23_io_deq_valid : _T_3312 ? _Queue64_UInt8_22_io_deq_valid : _T_3311 ? _Queue64_UInt8_21_io_deq_valid : _T_3310 ? _Queue64_UInt8_20_io_deq_valid : _T_3309 ? _Queue64_UInt8_19_io_deq_valid : _T_3308 ? _Queue64_UInt8_18_io_deq_valid : _T_3307 ? _Queue64_UInt8_17_io_deq_valid : _T_3306 ? _Queue64_UInt8_16_io_deq_valid : _T_3305 ? _Queue64_UInt8_15_io_deq_valid : _T_3304 ? _Queue64_UInt8_14_io_deq_valid : _T_3303 ? _Queue64_UInt8_13_io_deq_valid : _T_3302 ? _Queue64_UInt8_12_io_deq_valid : _T_3301 ? _Queue64_UInt8_11_io_deq_valid : _T_3300 ? _Queue64_UInt8_10_io_deq_valid : _T_3299 ? _Queue64_UInt8_9_io_deq_valid : _T_3298 ? _Queue64_UInt8_8_io_deq_valid : _T_3297 ? _Queue64_UInt8_7_io_deq_valid : _T_3296 ? _Queue64_UInt8_6_io_deq_valid : _T_3295 ? _Queue64_UInt8_5_io_deq_valid : _T_3294 ? _Queue64_UInt8_4_io_deq_valid : _T_3293 ? _Queue64_UInt8_3_io_deq_valid : _T_3292 ? _Queue64_UInt8_2_io_deq_valid : _T_3291 ? _Queue64_UInt8_1_io_deq_valid : _T_3290 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_122 = _remapindex_T_31 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_31 = _GEN_122[5:0]; // @[MemLoader.scala:177:54]
wire _T_3322 = remapindex_31 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3323 = remapindex_31 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3324 = remapindex_31 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3325 = remapindex_31 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3326 = remapindex_31 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3327 = remapindex_31 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3328 = remapindex_31 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3329 = remapindex_31 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3330 = remapindex_31 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3331 = remapindex_31 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3332 = remapindex_31 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3333 = remapindex_31 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3334 = remapindex_31 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3335 = remapindex_31 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3336 = remapindex_31 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3337 = remapindex_31 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3338 = remapindex_31 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3339 = remapindex_31 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3340 = remapindex_31 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3341 = remapindex_31 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3342 = remapindex_31 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3343 = remapindex_31 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3344 = remapindex_31 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3345 = remapindex_31 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3346 = remapindex_31 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3347 = remapindex_31 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3348 = remapindex_31 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3349 = remapindex_31 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3350 = remapindex_31 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3351 = remapindex_31 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3352 = remapindex_31 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3353 = remapindex_31 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_bits : _T_3352 ? _Queue64_UInt8_30_io_deq_bits : _T_3351 ? _Queue64_UInt8_29_io_deq_bits : _T_3350 ? _Queue64_UInt8_28_io_deq_bits : _T_3349 ? _Queue64_UInt8_27_io_deq_bits : _T_3348 ? _Queue64_UInt8_26_io_deq_bits : _T_3347 ? _Queue64_UInt8_25_io_deq_bits : _T_3346 ? _Queue64_UInt8_24_io_deq_bits : _T_3345 ? _Queue64_UInt8_23_io_deq_bits : _T_3344 ? _Queue64_UInt8_22_io_deq_bits : _T_3343 ? _Queue64_UInt8_21_io_deq_bits : _T_3342 ? _Queue64_UInt8_20_io_deq_bits : _T_3341 ? _Queue64_UInt8_19_io_deq_bits : _T_3340 ? _Queue64_UInt8_18_io_deq_bits : _T_3339 ? _Queue64_UInt8_17_io_deq_bits : _T_3338 ? _Queue64_UInt8_16_io_deq_bits : _T_3337 ? _Queue64_UInt8_15_io_deq_bits : _T_3336 ? _Queue64_UInt8_14_io_deq_bits : _T_3335 ? _Queue64_UInt8_13_io_deq_bits : _T_3334 ? _Queue64_UInt8_12_io_deq_bits : _T_3333 ? _Queue64_UInt8_11_io_deq_bits : _T_3332 ? _Queue64_UInt8_10_io_deq_bits : _T_3331 ? _Queue64_UInt8_9_io_deq_bits : _T_3330 ? _Queue64_UInt8_8_io_deq_bits : _T_3329 ? _Queue64_UInt8_7_io_deq_bits : _T_3328 ? _Queue64_UInt8_6_io_deq_bits : _T_3327 ? _Queue64_UInt8_5_io_deq_bits : _T_3326 ? _Queue64_UInt8_4_io_deq_bits : _T_3325 ? _Queue64_UInt8_3_io_deq_bits : _T_3324 ? _Queue64_UInt8_2_io_deq_bits : _T_3323 ? _Queue64_UInt8_1_io_deq_bits : _T_3322 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_valid : _T_3352 ? _Queue64_UInt8_30_io_deq_valid : _T_3351 ? _Queue64_UInt8_29_io_deq_valid : _T_3350 ? _Queue64_UInt8_28_io_deq_valid : _T_3349 ? _Queue64_UInt8_27_io_deq_valid : _T_3348 ? _Queue64_UInt8_26_io_deq_valid : _T_3347 ? _Queue64_UInt8_25_io_deq_valid : _T_3346 ? _Queue64_UInt8_24_io_deq_valid : _T_3345 ? _Queue64_UInt8_23_io_deq_valid : _T_3344 ? _Queue64_UInt8_22_io_deq_valid : _T_3343 ? _Queue64_UInt8_21_io_deq_valid : _T_3342 ? _Queue64_UInt8_20_io_deq_valid : _T_3341 ? _Queue64_UInt8_19_io_deq_valid : _T_3340 ? _Queue64_UInt8_18_io_deq_valid : _T_3339 ? _Queue64_UInt8_17_io_deq_valid : _T_3338 ? _Queue64_UInt8_16_io_deq_valid : _T_3337 ? _Queue64_UInt8_15_io_deq_valid : _T_3336 ? _Queue64_UInt8_14_io_deq_valid : _T_3335 ? _Queue64_UInt8_13_io_deq_valid : _T_3334 ? _Queue64_UInt8_12_io_deq_valid : _T_3333 ? _Queue64_UInt8_11_io_deq_valid : _T_3332 ? _Queue64_UInt8_10_io_deq_valid : _T_3331 ? _Queue64_UInt8_9_io_deq_valid : _T_3330 ? _Queue64_UInt8_8_io_deq_valid : _T_3329 ? _Queue64_UInt8_7_io_deq_valid : _T_3328 ? _Queue64_UInt8_6_io_deq_valid : _T_3327 ? _Queue64_UInt8_5_io_deq_valid : _T_3326 ? _Queue64_UInt8_4_io_deq_valid : _T_3325 ? _Queue64_UInt8_3_io_deq_valid : _T_3324 ? _Queue64_UInt8_2_io_deq_valid : _T_3323 ? _Queue64_UInt8_1_io_deq_valid : _T_3322 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[MemLoader.scala:186:33]
assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[MemLoader.scala:186:33]
assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[MemLoader.scala:15:7, :186:33]
wire [64:0] _GEN_123 = {1'h0, len_already_consumed}; // @[MemLoader.scala:164:37, :189:40]
wire [64:0] _GEN_124 = _GEN_123 + {59'h0, io_consumer_user_consumed_bytes_0}; // @[MemLoader.scala:15:7, :189:40]
wire [64:0] _buf_last_T; // @[MemLoader.scala:189:40]
assign _buf_last_T = _GEN_124; // @[MemLoader.scala:189:40]
wire [64:0] _len_already_consumed_T; // @[MemLoader.scala:230:52]
assign _len_already_consumed_T = _GEN_124; // @[MemLoader.scala:189:40, :230:52]
wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[MemLoader.scala:189:40]
wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30, :189:{40,75}]
wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[MemLoader.scala:167:28, :190:60]
wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[MemLoader.scala:167:28, :190:60]
wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[MemLoader.scala:167:28, :190:60]
wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[MemLoader.scala:167:28, :190:60]
wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[MemLoader.scala:167:28, :190:60]
wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[MemLoader.scala:167:28, :190:60]
wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[MemLoader.scala:167:28, :190:60]
wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[MemLoader.scala:167:28, :190:60]
wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[MemLoader.scala:167:28, :190:60]
wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[MemLoader.scala:167:28, :190:60]
wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[MemLoader.scala:167:28, :190:60]
wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[MemLoader.scala:167:28, :190:60]
wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[MemLoader.scala:167:28, :190:60]
wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[MemLoader.scala:167:28, :190:60]
wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[MemLoader.scala:167:28, :190:60]
wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[MemLoader.scala:167:28, :190:60]
wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[MemLoader.scala:167:28, :190:60]
wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[MemLoader.scala:167:28, :190:60]
wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[MemLoader.scala:167:28, :190:60]
wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[MemLoader.scala:167:28, :190:60]
wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[MemLoader.scala:167:28, :190:60]
wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[MemLoader.scala:167:28, :190:60]
wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[MemLoader.scala:167:28, :190:60]
wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[MemLoader.scala:167:28, :190:60]
wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[MemLoader.scala:167:28, :190:60]
wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[MemLoader.scala:167:28, :190:60]
wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[MemLoader.scala:167:28, :190:60]
wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[MemLoader.scala:167:28, :190:60]
wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[MemLoader.scala:167:28, :190:60]
wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[MemLoader.scala:167:28, :190:60]
wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[MemLoader.scala:167:28, :190:60]
wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_123; // @[MemLoader.scala:26:30, :189:40, :191:70]
wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[MemLoader.scala:191:70]
wire _enough_data_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49]
wire _enough_data_T_1 = count_valids == 32'h20; // @[MemLoader.scala:190:60, :194:38]
wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[MemLoader.scala:190:60, :191:70, :195:38]
wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[MemLoader.scala:193:{24,49}, :194:38, :195:38]
wire _io_consumer_available_output_bytes_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49, :197:69]
wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[MemLoader.scala:191:70, :197:{44,69}]
assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[MemLoader.scala:15:7, :197:{38,44}]
assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[MemLoader.scala:191:70, :201:61]
assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[MemLoader.scala:15:7, :201:61]
wire _T_3362 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_1 = _T_3362; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module PE_315 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_59
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_315( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_59 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_31 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<10>(0h1c0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_98 = shr(io.in.a.bits.source, 5)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_176 = shr(io.in.a.bits.source, 5)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_229 = shr(io.in.a.bits.source, 5)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_276 = shr(io.in.a.bits.source, 5)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_325 = shr(io.in.a.bits.source, 5)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_369 = shr(io.in.a.bits.source, 5)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_413 = shr(io.in.a.bits.source, 5)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_62
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_63
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_64 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_65 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_31( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AXI4ToTL :
input clock : Clock
input reset : Reset
output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate nodeIn.r.bits.last
invalidate nodeIn.r.bits.resp
invalidate nodeIn.r.bits.data
invalidate nodeIn.r.bits.id
invalidate nodeIn.r.valid
invalidate nodeIn.r.ready
invalidate nodeIn.ar.bits.qos
invalidate nodeIn.ar.bits.prot
invalidate nodeIn.ar.bits.cache
invalidate nodeIn.ar.bits.lock
invalidate nodeIn.ar.bits.burst
invalidate nodeIn.ar.bits.size
invalidate nodeIn.ar.bits.len
invalidate nodeIn.ar.bits.addr
invalidate nodeIn.ar.bits.id
invalidate nodeIn.ar.valid
invalidate nodeIn.ar.ready
invalidate nodeIn.b.bits.resp
invalidate nodeIn.b.bits.id
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.w.bits.last
invalidate nodeIn.w.bits.strb
invalidate nodeIn.w.bits.data
invalidate nodeIn.w.valid
invalidate nodeIn.w.ready
invalidate nodeIn.aw.bits.qos
invalidate nodeIn.aw.bits.prot
invalidate nodeIn.aw.bits.cache
invalidate nodeIn.aw.bits.lock
invalidate nodeIn.aw.bits.burst
invalidate nodeIn.aw.bits.size
invalidate nodeIn.aw.bits.len
invalidate nodeIn.aw.bits.addr
invalidate nodeIn.aw.bits.id
invalidate nodeIn.aw.valid
invalidate nodeIn.aw.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.user.amba_prot.fetch
invalidate nodeOut.a.bits.user.amba_prot.secure
invalidate nodeOut.a.bits.user.amba_prot.privileged
invalidate nodeOut.a.bits.user.amba_prot.writealloc
invalidate nodeOut.a.bits.user.amba_prot.readalloc
invalidate nodeOut.a.bits.user.amba_prot.modifiable
invalidate nodeOut.a.bits.user.amba_prot.bufferable
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
wire r_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect r_out.bits, nodeOut.a.bits
connect r_out.valid, nodeOut.a.valid
connect r_out.ready, nodeOut.a.ready
node _r_size1_T = cat(nodeIn.ar.bits.len, UInt<8>(0hff))
node _r_size1_T_1 = dshl(_r_size1_T, nodeIn.ar.bits.size)
node r_size1 = shr(_r_size1_T_1, 8)
node _r_size_T = shl(r_size1, 1)
node _r_size_T_1 = or(_r_size_T, UInt<1>(0h1))
node _r_size_T_2 = cat(UInt<1>(0h0), r_size1)
node _r_size_T_3 = not(_r_size_T_2)
node _r_size_T_4 = and(_r_size_T_1, _r_size_T_3)
node r_size_hi = bits(_r_size_T_4, 15, 8)
node r_size_lo = bits(_r_size_T_4, 7, 0)
node _r_size_T_5 = orr(r_size_hi)
node _r_size_T_6 = or(r_size_hi, r_size_lo)
node r_size_hi_1 = bits(_r_size_T_6, 7, 4)
node r_size_lo_1 = bits(_r_size_T_6, 3, 0)
node _r_size_T_7 = orr(r_size_hi_1)
node _r_size_T_8 = or(r_size_hi_1, r_size_lo_1)
node r_size_hi_2 = bits(_r_size_T_8, 3, 2)
node r_size_lo_2 = bits(_r_size_T_8, 1, 0)
node _r_size_T_9 = orr(r_size_hi_2)
node _r_size_T_10 = or(r_size_hi_2, r_size_lo_2)
node _r_size_T_11 = bits(_r_size_T_10, 1, 1)
node _r_size_T_12 = cat(_r_size_T_9, _r_size_T_11)
node _r_size_T_13 = cat(_r_size_T_7, _r_size_T_12)
node r_size = cat(_r_size_T_5, _r_size_T_13)
node _r_ok_T = leq(UInt<1>(0h0), r_size)
node _r_ok_T_1 = leq(r_size, UInt<4>(0hc))
node _r_ok_T_2 = and(_r_ok_T, _r_ok_T_1)
node _r_ok_T_3 = or(UInt<1>(0h0), _r_ok_T_2)
node _r_ok_T_4 = xor(nodeIn.ar.bits.addr, UInt<14>(0h3000))
node _r_ok_T_5 = cvt(_r_ok_T_4)
node _r_ok_T_6 = and(_r_ok_T_5, asSInt(UInt<13>(0h1000)))
node _r_ok_T_7 = asSInt(_r_ok_T_6)
node _r_ok_T_8 = eq(_r_ok_T_7, asSInt(UInt<1>(0h0)))
node _r_ok_T_9 = and(_r_ok_T_3, _r_ok_T_8)
node _r_ok_T_10 = leq(UInt<1>(0h0), r_size)
node _r_ok_T_11 = leq(r_size, UInt<3>(0h6))
node _r_ok_T_12 = and(_r_ok_T_10, _r_ok_T_11)
node _r_ok_T_13 = or(UInt<1>(0h0), _r_ok_T_12)
node _r_ok_T_14 = xor(nodeIn.ar.bits.addr, UInt<1>(0h0))
node _r_ok_T_15 = cvt(_r_ok_T_14)
node _r_ok_T_16 = and(_r_ok_T_15, asSInt(UInt<14>(0h2000)))
node _r_ok_T_17 = asSInt(_r_ok_T_16)
node _r_ok_T_18 = eq(_r_ok_T_17, asSInt(UInt<1>(0h0)))
node _r_ok_T_19 = xor(nodeIn.ar.bits.addr, UInt<17>(0h10000))
node _r_ok_T_20 = cvt(_r_ok_T_19)
node _r_ok_T_21 = and(_r_ok_T_20, asSInt(UInt<17>(0h10000)))
node _r_ok_T_22 = asSInt(_r_ok_T_21)
node _r_ok_T_23 = eq(_r_ok_T_22, asSInt(UInt<1>(0h0)))
node _r_ok_T_24 = xor(nodeIn.ar.bits.addr, UInt<21>(0h100000))
node _r_ok_T_25 = cvt(_r_ok_T_24)
node _r_ok_T_26 = and(_r_ok_T_25, asSInt(UInt<18>(0h2f000)))
node _r_ok_T_27 = asSInt(_r_ok_T_26)
node _r_ok_T_28 = eq(_r_ok_T_27, asSInt(UInt<1>(0h0)))
node _r_ok_T_29 = xor(nodeIn.ar.bits.addr, UInt<26>(0h2000000))
node _r_ok_T_30 = cvt(_r_ok_T_29)
node _r_ok_T_31 = and(_r_ok_T_30, asSInt(UInt<17>(0h10000)))
node _r_ok_T_32 = asSInt(_r_ok_T_31)
node _r_ok_T_33 = eq(_r_ok_T_32, asSInt(UInt<1>(0h0)))
node _r_ok_T_34 = xor(nodeIn.ar.bits.addr, UInt<28>(0hc000000))
node _r_ok_T_35 = cvt(_r_ok_T_34)
node _r_ok_T_36 = and(_r_ok_T_35, asSInt(UInt<27>(0h4000000)))
node _r_ok_T_37 = asSInt(_r_ok_T_36)
node _r_ok_T_38 = eq(_r_ok_T_37, asSInt(UInt<1>(0h0)))
node _r_ok_T_39 = xor(nodeIn.ar.bits.addr, UInt<29>(0h10020000))
node _r_ok_T_40 = cvt(_r_ok_T_39)
node _r_ok_T_41 = and(_r_ok_T_40, asSInt(UInt<13>(0h1000)))
node _r_ok_T_42 = asSInt(_r_ok_T_41)
node _r_ok_T_43 = eq(_r_ok_T_42, asSInt(UInt<1>(0h0)))
node _r_ok_T_44 = xor(nodeIn.ar.bits.addr, UInt<31>(0h60000000))
node _r_ok_T_45 = cvt(_r_ok_T_44)
node _r_ok_T_46 = and(_r_ok_T_45, asSInt(UInt<30>(0h20000000)))
node _r_ok_T_47 = asSInt(_r_ok_T_46)
node _r_ok_T_48 = eq(_r_ok_T_47, asSInt(UInt<1>(0h0)))
node _r_ok_T_49 = xor(nodeIn.ar.bits.addr, UInt<32>(0h80000000))
node _r_ok_T_50 = cvt(_r_ok_T_49)
node _r_ok_T_51 = and(_r_ok_T_50, asSInt(UInt<15>(0h4000)))
node _r_ok_T_52 = asSInt(_r_ok_T_51)
node _r_ok_T_53 = eq(_r_ok_T_52, asSInt(UInt<1>(0h0)))
node _r_ok_T_54 = or(_r_ok_T_18, _r_ok_T_23)
node _r_ok_T_55 = or(_r_ok_T_54, _r_ok_T_28)
node _r_ok_T_56 = or(_r_ok_T_55, _r_ok_T_33)
node _r_ok_T_57 = or(_r_ok_T_56, _r_ok_T_38)
node _r_ok_T_58 = or(_r_ok_T_57, _r_ok_T_43)
node _r_ok_T_59 = or(_r_ok_T_58, _r_ok_T_48)
node _r_ok_T_60 = or(_r_ok_T_59, _r_ok_T_53)
node _r_ok_T_61 = and(_r_ok_T_13, _r_ok_T_60)
node _r_ok_T_62 = or(UInt<1>(0h0), _r_ok_T_9)
node r_ok = or(_r_ok_T_62, _r_ok_T_61)
node _r_addr_T = bits(nodeIn.ar.bits.addr, 2, 0)
node _r_addr_T_1 = or(UInt<14>(0h3000), _r_addr_T)
node r_addr = mux(r_ok, nodeIn.ar.bits.addr, _r_addr_T_1)
wire _r_count_WIRE : UInt<3>[2]
connect _r_count_WIRE[0], UInt<3>(0h0)
connect _r_count_WIRE[1], UInt<3>(0h0)
regreset r_count : UInt<3>[2], clock, reset, _r_count_WIRE
node _r_id_T = bits(r_count[nodeIn.ar.bits.id], 1, 0)
node r_id_hi = cat(nodeIn.ar.bits.id, _r_id_T)
node r_id = cat(r_id_hi, UInt<1>(0h0))
node _T = eq(nodeIn.ar.valid, UInt<1>(0h0))
node _T_1 = dshl(UInt<15>(0h7fff), r_size)
node _T_2 = bits(_T_1, 14, 0)
node _T_3 = not(_T_2)
node _T_4 = eq(r_size1, _T_3)
node _T_5 = or(_T, _T_4)
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ToTL.scala:114 assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned\n") : printf
assert(clock, _T_5, UInt<1>(0h1), "") : assert
connect nodeIn.ar.ready, r_out.ready
connect r_out.valid, nodeIn.ar.valid
node _r_out_bits_legal_T = leq(UInt<1>(0h0), r_size)
node _r_out_bits_legal_T_1 = leq(r_size, UInt<4>(0hc))
node _r_out_bits_legal_T_2 = and(_r_out_bits_legal_T, _r_out_bits_legal_T_1)
node _r_out_bits_legal_T_3 = or(UInt<1>(0h0), _r_out_bits_legal_T_2)
node _r_out_bits_legal_T_4 = xor(r_addr, UInt<14>(0h3000))
node _r_out_bits_legal_T_5 = cvt(_r_out_bits_legal_T_4)
node _r_out_bits_legal_T_6 = and(_r_out_bits_legal_T_5, asSInt(UInt<33>(0hca113000)))
node _r_out_bits_legal_T_7 = asSInt(_r_out_bits_legal_T_6)
node _r_out_bits_legal_T_8 = eq(_r_out_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_9 = and(_r_out_bits_legal_T_3, _r_out_bits_legal_T_8)
node _r_out_bits_legal_T_10 = leq(UInt<1>(0h0), r_size)
node _r_out_bits_legal_T_11 = leq(r_size, UInt<3>(0h6))
node _r_out_bits_legal_T_12 = and(_r_out_bits_legal_T_10, _r_out_bits_legal_T_11)
node _r_out_bits_legal_T_13 = or(UInt<1>(0h0), _r_out_bits_legal_T_12)
node _r_out_bits_legal_T_14 = xor(r_addr, UInt<1>(0h0))
node _r_out_bits_legal_T_15 = cvt(_r_out_bits_legal_T_14)
node _r_out_bits_legal_T_16 = and(_r_out_bits_legal_T_15, asSInt(UInt<33>(0hca112000)))
node _r_out_bits_legal_T_17 = asSInt(_r_out_bits_legal_T_16)
node _r_out_bits_legal_T_18 = eq(_r_out_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_19 = xor(r_addr, UInt<17>(0h10000))
node _r_out_bits_legal_T_20 = cvt(_r_out_bits_legal_T_19)
node _r_out_bits_legal_T_21 = and(_r_out_bits_legal_T_20, asSInt(UInt<33>(0hca110000)))
node _r_out_bits_legal_T_22 = asSInt(_r_out_bits_legal_T_21)
node _r_out_bits_legal_T_23 = eq(_r_out_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_24 = xor(r_addr, UInt<21>(0h100000))
node _r_out_bits_legal_T_25 = cvt(_r_out_bits_legal_T_24)
node _r_out_bits_legal_T_26 = and(_r_out_bits_legal_T_25, asSInt(UInt<33>(0hca103000)))
node _r_out_bits_legal_T_27 = asSInt(_r_out_bits_legal_T_26)
node _r_out_bits_legal_T_28 = eq(_r_out_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_29 = xor(r_addr, UInt<26>(0h2000000))
node _r_out_bits_legal_T_30 = cvt(_r_out_bits_legal_T_29)
node _r_out_bits_legal_T_31 = and(_r_out_bits_legal_T_30, asSInt(UInt<33>(0hca110000)))
node _r_out_bits_legal_T_32 = asSInt(_r_out_bits_legal_T_31)
node _r_out_bits_legal_T_33 = eq(_r_out_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_34 = xor(r_addr, UInt<28>(0h8000000))
node _r_out_bits_legal_T_35 = cvt(_r_out_bits_legal_T_34)
node _r_out_bits_legal_T_36 = and(_r_out_bits_legal_T_35, asSInt(UInt<33>(0hc8000000)))
node _r_out_bits_legal_T_37 = asSInt(_r_out_bits_legal_T_36)
node _r_out_bits_legal_T_38 = eq(_r_out_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_39 = xor(r_addr, UInt<31>(0h40000000))
node _r_out_bits_legal_T_40 = cvt(_r_out_bits_legal_T_39)
node _r_out_bits_legal_T_41 = and(_r_out_bits_legal_T_40, asSInt(UInt<33>(0hc0000000)))
node _r_out_bits_legal_T_42 = asSInt(_r_out_bits_legal_T_41)
node _r_out_bits_legal_T_43 = eq(_r_out_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_44 = xor(r_addr, UInt<32>(0h80000000))
node _r_out_bits_legal_T_45 = cvt(_r_out_bits_legal_T_44)
node _r_out_bits_legal_T_46 = and(_r_out_bits_legal_T_45, asSInt(UInt<33>(0hca110000)))
node _r_out_bits_legal_T_47 = asSInt(_r_out_bits_legal_T_46)
node _r_out_bits_legal_T_48 = eq(_r_out_bits_legal_T_47, asSInt(UInt<1>(0h0)))
node _r_out_bits_legal_T_49 = or(_r_out_bits_legal_T_18, _r_out_bits_legal_T_23)
node _r_out_bits_legal_T_50 = or(_r_out_bits_legal_T_49, _r_out_bits_legal_T_28)
node _r_out_bits_legal_T_51 = or(_r_out_bits_legal_T_50, _r_out_bits_legal_T_33)
node _r_out_bits_legal_T_52 = or(_r_out_bits_legal_T_51, _r_out_bits_legal_T_38)
node _r_out_bits_legal_T_53 = or(_r_out_bits_legal_T_52, _r_out_bits_legal_T_43)
node _r_out_bits_legal_T_54 = or(_r_out_bits_legal_T_53, _r_out_bits_legal_T_48)
node _r_out_bits_legal_T_55 = and(_r_out_bits_legal_T_13, _r_out_bits_legal_T_54)
node _r_out_bits_legal_T_56 = or(UInt<1>(0h0), _r_out_bits_legal_T_9)
node r_out_bits_legal = or(_r_out_bits_legal_T_56, _r_out_bits_legal_T_55)
wire r_out_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect r_out_bits_a.opcode, UInt<3>(0h4)
connect r_out_bits_a.param, UInt<1>(0h0)
connect r_out_bits_a.size, r_size
connect r_out_bits_a.source, r_id
connect r_out_bits_a.address, r_addr
invalidate r_out_bits_a.user.amba_prot.fetch
invalidate r_out_bits_a.user.amba_prot.secure
invalidate r_out_bits_a.user.amba_prot.privileged
invalidate r_out_bits_a.user.amba_prot.writealloc
invalidate r_out_bits_a.user.amba_prot.readalloc
invalidate r_out_bits_a.user.amba_prot.modifiable
invalidate r_out_bits_a.user.amba_prot.bufferable
node _r_out_bits_a_mask_sizeOH_T = or(r_size, UInt<3>(0h0))
node r_out_bits_a_mask_sizeOH_shiftAmount = bits(_r_out_bits_a_mask_sizeOH_T, 1, 0)
node _r_out_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), r_out_bits_a_mask_sizeOH_shiftAmount)
node _r_out_bits_a_mask_sizeOH_T_2 = bits(_r_out_bits_a_mask_sizeOH_T_1, 2, 0)
node r_out_bits_a_mask_sizeOH = or(_r_out_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node r_out_bits_a_mask_sub_sub_sub_0_1 = geq(r_size, UInt<2>(0h3))
node r_out_bits_a_mask_sub_sub_size = bits(r_out_bits_a_mask_sizeOH, 2, 2)
node r_out_bits_a_mask_sub_sub_bit = bits(r_addr, 2, 2)
node r_out_bits_a_mask_sub_sub_nbit = eq(r_out_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node r_out_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), r_out_bits_a_mask_sub_sub_nbit)
node _r_out_bits_a_mask_sub_sub_acc_T = and(r_out_bits_a_mask_sub_sub_size, r_out_bits_a_mask_sub_sub_0_2)
node r_out_bits_a_mask_sub_sub_0_1 = or(r_out_bits_a_mask_sub_sub_sub_0_1, _r_out_bits_a_mask_sub_sub_acc_T)
node r_out_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), r_out_bits_a_mask_sub_sub_bit)
node _r_out_bits_a_mask_sub_sub_acc_T_1 = and(r_out_bits_a_mask_sub_sub_size, r_out_bits_a_mask_sub_sub_1_2)
node r_out_bits_a_mask_sub_sub_1_1 = or(r_out_bits_a_mask_sub_sub_sub_0_1, _r_out_bits_a_mask_sub_sub_acc_T_1)
node r_out_bits_a_mask_sub_size = bits(r_out_bits_a_mask_sizeOH, 1, 1)
node r_out_bits_a_mask_sub_bit = bits(r_addr, 1, 1)
node r_out_bits_a_mask_sub_nbit = eq(r_out_bits_a_mask_sub_bit, UInt<1>(0h0))
node r_out_bits_a_mask_sub_0_2 = and(r_out_bits_a_mask_sub_sub_0_2, r_out_bits_a_mask_sub_nbit)
node _r_out_bits_a_mask_sub_acc_T = and(r_out_bits_a_mask_sub_size, r_out_bits_a_mask_sub_0_2)
node r_out_bits_a_mask_sub_0_1 = or(r_out_bits_a_mask_sub_sub_0_1, _r_out_bits_a_mask_sub_acc_T)
node r_out_bits_a_mask_sub_1_2 = and(r_out_bits_a_mask_sub_sub_0_2, r_out_bits_a_mask_sub_bit)
node _r_out_bits_a_mask_sub_acc_T_1 = and(r_out_bits_a_mask_sub_size, r_out_bits_a_mask_sub_1_2)
node r_out_bits_a_mask_sub_1_1 = or(r_out_bits_a_mask_sub_sub_0_1, _r_out_bits_a_mask_sub_acc_T_1)
node r_out_bits_a_mask_sub_2_2 = and(r_out_bits_a_mask_sub_sub_1_2, r_out_bits_a_mask_sub_nbit)
node _r_out_bits_a_mask_sub_acc_T_2 = and(r_out_bits_a_mask_sub_size, r_out_bits_a_mask_sub_2_2)
node r_out_bits_a_mask_sub_2_1 = or(r_out_bits_a_mask_sub_sub_1_1, _r_out_bits_a_mask_sub_acc_T_2)
node r_out_bits_a_mask_sub_3_2 = and(r_out_bits_a_mask_sub_sub_1_2, r_out_bits_a_mask_sub_bit)
node _r_out_bits_a_mask_sub_acc_T_3 = and(r_out_bits_a_mask_sub_size, r_out_bits_a_mask_sub_3_2)
node r_out_bits_a_mask_sub_3_1 = or(r_out_bits_a_mask_sub_sub_1_1, _r_out_bits_a_mask_sub_acc_T_3)
node r_out_bits_a_mask_size = bits(r_out_bits_a_mask_sizeOH, 0, 0)
node r_out_bits_a_mask_bit = bits(r_addr, 0, 0)
node r_out_bits_a_mask_nbit = eq(r_out_bits_a_mask_bit, UInt<1>(0h0))
node r_out_bits_a_mask_eq = and(r_out_bits_a_mask_sub_0_2, r_out_bits_a_mask_nbit)
node _r_out_bits_a_mask_acc_T = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq)
node r_out_bits_a_mask_acc = or(r_out_bits_a_mask_sub_0_1, _r_out_bits_a_mask_acc_T)
node r_out_bits_a_mask_eq_1 = and(r_out_bits_a_mask_sub_0_2, r_out_bits_a_mask_bit)
node _r_out_bits_a_mask_acc_T_1 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_1)
node r_out_bits_a_mask_acc_1 = or(r_out_bits_a_mask_sub_0_1, _r_out_bits_a_mask_acc_T_1)
node r_out_bits_a_mask_eq_2 = and(r_out_bits_a_mask_sub_1_2, r_out_bits_a_mask_nbit)
node _r_out_bits_a_mask_acc_T_2 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_2)
node r_out_bits_a_mask_acc_2 = or(r_out_bits_a_mask_sub_1_1, _r_out_bits_a_mask_acc_T_2)
node r_out_bits_a_mask_eq_3 = and(r_out_bits_a_mask_sub_1_2, r_out_bits_a_mask_bit)
node _r_out_bits_a_mask_acc_T_3 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_3)
node r_out_bits_a_mask_acc_3 = or(r_out_bits_a_mask_sub_1_1, _r_out_bits_a_mask_acc_T_3)
node r_out_bits_a_mask_eq_4 = and(r_out_bits_a_mask_sub_2_2, r_out_bits_a_mask_nbit)
node _r_out_bits_a_mask_acc_T_4 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_4)
node r_out_bits_a_mask_acc_4 = or(r_out_bits_a_mask_sub_2_1, _r_out_bits_a_mask_acc_T_4)
node r_out_bits_a_mask_eq_5 = and(r_out_bits_a_mask_sub_2_2, r_out_bits_a_mask_bit)
node _r_out_bits_a_mask_acc_T_5 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_5)
node r_out_bits_a_mask_acc_5 = or(r_out_bits_a_mask_sub_2_1, _r_out_bits_a_mask_acc_T_5)
node r_out_bits_a_mask_eq_6 = and(r_out_bits_a_mask_sub_3_2, r_out_bits_a_mask_nbit)
node _r_out_bits_a_mask_acc_T_6 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_6)
node r_out_bits_a_mask_acc_6 = or(r_out_bits_a_mask_sub_3_1, _r_out_bits_a_mask_acc_T_6)
node r_out_bits_a_mask_eq_7 = and(r_out_bits_a_mask_sub_3_2, r_out_bits_a_mask_bit)
node _r_out_bits_a_mask_acc_T_7 = and(r_out_bits_a_mask_size, r_out_bits_a_mask_eq_7)
node r_out_bits_a_mask_acc_7 = or(r_out_bits_a_mask_sub_3_1, _r_out_bits_a_mask_acc_T_7)
node r_out_bits_a_mask_lo_lo = cat(r_out_bits_a_mask_acc_1, r_out_bits_a_mask_acc)
node r_out_bits_a_mask_lo_hi = cat(r_out_bits_a_mask_acc_3, r_out_bits_a_mask_acc_2)
node r_out_bits_a_mask_lo = cat(r_out_bits_a_mask_lo_hi, r_out_bits_a_mask_lo_lo)
node r_out_bits_a_mask_hi_lo = cat(r_out_bits_a_mask_acc_5, r_out_bits_a_mask_acc_4)
node r_out_bits_a_mask_hi_hi = cat(r_out_bits_a_mask_acc_7, r_out_bits_a_mask_acc_6)
node r_out_bits_a_mask_hi = cat(r_out_bits_a_mask_hi_hi, r_out_bits_a_mask_hi_lo)
node _r_out_bits_a_mask_T = cat(r_out_bits_a_mask_hi, r_out_bits_a_mask_lo)
connect r_out_bits_a.mask, _r_out_bits_a_mask_T
invalidate r_out_bits_a.data
connect r_out_bits_a.corrupt, UInt<1>(0h0)
connect r_out.bits.corrupt, r_out_bits_a.corrupt
connect r_out.bits.data, r_out_bits_a.data
connect r_out.bits.mask, r_out_bits_a.mask
connect r_out.bits.user.amba_prot.fetch, r_out_bits_a.user.amba_prot.fetch
connect r_out.bits.user.amba_prot.secure, r_out_bits_a.user.amba_prot.secure
connect r_out.bits.user.amba_prot.privileged, r_out_bits_a.user.amba_prot.privileged
connect r_out.bits.user.amba_prot.writealloc, r_out_bits_a.user.amba_prot.writealloc
connect r_out.bits.user.amba_prot.readalloc, r_out_bits_a.user.amba_prot.readalloc
connect r_out.bits.user.amba_prot.modifiable, r_out_bits_a.user.amba_prot.modifiable
connect r_out.bits.user.amba_prot.bufferable, r_out_bits_a.user.amba_prot.bufferable
connect r_out.bits.address, r_out_bits_a.address
connect r_out.bits.source, r_out_bits_a.source
connect r_out.bits.size, r_out_bits_a.size
connect r_out.bits.param, r_out_bits_a.param
connect r_out.bits.opcode, r_out_bits_a.opcode
node _r_out_bits_user_amba_prot_privileged_T = bits(nodeIn.ar.bits.prot, 0, 0)
connect r_out.bits.user.amba_prot.privileged, _r_out_bits_user_amba_prot_privileged_T
node _r_out_bits_user_amba_prot_secure_T = bits(nodeIn.ar.bits.prot, 1, 1)
node _r_out_bits_user_amba_prot_secure_T_1 = eq(_r_out_bits_user_amba_prot_secure_T, UInt<1>(0h0))
connect r_out.bits.user.amba_prot.secure, _r_out_bits_user_amba_prot_secure_T_1
node _r_out_bits_user_amba_prot_fetch_T = bits(nodeIn.ar.bits.prot, 2, 2)
connect r_out.bits.user.amba_prot.fetch, _r_out_bits_user_amba_prot_fetch_T
node _r_out_bits_user_amba_prot_bufferable_T = bits(nodeIn.ar.bits.cache, 0, 0)
connect r_out.bits.user.amba_prot.bufferable, _r_out_bits_user_amba_prot_bufferable_T
node _r_out_bits_user_amba_prot_modifiable_T = bits(nodeIn.ar.bits.cache, 1, 1)
connect r_out.bits.user.amba_prot.modifiable, _r_out_bits_user_amba_prot_modifiable_T
node _r_out_bits_user_amba_prot_readalloc_T = bits(nodeIn.ar.bits.cache, 2, 2)
connect r_out.bits.user.amba_prot.readalloc, _r_out_bits_user_amba_prot_readalloc_T
node _r_out_bits_user_amba_prot_writealloc_T = bits(nodeIn.ar.bits.cache, 3, 3)
connect r_out.bits.user.amba_prot.writealloc, _r_out_bits_user_amba_prot_writealloc_T
node r_sel_shiftAmount = bits(nodeIn.ar.bits.id, 0, 0)
node _r_sel_T = dshl(UInt<1>(0h1), r_sel_shiftAmount)
node r_sel = bits(_r_sel_T, 1, 0)
node _T_9 = bits(r_sel, 0, 0)
node _T_10 = bits(r_sel, 1, 1)
node _T_11 = and(nodeIn.ar.ready, nodeIn.ar.valid)
node _T_12 = and(_T_11, _T_9)
when _T_12 :
node _r_count_0_T = add(r_count[0], UInt<1>(0h1))
node _r_count_0_T_1 = tail(_r_count_0_T, 1)
connect r_count[0], _r_count_0_T_1
node _T_13 = and(nodeIn.ar.ready, nodeIn.ar.valid)
node _T_14 = and(_T_13, _T_10)
when _T_14 :
node _r_count_1_T = add(r_count[1], UInt<1>(0h1))
node _r_count_1_T_1 = tail(_r_count_1_T, 1)
connect r_count[1], _r_count_1_T_1
wire w_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect w_out.bits, nodeOut.a.bits
connect w_out.valid, nodeOut.a.valid
connect w_out.ready, nodeOut.a.ready
node _w_size1_T = cat(nodeIn.aw.bits.len, UInt<8>(0hff))
node _w_size1_T_1 = dshl(_w_size1_T, nodeIn.aw.bits.size)
node w_size1 = shr(_w_size1_T_1, 8)
node _w_size_T = shl(w_size1, 1)
node _w_size_T_1 = or(_w_size_T, UInt<1>(0h1))
node _w_size_T_2 = cat(UInt<1>(0h0), w_size1)
node _w_size_T_3 = not(_w_size_T_2)
node _w_size_T_4 = and(_w_size_T_1, _w_size_T_3)
node w_size_hi = bits(_w_size_T_4, 15, 8)
node w_size_lo = bits(_w_size_T_4, 7, 0)
node _w_size_T_5 = orr(w_size_hi)
node _w_size_T_6 = or(w_size_hi, w_size_lo)
node w_size_hi_1 = bits(_w_size_T_6, 7, 4)
node w_size_lo_1 = bits(_w_size_T_6, 3, 0)
node _w_size_T_7 = orr(w_size_hi_1)
node _w_size_T_8 = or(w_size_hi_1, w_size_lo_1)
node w_size_hi_2 = bits(_w_size_T_8, 3, 2)
node w_size_lo_2 = bits(_w_size_T_8, 1, 0)
node _w_size_T_9 = orr(w_size_hi_2)
node _w_size_T_10 = or(w_size_hi_2, w_size_lo_2)
node _w_size_T_11 = bits(_w_size_T_10, 1, 1)
node _w_size_T_12 = cat(_w_size_T_9, _w_size_T_11)
node _w_size_T_13 = cat(_w_size_T_7, _w_size_T_12)
node w_size = cat(_w_size_T_5, _w_size_T_13)
node _w_ok_T = leq(UInt<1>(0h0), w_size)
node _w_ok_T_1 = leq(w_size, UInt<4>(0hc))
node _w_ok_T_2 = and(_w_ok_T, _w_ok_T_1)
node _w_ok_T_3 = or(UInt<1>(0h0), _w_ok_T_2)
node _w_ok_T_4 = xor(nodeIn.aw.bits.addr, UInt<14>(0h3000))
node _w_ok_T_5 = cvt(_w_ok_T_4)
node _w_ok_T_6 = and(_w_ok_T_5, asSInt(UInt<13>(0h1000)))
node _w_ok_T_7 = asSInt(_w_ok_T_6)
node _w_ok_T_8 = eq(_w_ok_T_7, asSInt(UInt<1>(0h0)))
node _w_ok_T_9 = and(_w_ok_T_3, _w_ok_T_8)
node _w_ok_T_10 = leq(UInt<1>(0h0), w_size)
node _w_ok_T_11 = leq(w_size, UInt<3>(0h6))
node _w_ok_T_12 = and(_w_ok_T_10, _w_ok_T_11)
node _w_ok_T_13 = or(UInt<1>(0h0), _w_ok_T_12)
node _w_ok_T_14 = xor(nodeIn.aw.bits.addr, UInt<1>(0h0))
node _w_ok_T_15 = cvt(_w_ok_T_14)
node _w_ok_T_16 = and(_w_ok_T_15, asSInt(UInt<14>(0h2000)))
node _w_ok_T_17 = asSInt(_w_ok_T_16)
node _w_ok_T_18 = eq(_w_ok_T_17, asSInt(UInt<1>(0h0)))
node _w_ok_T_19 = xor(nodeIn.aw.bits.addr, UInt<21>(0h100000))
node _w_ok_T_20 = cvt(_w_ok_T_19)
node _w_ok_T_21 = and(_w_ok_T_20, asSInt(UInt<18>(0h2f000)))
node _w_ok_T_22 = asSInt(_w_ok_T_21)
node _w_ok_T_23 = eq(_w_ok_T_22, asSInt(UInt<1>(0h0)))
node _w_ok_T_24 = xor(nodeIn.aw.bits.addr, UInt<26>(0h2000000))
node _w_ok_T_25 = cvt(_w_ok_T_24)
node _w_ok_T_26 = and(_w_ok_T_25, asSInt(UInt<17>(0h10000)))
node _w_ok_T_27 = asSInt(_w_ok_T_26)
node _w_ok_T_28 = eq(_w_ok_T_27, asSInt(UInt<1>(0h0)))
node _w_ok_T_29 = xor(nodeIn.aw.bits.addr, UInt<28>(0hc000000))
node _w_ok_T_30 = cvt(_w_ok_T_29)
node _w_ok_T_31 = and(_w_ok_T_30, asSInt(UInt<27>(0h4000000)))
node _w_ok_T_32 = asSInt(_w_ok_T_31)
node _w_ok_T_33 = eq(_w_ok_T_32, asSInt(UInt<1>(0h0)))
node _w_ok_T_34 = xor(nodeIn.aw.bits.addr, UInt<29>(0h10020000))
node _w_ok_T_35 = cvt(_w_ok_T_34)
node _w_ok_T_36 = and(_w_ok_T_35, asSInt(UInt<13>(0h1000)))
node _w_ok_T_37 = asSInt(_w_ok_T_36)
node _w_ok_T_38 = eq(_w_ok_T_37, asSInt(UInt<1>(0h0)))
node _w_ok_T_39 = xor(nodeIn.aw.bits.addr, UInt<32>(0h80000000))
node _w_ok_T_40 = cvt(_w_ok_T_39)
node _w_ok_T_41 = and(_w_ok_T_40, asSInt(UInt<15>(0h4000)))
node _w_ok_T_42 = asSInt(_w_ok_T_41)
node _w_ok_T_43 = eq(_w_ok_T_42, asSInt(UInt<1>(0h0)))
node _w_ok_T_44 = or(_w_ok_T_18, _w_ok_T_23)
node _w_ok_T_45 = or(_w_ok_T_44, _w_ok_T_28)
node _w_ok_T_46 = or(_w_ok_T_45, _w_ok_T_33)
node _w_ok_T_47 = or(_w_ok_T_46, _w_ok_T_38)
node _w_ok_T_48 = or(_w_ok_T_47, _w_ok_T_43)
node _w_ok_T_49 = and(_w_ok_T_13, _w_ok_T_48)
node _w_ok_T_50 = or(UInt<1>(0h0), UInt<1>(0h0))
node _w_ok_T_51 = xor(nodeIn.aw.bits.addr, UInt<17>(0h10000))
node _w_ok_T_52 = cvt(_w_ok_T_51)
node _w_ok_T_53 = and(_w_ok_T_52, asSInt(UInt<17>(0h10000)))
node _w_ok_T_54 = asSInt(_w_ok_T_53)
node _w_ok_T_55 = eq(_w_ok_T_54, asSInt(UInt<1>(0h0)))
node _w_ok_T_56 = and(_w_ok_T_50, _w_ok_T_55)
node _w_ok_T_57 = leq(UInt<1>(0h0), w_size)
node _w_ok_T_58 = leq(w_size, UInt<4>(0h8))
node _w_ok_T_59 = and(_w_ok_T_57, _w_ok_T_58)
node _w_ok_T_60 = or(UInt<1>(0h0), _w_ok_T_59)
node _w_ok_T_61 = xor(nodeIn.aw.bits.addr, UInt<31>(0h60000000))
node _w_ok_T_62 = cvt(_w_ok_T_61)
node _w_ok_T_63 = and(_w_ok_T_62, asSInt(UInt<30>(0h20000000)))
node _w_ok_T_64 = asSInt(_w_ok_T_63)
node _w_ok_T_65 = eq(_w_ok_T_64, asSInt(UInt<1>(0h0)))
node _w_ok_T_66 = and(_w_ok_T_60, _w_ok_T_65)
node _w_ok_T_67 = or(UInt<1>(0h0), _w_ok_T_9)
node _w_ok_T_68 = or(_w_ok_T_67, _w_ok_T_49)
node _w_ok_T_69 = or(_w_ok_T_68, _w_ok_T_56)
node w_ok = or(_w_ok_T_69, _w_ok_T_66)
node _w_addr_T = bits(nodeIn.aw.bits.addr, 2, 0)
node _w_addr_T_1 = or(UInt<14>(0h3000), _w_addr_T)
node w_addr = mux(w_ok, nodeIn.aw.bits.addr, _w_addr_T_1)
wire _w_count_WIRE : UInt<3>[2]
connect _w_count_WIRE[0], UInt<3>(0h0)
connect _w_count_WIRE[1], UInt<3>(0h0)
regreset w_count : UInt<3>[2], clock, reset, _w_count_WIRE
node _w_id_T = bits(w_count[nodeIn.aw.bits.id], 1, 0)
node w_id_hi = cat(nodeIn.aw.bits.id, _w_id_T)
node w_id = cat(w_id_hi, UInt<1>(0h1))
node _T_15 = eq(nodeIn.aw.valid, UInt<1>(0h0))
node _T_16 = dshl(UInt<15>(0h7fff), w_size)
node _T_17 = bits(_T_16, 14, 0)
node _T_18 = not(_T_17)
node _T_19 = eq(w_size1, _T_18)
node _T_20 = or(_T_15, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ToTL.scala:150 assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(nodeIn.aw.valid, UInt<1>(0h0))
node _T_25 = eq(nodeIn.aw.bits.len, UInt<1>(0h0))
node _T_26 = or(_T_24, _T_25)
node _T_27 = eq(nodeIn.aw.bits.size, UInt<2>(0h3))
node _T_28 = or(_T_26, _T_27)
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ToTL.scala:151 assert (!in.aw.valid || in.aw.bits.len === 0.U || in.aw.bits.size === log2Ceil(beatBytes).U) // because aligned\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
node _nodeIn_aw_ready_T = and(w_out.ready, nodeIn.w.valid)
node _nodeIn_aw_ready_T_1 = and(_nodeIn_aw_ready_T, nodeIn.w.bits.last)
connect nodeIn.aw.ready, _nodeIn_aw_ready_T_1
node _nodeIn_w_ready_T = and(w_out.ready, nodeIn.aw.valid)
connect nodeIn.w.ready, _nodeIn_w_ready_T
node _w_out_valid_T = and(nodeIn.aw.valid, nodeIn.w.valid)
connect w_out.valid, _w_out_valid_T
node _w_out_bits_legal_T = leq(UInt<1>(0h0), w_size)
node _w_out_bits_legal_T_1 = leq(w_size, UInt<4>(0hc))
node _w_out_bits_legal_T_2 = and(_w_out_bits_legal_T, _w_out_bits_legal_T_1)
node _w_out_bits_legal_T_3 = or(UInt<1>(0h0), _w_out_bits_legal_T_2)
node _w_out_bits_legal_T_4 = xor(w_addr, UInt<14>(0h3000))
node _w_out_bits_legal_T_5 = cvt(_w_out_bits_legal_T_4)
node _w_out_bits_legal_T_6 = and(_w_out_bits_legal_T_5, asSInt(UInt<33>(0hca113000)))
node _w_out_bits_legal_T_7 = asSInt(_w_out_bits_legal_T_6)
node _w_out_bits_legal_T_8 = eq(_w_out_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_9 = and(_w_out_bits_legal_T_3, _w_out_bits_legal_T_8)
node _w_out_bits_legal_T_10 = leq(UInt<1>(0h0), w_size)
node _w_out_bits_legal_T_11 = leq(w_size, UInt<3>(0h6))
node _w_out_bits_legal_T_12 = and(_w_out_bits_legal_T_10, _w_out_bits_legal_T_11)
node _w_out_bits_legal_T_13 = or(UInt<1>(0h0), _w_out_bits_legal_T_12)
node _w_out_bits_legal_T_14 = xor(w_addr, UInt<1>(0h0))
node _w_out_bits_legal_T_15 = cvt(_w_out_bits_legal_T_14)
node _w_out_bits_legal_T_16 = and(_w_out_bits_legal_T_15, asSInt(UInt<33>(0hca112000)))
node _w_out_bits_legal_T_17 = asSInt(_w_out_bits_legal_T_16)
node _w_out_bits_legal_T_18 = eq(_w_out_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_19 = xor(w_addr, UInt<21>(0h100000))
node _w_out_bits_legal_T_20 = cvt(_w_out_bits_legal_T_19)
node _w_out_bits_legal_T_21 = and(_w_out_bits_legal_T_20, asSInt(UInt<33>(0hca103000)))
node _w_out_bits_legal_T_22 = asSInt(_w_out_bits_legal_T_21)
node _w_out_bits_legal_T_23 = eq(_w_out_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_24 = xor(w_addr, UInt<26>(0h2000000))
node _w_out_bits_legal_T_25 = cvt(_w_out_bits_legal_T_24)
node _w_out_bits_legal_T_26 = and(_w_out_bits_legal_T_25, asSInt(UInt<33>(0hca110000)))
node _w_out_bits_legal_T_27 = asSInt(_w_out_bits_legal_T_26)
node _w_out_bits_legal_T_28 = eq(_w_out_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_29 = xor(w_addr, UInt<28>(0h8000000))
node _w_out_bits_legal_T_30 = cvt(_w_out_bits_legal_T_29)
node _w_out_bits_legal_T_31 = and(_w_out_bits_legal_T_30, asSInt(UInt<33>(0hc8000000)))
node _w_out_bits_legal_T_32 = asSInt(_w_out_bits_legal_T_31)
node _w_out_bits_legal_T_33 = eq(_w_out_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_34 = xor(w_addr, UInt<32>(0h80000000))
node _w_out_bits_legal_T_35 = cvt(_w_out_bits_legal_T_34)
node _w_out_bits_legal_T_36 = and(_w_out_bits_legal_T_35, asSInt(UInt<33>(0hca110000)))
node _w_out_bits_legal_T_37 = asSInt(_w_out_bits_legal_T_36)
node _w_out_bits_legal_T_38 = eq(_w_out_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_39 = or(_w_out_bits_legal_T_18, _w_out_bits_legal_T_23)
node _w_out_bits_legal_T_40 = or(_w_out_bits_legal_T_39, _w_out_bits_legal_T_28)
node _w_out_bits_legal_T_41 = or(_w_out_bits_legal_T_40, _w_out_bits_legal_T_33)
node _w_out_bits_legal_T_42 = or(_w_out_bits_legal_T_41, _w_out_bits_legal_T_38)
node _w_out_bits_legal_T_43 = and(_w_out_bits_legal_T_13, _w_out_bits_legal_T_42)
node _w_out_bits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _w_out_bits_legal_T_45 = xor(w_addr, UInt<17>(0h10000))
node _w_out_bits_legal_T_46 = cvt(_w_out_bits_legal_T_45)
node _w_out_bits_legal_T_47 = and(_w_out_bits_legal_T_46, asSInt(UInt<33>(0hca110000)))
node _w_out_bits_legal_T_48 = asSInt(_w_out_bits_legal_T_47)
node _w_out_bits_legal_T_49 = eq(_w_out_bits_legal_T_48, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_50 = and(_w_out_bits_legal_T_44, _w_out_bits_legal_T_49)
node _w_out_bits_legal_T_51 = leq(UInt<1>(0h0), w_size)
node _w_out_bits_legal_T_52 = leq(w_size, UInt<4>(0h8))
node _w_out_bits_legal_T_53 = and(_w_out_bits_legal_T_51, _w_out_bits_legal_T_52)
node _w_out_bits_legal_T_54 = or(UInt<1>(0h0), _w_out_bits_legal_T_53)
node _w_out_bits_legal_T_55 = xor(w_addr, UInt<31>(0h40000000))
node _w_out_bits_legal_T_56 = cvt(_w_out_bits_legal_T_55)
node _w_out_bits_legal_T_57 = and(_w_out_bits_legal_T_56, asSInt(UInt<33>(0hc0000000)))
node _w_out_bits_legal_T_58 = asSInt(_w_out_bits_legal_T_57)
node _w_out_bits_legal_T_59 = eq(_w_out_bits_legal_T_58, asSInt(UInt<1>(0h0)))
node _w_out_bits_legal_T_60 = and(_w_out_bits_legal_T_54, _w_out_bits_legal_T_59)
node _w_out_bits_legal_T_61 = or(UInt<1>(0h0), _w_out_bits_legal_T_9)
node _w_out_bits_legal_T_62 = or(_w_out_bits_legal_T_61, _w_out_bits_legal_T_43)
node _w_out_bits_legal_T_63 = or(_w_out_bits_legal_T_62, _w_out_bits_legal_T_50)
node w_out_bits_legal = or(_w_out_bits_legal_T_63, _w_out_bits_legal_T_60)
wire w_out_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect w_out_bits_a.opcode, UInt<1>(0h1)
connect w_out_bits_a.param, UInt<1>(0h0)
connect w_out_bits_a.size, w_size
connect w_out_bits_a.source, w_id
connect w_out_bits_a.address, w_addr
invalidate w_out_bits_a.user.amba_prot.fetch
invalidate w_out_bits_a.user.amba_prot.secure
invalidate w_out_bits_a.user.amba_prot.privileged
invalidate w_out_bits_a.user.amba_prot.writealloc
invalidate w_out_bits_a.user.amba_prot.readalloc
invalidate w_out_bits_a.user.amba_prot.modifiable
invalidate w_out_bits_a.user.amba_prot.bufferable
connect w_out_bits_a.mask, nodeIn.w.bits.strb
connect w_out_bits_a.data, nodeIn.w.bits.data
connect w_out_bits_a.corrupt, UInt<1>(0h0)
connect w_out.bits.corrupt, w_out_bits_a.corrupt
connect w_out.bits.data, w_out_bits_a.data
connect w_out.bits.mask, w_out_bits_a.mask
connect w_out.bits.user.amba_prot.fetch, w_out_bits_a.user.amba_prot.fetch
connect w_out.bits.user.amba_prot.secure, w_out_bits_a.user.amba_prot.secure
connect w_out.bits.user.amba_prot.privileged, w_out_bits_a.user.amba_prot.privileged
connect w_out.bits.user.amba_prot.writealloc, w_out_bits_a.user.amba_prot.writealloc
connect w_out.bits.user.amba_prot.readalloc, w_out_bits_a.user.amba_prot.readalloc
connect w_out.bits.user.amba_prot.modifiable, w_out_bits_a.user.amba_prot.modifiable
connect w_out.bits.user.amba_prot.bufferable, w_out_bits_a.user.amba_prot.bufferable
connect w_out.bits.address, w_out_bits_a.address
connect w_out.bits.source, w_out_bits_a.source
connect w_out.bits.size, w_out_bits_a.size
connect w_out.bits.param, w_out_bits_a.param
connect w_out.bits.opcode, w_out_bits_a.opcode
node _w_out_bits_user_amba_prot_privileged_T = bits(nodeIn.aw.bits.prot, 0, 0)
connect w_out.bits.user.amba_prot.privileged, _w_out_bits_user_amba_prot_privileged_T
node _w_out_bits_user_amba_prot_secure_T = bits(nodeIn.aw.bits.prot, 1, 1)
node _w_out_bits_user_amba_prot_secure_T_1 = eq(_w_out_bits_user_amba_prot_secure_T, UInt<1>(0h0))
connect w_out.bits.user.amba_prot.secure, _w_out_bits_user_amba_prot_secure_T_1
node _w_out_bits_user_amba_prot_fetch_T = bits(nodeIn.aw.bits.prot, 2, 2)
connect w_out.bits.user.amba_prot.fetch, _w_out_bits_user_amba_prot_fetch_T
node _w_out_bits_user_amba_prot_bufferable_T = bits(nodeIn.aw.bits.cache, 0, 0)
connect w_out.bits.user.amba_prot.bufferable, _w_out_bits_user_amba_prot_bufferable_T
node _w_out_bits_user_amba_prot_modifiable_T = bits(nodeIn.aw.bits.cache, 1, 1)
connect w_out.bits.user.amba_prot.modifiable, _w_out_bits_user_amba_prot_modifiable_T
node _w_out_bits_user_amba_prot_readalloc_T = bits(nodeIn.aw.bits.cache, 2, 2)
connect w_out.bits.user.amba_prot.readalloc, _w_out_bits_user_amba_prot_readalloc_T
node _w_out_bits_user_amba_prot_writealloc_T = bits(nodeIn.aw.bits.cache, 3, 3)
connect w_out.bits.user.amba_prot.writealloc, _w_out_bits_user_amba_prot_writealloc_T
node w_sel_shiftAmount = bits(nodeIn.aw.bits.id, 0, 0)
node _w_sel_T = dshl(UInt<1>(0h1), w_sel_shiftAmount)
node w_sel = bits(_w_sel_T, 1, 0)
node _T_32 = bits(w_sel, 0, 0)
node _T_33 = bits(w_sel, 1, 1)
node _T_34 = and(nodeIn.aw.ready, nodeIn.aw.valid)
node _T_35 = and(_T_34, _T_32)
when _T_35 :
node _w_count_0_T = add(w_count[0], UInt<1>(0h1))
node _w_count_0_T_1 = tail(_w_count_0_T, 1)
connect w_count[0], _w_count_0_T_1
node _T_36 = and(nodeIn.aw.ready, nodeIn.aw.valid)
node _T_37 = and(_T_36, _T_33)
when _T_37 :
node _w_count_1_T = add(w_count[1], UInt<1>(0h1))
node _w_count_1_T_1 = tail(_w_count_1_T, 1)
connect w_count[1], _w_count_1_T_1
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(w_out.valid, r_out.valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], r_out.valid)
node _winner_T_1 = and(readys[1], w_out.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_39 = eq(winner[0], UInt<1>(0h0))
node _T_40 = or(_T_38, _T_39)
node _T_41 = eq(prefixOR_1, UInt<1>(0h0))
node _T_42 = eq(winner[1], UInt<1>(0h0))
node _T_43 = or(_T_41, _T_42)
node _T_44 = and(_T_40, _T_43)
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
node _T_47 = eq(_T_44, UInt<1>(0h0))
when _T_47 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_3
assert(clock, _T_44, UInt<1>(0h1), "") : assert_3
node _T_48 = or(r_out.valid, w_out.valid)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = or(winner[0], winner[1])
node _T_51 = or(_T_49, _T_50)
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
node _T_54 = eq(_T_51, UInt<1>(0h0))
when _T_54 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_4
assert(clock, _T_51, UInt<1>(0h1), "") : assert_4
node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], nodeIn.aw.bits.len, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _r_out_ready_T = and(nodeOut.a.ready, allowed[0])
connect r_out.ready, _r_out_ready_T
node _w_out_ready_T = and(nodeOut.a.ready, allowed[1])
connect w_out.ready, _w_out_ready_T
node _nodeOut_a_valid_T = or(r_out.valid, w_out.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], r_out.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], w_out.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], r_out.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], w_out.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], r_out.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], w_out.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], r_out.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], w_out.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}
wire _nodeOut_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}
node _nodeOut_a_bits_T_9 = mux(muxState[0], r_out.bits.user.amba_prot.fetch, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], w_out.bits.user.amba_prot.fetch, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_7 : UInt<1>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE_6.fetch, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_12 = mux(muxState[0], r_out.bits.user.amba_prot.secure, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], w_out.bits.user.amba_prot.secure, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_8 : UInt<1>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE_6.secure, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_15 = mux(muxState[0], r_out.bits.user.amba_prot.privileged, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], w_out.bits.user.amba_prot.privileged, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_9 : UInt<1>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE_6.privileged, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_18 = mux(muxState[0], r_out.bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], w_out.bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_10 : UInt<1>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE_6.writealloc, _nodeOut_a_bits_WIRE_10
node _nodeOut_a_bits_T_21 = mux(muxState[0], r_out.bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], w_out.bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_11 : UInt<1>
connect _nodeOut_a_bits_WIRE_11, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE_6.readalloc, _nodeOut_a_bits_WIRE_11
node _nodeOut_a_bits_T_24 = mux(muxState[0], r_out.bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _nodeOut_a_bits_T_25 = mux(muxState[1], w_out.bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25)
wire _nodeOut_a_bits_WIRE_12 : UInt<1>
connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26
connect _nodeOut_a_bits_WIRE_6.modifiable, _nodeOut_a_bits_WIRE_12
node _nodeOut_a_bits_T_27 = mux(muxState[0], r_out.bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _nodeOut_a_bits_T_28 = mux(muxState[1], w_out.bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28)
wire _nodeOut_a_bits_WIRE_13 : UInt<1>
connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29
connect _nodeOut_a_bits_WIRE_6.bufferable, _nodeOut_a_bits_WIRE_13
connect _nodeOut_a_bits_WIRE_5.amba_prot, _nodeOut_a_bits_WIRE_6
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_30 = mux(muxState[0], r_out.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_31 = mux(muxState[1], w_out.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31)
wire _nodeOut_a_bits_WIRE_14 : UInt<32>
connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_14
node _nodeOut_a_bits_T_33 = mux(muxState[0], r_out.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_34 = mux(muxState[1], w_out.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34)
wire _nodeOut_a_bits_WIRE_15 : UInt<4>
connect _nodeOut_a_bits_WIRE_15, _nodeOut_a_bits_T_35
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_15
node _nodeOut_a_bits_T_36 = mux(muxState[0], r_out.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_37 = mux(muxState[1], w_out.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37)
wire _nodeOut_a_bits_WIRE_16 : UInt<4>
connect _nodeOut_a_bits_WIRE_16, _nodeOut_a_bits_T_38
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_16
node _nodeOut_a_bits_T_39 = mux(muxState[0], r_out.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_40 = mux(muxState[1], w_out.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40)
wire _nodeOut_a_bits_WIRE_17 : UInt<3>
connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_41
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_17
node _nodeOut_a_bits_T_42 = mux(muxState[0], r_out.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_43 = mux(muxState[1], w_out.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43)
wire _nodeOut_a_bits_WIRE_18 : UInt<3>
connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_44
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_18
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.user.amba_prot.fetch, _nodeOut_a_bits_WIRE.user.amba_prot.fetch
connect nodeOut.a.bits.user.amba_prot.secure, _nodeOut_a_bits_WIRE.user.amba_prot.secure
connect nodeOut.a.bits.user.amba_prot.privileged, _nodeOut_a_bits_WIRE.user.amba_prot.privileged
connect nodeOut.a.bits.user.amba_prot.writealloc, _nodeOut_a_bits_WIRE.user.amba_prot.writealloc
connect nodeOut.a.bits.user.amba_prot.readalloc, _nodeOut_a_bits_WIRE.user.amba_prot.readalloc
connect nodeOut.a.bits.user.amba_prot.modifiable, _nodeOut_a_bits_WIRE.user.amba_prot.modifiable
connect nodeOut.a.bits.user.amba_prot.bufferable, _nodeOut_a_bits_WIRE.user.amba_prot.bufferable
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
wire ok_b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { }}}
connect ok_b.bits.resp, nodeIn.b.bits.resp
connect ok_b.bits.id, nodeIn.b.bits.id
connect ok_b.valid, nodeIn.b.valid
connect ok_b.ready, nodeIn.b.ready
wire ok_r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}
connect ok_r.bits.last, nodeIn.r.bits.last
connect ok_r.bits.resp, nodeIn.r.bits.resp
connect ok_r.bits.data, nodeIn.r.bits.data
connect ok_r.bits.id, nodeIn.r.bits.id
connect ok_r.valid, nodeIn.r.valid
connect ok_r.ready, nodeIn.r.ready
node _d_resp_T = or(nodeOut.d.bits.denied, nodeOut.d.bits.corrupt)
node d_resp = mux(_d_resp_T, UInt<2>(0h2), UInt<2>(0h0))
node d_hasData = bits(nodeOut.d.bits.opcode, 0, 0)
node _d_last_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _d_last_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _d_last_beats1_decode_T_1 = bits(_d_last_beats1_decode_T, 11, 0)
node _d_last_beats1_decode_T_2 = not(_d_last_beats1_decode_T_1)
node d_last_beats1_decode = shr(_d_last_beats1_decode_T_2, 3)
node d_last_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node d_last_beats1 = mux(d_last_beats1_opdata, d_last_beats1_decode, UInt<1>(0h0))
regreset d_last_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_last_counter1_T = sub(d_last_counter, UInt<1>(0h1))
node d_last_counter1 = tail(_d_last_counter1_T, 1)
node d_last_first = eq(d_last_counter, UInt<1>(0h0))
node _d_last_last_T = eq(d_last_counter, UInt<1>(0h1))
node _d_last_last_T_1 = eq(d_last_beats1, UInt<1>(0h0))
node d_last = or(_d_last_last_T, _d_last_last_T_1)
node d_last_done = and(d_last, _d_last_T)
node _d_last_count_T = not(d_last_counter1)
node d_last_count = and(d_last_beats1, _d_last_count_T)
when _d_last_T :
node _d_last_counter_T = mux(d_last_first, d_last_beats1, d_last_counter1)
connect d_last_counter, _d_last_counter_T
node _nodeOut_d_ready_T = mux(d_hasData, ok_r.ready, ok_b.ready)
connect nodeOut.d.ready, _nodeOut_d_ready_T
node _ok_r_valid_T = and(nodeOut.d.valid, d_hasData)
connect ok_r.valid, _ok_r_valid_T
node _ok_b_valid_T = eq(d_hasData, UInt<1>(0h0))
node _ok_b_valid_T_1 = and(nodeOut.d.valid, _ok_b_valid_T)
connect ok_b.valid, _ok_b_valid_T_1
node _ok_r_bits_id_T = shr(nodeOut.d.bits.source, 3)
connect ok_r.bits.id, _ok_r_bits_id_T
connect ok_r.bits.data, nodeOut.d.bits.data
connect ok_r.bits.resp, d_resp
connect ok_r.bits.last, d_last
inst nodeIn_r_deq_q of Queue1_AXI4BundleR
connect nodeIn_r_deq_q.clock, clock
connect nodeIn_r_deq_q.reset, reset
connect nodeIn_r_deq_q.io.enq.valid, ok_r.valid
connect nodeIn_r_deq_q.io.enq.bits.last, ok_r.bits.last
connect nodeIn_r_deq_q.io.enq.bits.resp, ok_r.bits.resp
connect nodeIn_r_deq_q.io.enq.bits.data, ok_r.bits.data
connect nodeIn_r_deq_q.io.enq.bits.id, ok_r.bits.id
connect ok_r.ready, nodeIn_r_deq_q.io.enq.ready
wire nodeIn_r_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}
connect nodeIn_r_irr.bits, nodeIn_r_deq_q.io.deq.bits
connect nodeIn_r_irr.valid, nodeIn_r_deq_q.io.deq.valid
connect nodeIn_r_deq_q.io.deq.ready, nodeIn_r_irr.ready
connect nodeIn.r, nodeIn_r_irr
node _ok_b_bits_id_T = shr(nodeOut.d.bits.source, 3)
connect ok_b.bits.id, _ok_b_bits_id_T
connect ok_b.bits.resp, d_resp
inst q_b_deq_q of Queue1_AXI4BundleB
connect q_b_deq_q.clock, clock
connect q_b_deq_q.reset, reset
connect q_b_deq_q.io.enq.valid, ok_b.valid
connect q_b_deq_q.io.enq.bits.resp, ok_b.bits.resp
connect q_b_deq_q.io.enq.bits.id, ok_b.bits.id
connect ok_b.ready, q_b_deq_q.io.enq.ready
wire q_b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { }}}
connect q_b.bits, q_b_deq_q.io.deq.bits
connect q_b.valid, q_b_deq_q.io.deq.valid
connect q_b_deq_q.io.deq.ready, q_b.ready
wire _b_count_WIRE : UInt<3>[2]
connect _b_count_WIRE[0], UInt<3>(0h0)
connect _b_count_WIRE[1], UInt<3>(0h0)
regreset b_count : UInt<3>[2], clock, reset, _b_count_WIRE
node b_allow = neq(b_count[nodeIn.b.bits.id], w_count[nodeIn.b.bits.id])
node b_sel_shiftAmount = bits(nodeIn.b.bits.id, 0, 0)
node _b_sel_T = dshl(UInt<1>(0h1), b_sel_shiftAmount)
node b_sel = bits(_b_sel_T, 1, 0)
node _T_55 = bits(b_sel, 0, 0)
node _T_56 = bits(b_sel, 1, 1)
node _T_57 = and(nodeIn.b.ready, nodeIn.b.valid)
node _T_58 = and(_T_57, _T_55)
when _T_58 :
node _b_count_0_T = add(b_count[0], UInt<1>(0h1))
node _b_count_0_T_1 = tail(_b_count_0_T, 1)
connect b_count[0], _b_count_0_T_1
node _T_59 = and(nodeIn.b.ready, nodeIn.b.valid)
node _T_60 = and(_T_59, _T_56)
when _T_60 :
node _b_count_1_T = add(b_count[1], UInt<1>(0h1))
node _b_count_1_T_1 = tail(_b_count_1_T, 1)
connect b_count[1], _b_count_1_T_1
connect nodeIn.b.bits.resp, q_b.bits.resp
connect nodeIn.b.bits.id, q_b.bits.id
node _nodeIn_b_valid_T = and(q_b.valid, b_allow)
connect nodeIn.b.valid, _nodeIn_b_valid_T
node _q_b_ready_T = and(nodeIn.b.ready, b_allow)
connect q_b.ready, _q_b_ready_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0) | module AXI4ToTL( // @[ToTL.scala:79:9]
input clock, // @[ToTL.scala:79:9]
input reset, // @[ToTL.scala:79:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[ToTL.scala:79:9]
wire auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[ToTL.scala:79:9]
wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[ToTL.scala:79:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[ToTL.scala:79:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[ToTL.scala:79:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[ToTL.scala:79:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[ToTL.scala:79:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[ToTL.scala:79:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[ToTL.scala:79:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[ToTL.scala:79:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[ToTL.scala:79:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[ToTL.scala:79:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[ToTL.scala:79:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[ToTL.scala:79:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[ToTL.scala:79:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[ToTL.scala:79:9]
wire auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[ToTL.scala:79:9]
wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[ToTL.scala:79:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[ToTL.scala:79:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[ToTL.scala:79:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[ToTL.scala:79:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[ToTL.scala:79:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[ToTL.scala:79:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[ToTL.scala:79:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[ToTL.scala:79:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[ToTL.scala:79:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[ToTL.scala:79:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[ToTL.scala:79:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[ToTL.scala:79:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[ToTL.scala:79:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[ToTL.scala:79:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[ToTL.scala:79:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[ToTL.scala:79:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[ToTL.scala:79:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[ToTL.scala:79:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[ToTL.scala:79:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_out_a_bits_param = 3'h0; // @[ToTL.scala:79:9]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] r_out_bits_param = 3'h0; // @[ToTL.scala:102:30]
wire [2:0] _r_count_WIRE_0 = 3'h0; // @[ToTL.scala:107:50]
wire [2:0] _r_count_WIRE_1 = 3'h0; // @[ToTL.scala:107:50]
wire [2:0] r_out_bits_a_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] w_out_bits_param = 3'h0; // @[ToTL.scala:138:30]
wire [2:0] _w_count_WIRE_0 = 3'h0; // @[ToTL.scala:143:50]
wire [2:0] _w_count_WIRE_1 = 3'h0; // @[ToTL.scala:143:50]
wire [2:0] w_out_bits_a_param = 3'h0; // @[Edges.scala:500:17]
wire [2:0] _nodeOut_a_bits_WIRE_param = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_39 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_40 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_41 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_WIRE_17 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _b_count_WIRE_0 = 3'h0; // @[ToTL.scala:208:50]
wire [2:0] _b_count_WIRE_1 = 3'h0; // @[ToTL.scala:208:50]
wire auto_out_a_bits_corrupt = 1'h0; // @[ToTL.scala:79:9]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_out_bits_corrupt = 1'h0; // @[ToTL.scala:102:30]
wire r_out_bits_a_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_privileged = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_secure = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_user_amba_prot_fetch = 1'h0; // @[Edges.scala:460:17]
wire r_out_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17]
wire w_out_bits_corrupt = 1'h0; // @[ToTL.scala:138:30]
wire _w_ok_T_50 = 1'h0; // @[Parameters.scala:684:29]
wire _w_ok_T_56 = 1'h0; // @[Parameters.scala:684:54]
wire _w_out_bits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _w_out_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire w_out_bits_a_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_privileged = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_secure = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_user_amba_prot_fetch = 1'h0; // @[Edges.scala:500:17]
wire w_out_bits_a_corrupt = 1'h0; // @[Edges.scala:500:17]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _nodeOut_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire [63:0] r_out_bits_data = 64'h0; // @[ToTL.scala:102:30]
wire [63:0] r_out_bits_a_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _nodeOut_a_bits_T_3 = 64'h0; // @[Mux.scala:30:73]
wire [2:0] w_out_bits_opcode = 3'h1; // @[ToTL.scala:138:30]
wire [2:0] w_out_bits_a_opcode = 3'h1; // @[Edges.scala:500:17]
wire _r_ok_T = 1'h1; // @[Parameters.scala:92:28]
wire _r_ok_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _r_out_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _r_out_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _w_ok_T = 1'h1; // @[Parameters.scala:92:28]
wire _w_ok_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _w_ok_T_57 = 1'h1; // @[Parameters.scala:92:28]
wire _w_out_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _w_out_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _w_out_bits_legal_T_51 = 1'h1; // @[Parameters.scala:92:28]
wire [2:0] r_out_bits_opcode = 3'h4; // @[ToTL.scala:102:30]
wire [2:0] r_out_bits_a_opcode = 3'h4; // @[Edges.scala:460:17]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[ToTL.scala:79:9]
wire nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[ToTL.scala:79:9]
wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[ToTL.scala:79:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[ToTL.scala:79:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[ToTL.scala:79:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[ToTL.scala:79:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[ToTL.scala:79:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[ToTL.scala:79:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[ToTL.scala:79:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[ToTL.scala:79:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[ToTL.scala:79:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[ToTL.scala:79:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[ToTL.scala:79:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[ToTL.scala:79:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[ToTL.scala:79:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[ToTL.scala:79:9]
wire nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[ToTL.scala:79:9]
wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[ToTL.scala:79:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[ToTL.scala:79:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[ToTL.scala:79:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[ToTL.scala:79:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[ToTL.scala:79:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[ToTL.scala:79:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[ToTL.scala:79:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[ToTL.scala:79:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[ToTL.scala:79:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[ToTL.scala:79:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[ToTL.scala:79:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[ToTL.scala:79:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[ToTL.scala:79:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[ToTL.scala:79:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[ToTL.scala:79:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[ToTL.scala:79:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[ToTL.scala:79:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[ToTL.scala:79:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[ToTL.scala:79:9]
wire auto_in_aw_ready_0; // @[ToTL.scala:79:9]
wire auto_in_w_ready_0; // @[ToTL.scala:79:9]
wire auto_in_b_bits_id_0; // @[ToTL.scala:79:9]
wire [1:0] auto_in_b_bits_resp_0; // @[ToTL.scala:79:9]
wire auto_in_b_valid_0; // @[ToTL.scala:79:9]
wire auto_in_ar_ready_0; // @[ToTL.scala:79:9]
wire auto_in_r_bits_id_0; // @[ToTL.scala:79:9]
wire [63:0] auto_in_r_bits_data_0; // @[ToTL.scala:79:9]
wire [1:0] auto_in_r_bits_resp_0; // @[ToTL.scala:79:9]
wire auto_in_r_bits_last_0; // @[ToTL.scala:79:9]
wire auto_in_r_valid_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_bufferable_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_modifiable_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_readalloc_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_writealloc_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_privileged_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_secure_0; // @[ToTL.scala:79:9]
wire auto_out_a_bits_user_amba_prot_fetch_0; // @[ToTL.scala:79:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[ToTL.scala:79:9]
wire [3:0] auto_out_a_bits_size_0; // @[ToTL.scala:79:9]
wire [3:0] auto_out_a_bits_source_0; // @[ToTL.scala:79:9]
wire [31:0] auto_out_a_bits_address_0; // @[ToTL.scala:79:9]
wire [7:0] auto_out_a_bits_mask_0; // @[ToTL.scala:79:9]
wire [63:0] auto_out_a_bits_data_0; // @[ToTL.scala:79:9]
wire auto_out_a_valid_0; // @[ToTL.scala:79:9]
wire auto_out_d_ready_0; // @[ToTL.scala:79:9]
wire _nodeIn_aw_ready_T_1; // @[ToTL.scala:152:48]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[ToTL.scala:79:9]
wire w_sel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49]
wire [31:0] _w_ok_T_14 = nodeIn_aw_bits_addr; // @[Parameters.scala:137:31]
wire _nodeIn_w_ready_T; // @[ToTL.scala:153:34]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[ToTL.scala:79:9]
wire [63:0] w_out_bits_a_data = nodeIn_w_bits_data; // @[Edges.scala:500:17]
wire [7:0] w_out_bits_a_mask = nodeIn_w_bits_strb; // @[Edges.scala:500:17]
wire _nodeIn_b_valid_T; // @[ToTL.scala:217:31]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[ToTL.scala:79:9]
wire q_b_bits_id; // @[Decoupled.scala:401:19]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[ToTL.scala:79:9]
wire [1:0] q_b_bits_resp; // @[Decoupled.scala:401:19]
wire b_sel_shiftAmount = nodeIn_b_bits_id; // @[OneHot.scala:64:49]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[ToTL.scala:79:9]
wire r_out_ready; // @[ToTL.scala:102:30]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[ToTL.scala:79:9]
wire r_out_valid = nodeIn_ar_valid; // @[ToTL.scala:102:30]
wire r_sel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49]
wire [31:0] _r_ok_T_14 = nodeIn_ar_bits_addr; // @[Parameters.scala:137:31]
wire nodeIn_r_irr_ready = nodeIn_r_ready; // @[Decoupled.scala:401:19]
wire nodeIn_r_irr_valid; // @[Decoupled.scala:401:19]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[ToTL.scala:79:9]
wire nodeIn_r_irr_bits_id; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[ToTL.scala:79:9]
wire [63:0] nodeIn_r_irr_bits_data; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[ToTL.scala:79:9]
wire [1:0] nodeIn_r_irr_bits_resp; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[ToTL.scala:79:9]
wire nodeIn_r_irr_bits_last; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[ToTL.scala:79:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[ToTL.scala:79:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ToTL.scala:79:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[ToTL.scala:79:9]
wire [3:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[ToTL.scala:79:9]
wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_bufferable; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_bufferable_0 = nodeOut_a_bits_user_amba_prot_bufferable; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_modifiable; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_modifiable_0 = nodeOut_a_bits_user_amba_prot_modifiable; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_readalloc; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_readalloc_0 = nodeOut_a_bits_user_amba_prot_readalloc; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_writealloc; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_writealloc_0 = nodeOut_a_bits_user_amba_prot_writealloc; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_privileged; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_privileged_0 = nodeOut_a_bits_user_amba_prot_privileged; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_secure; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_secure_0 = nodeOut_a_bits_user_amba_prot_secure; // @[ToTL.scala:79:9]
wire _nodeOut_a_bits_WIRE_user_amba_prot_fetch; // @[Mux.scala:30:73]
assign auto_out_a_bits_user_amba_prot_fetch_0 = nodeOut_a_bits_user_amba_prot_fetch; // @[ToTL.scala:79:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ToTL.scala:79:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[ToTL.scala:79:9]
wire _nodeOut_d_ready_T; // @[ToTL.scala:186:25]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[ToTL.scala:79:9]
wire [63:0] ok_r_bits_data = nodeOut_d_bits_data; // @[ToTL.scala:180:30]
wire _r_out_ready_T; // @[Arbiter.scala:94:31]
assign nodeIn_ar_ready = r_out_ready; // @[ToTL.scala:102:30]
wire [3:0] r_out_bits_a_size; // @[Edges.scala:460:17]
wire [3:0] r_out_bits_a_source; // @[Edges.scala:460:17]
wire [31:0] r_out_bits_a_address; // @[Edges.scala:460:17]
wire _r_out_bits_user_amba_prot_bufferable_T; // @[ToTL.scala:127:46]
wire _r_out_bits_user_amba_prot_modifiable_T; // @[ToTL.scala:128:46]
wire _r_out_bits_user_amba_prot_readalloc_T; // @[ToTL.scala:129:46]
wire _r_out_bits_user_amba_prot_writealloc_T; // @[ToTL.scala:130:46]
wire _r_out_bits_user_amba_prot_privileged_T; // @[ToTL.scala:124:45]
wire _r_out_bits_user_amba_prot_secure_T_1; // @[ToTL.scala:125:29]
wire _r_out_bits_user_amba_prot_fetch_T; // @[ToTL.scala:126:45]
wire [7:0] r_out_bits_a_mask; // @[Edges.scala:460:17]
wire r_out_bits_user_amba_prot_bufferable; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_modifiable; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_readalloc; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_writealloc; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_privileged; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_secure; // @[ToTL.scala:102:30]
wire r_out_bits_user_amba_prot_fetch; // @[ToTL.scala:102:30]
wire [3:0] r_out_bits_size; // @[ToTL.scala:102:30]
wire [3:0] r_out_bits_source; // @[ToTL.scala:102:30]
wire [31:0] r_out_bits_address; // @[ToTL.scala:102:30]
wire [7:0] r_out_bits_mask; // @[ToTL.scala:102:30]
wire [15:0] _r_size1_T = {nodeIn_ar_bits_len, 8'hFF}; // @[Bundles.scala:33:9]
wire [22:0] _r_size1_T_1 = {7'h0, _r_size1_T} << nodeIn_ar_bits_size; // @[Bundles.scala:33:{9,21}]
wire [14:0] r_size1 = _r_size1_T_1[22:8]; // @[Bundles.scala:33:{21,30}]
wire [15:0] _r_size_T = {r_size1, 1'h0}; // @[package.scala:241:35]
wire [15:0] _r_size_T_1 = {_r_size_T[15:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [15:0] _r_size_T_2 = {1'h0, r_size1}; // @[package.scala:241:53]
wire [15:0] _r_size_T_3 = ~_r_size_T_2; // @[package.scala:241:{49,53}]
wire [15:0] _r_size_T_4 = _r_size_T_1 & _r_size_T_3; // @[package.scala:241:{40,47,49}]
wire [7:0] r_size_hi = _r_size_T_4[15:8]; // @[OneHot.scala:30:18]
wire [7:0] r_size_lo = _r_size_T_4[7:0]; // @[OneHot.scala:31:18]
wire _r_size_T_5 = |r_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _r_size_T_6 = r_size_hi | r_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] r_size_hi_1 = _r_size_T_6[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] r_size_lo_1 = _r_size_T_6[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_size_T_7 = |r_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_size_T_8 = r_size_hi_1 | r_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_size_hi_2 = _r_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_size_lo_2 = _r_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_size_T_9 = |r_size_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_size_T_10 = r_size_hi_2 | r_size_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_size_T_11 = _r_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_size_T_12 = {_r_size_T_9, _r_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_size_T_13 = {_r_size_T_7, _r_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [3:0] r_size = {_r_size_T_5, _r_size_T_13}; // @[OneHot.scala:32:{10,14}]
assign r_out_bits_a_size = r_size; // @[OneHot.scala:32:10]
wire [3:0] _r_out_bits_a_mask_sizeOH_T = r_size; // @[OneHot.scala:32:10]
wire _GEN = r_size < 4'hD; // @[OneHot.scala:32:10]
wire _r_ok_T_1; // @[Parameters.scala:92:38]
assign _r_ok_T_1 = _GEN; // @[Parameters.scala:92:38]
wire _r_out_bits_legal_T_1; // @[Parameters.scala:92:38]
assign _r_out_bits_legal_T_1 = _GEN; // @[Parameters.scala:92:38]
wire _r_ok_T_2 = _r_ok_T_1; // @[Parameters.scala:92:{33,38}]
wire _r_ok_T_3 = _r_ok_T_2; // @[Parameters.scala:684:29]
wire [31:0] _r_ok_T_4 = {nodeIn_ar_bits_addr[31:14], nodeIn_ar_bits_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_5 = {1'h0, _r_ok_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_6 = _r_ok_T_5 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_7 = _r_ok_T_6; // @[Parameters.scala:137:46]
wire _r_ok_T_8 = _r_ok_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _r_ok_T_9 = _r_ok_T_3 & _r_ok_T_8; // @[Parameters.scala:684:{29,54}]
wire _r_ok_T_62 = _r_ok_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_0 = r_size < 4'h7; // @[OneHot.scala:32:10]
wire _r_ok_T_11; // @[Parameters.scala:92:38]
assign _r_ok_T_11 = _GEN_0; // @[Parameters.scala:92:38]
wire _r_out_bits_legal_T_11; // @[Parameters.scala:92:38]
assign _r_out_bits_legal_T_11 = _GEN_0; // @[Parameters.scala:92:38]
wire _r_ok_T_12 = _r_ok_T_11; // @[Parameters.scala:92:{33,38}]
wire _r_ok_T_13 = _r_ok_T_12; // @[Parameters.scala:684:29]
wire [32:0] _r_ok_T_15 = {1'h0, _r_ok_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_16 = _r_ok_T_15 & 33'h1FFFFE000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_17 = _r_ok_T_16; // @[Parameters.scala:137:46]
wire _r_ok_T_18 = _r_ok_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_19 = {nodeIn_ar_bits_addr[31:17], nodeIn_ar_bits_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_20 = {1'h0, _r_ok_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_21 = _r_ok_T_20 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_22 = _r_ok_T_21; // @[Parameters.scala:137:46]
wire _r_ok_T_23 = _r_ok_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_24 = {nodeIn_ar_bits_addr[31:21], nodeIn_ar_bits_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_25 = {1'h0, _r_ok_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_26 = _r_ok_T_25 & 33'h1FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_27 = _r_ok_T_26; // @[Parameters.scala:137:46]
wire _r_ok_T_28 = _r_ok_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_29 = {nodeIn_ar_bits_addr[31:26], nodeIn_ar_bits_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_30 = {1'h0, _r_ok_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_31 = _r_ok_T_30 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_32 = _r_ok_T_31; // @[Parameters.scala:137:46]
wire _r_ok_T_33 = _r_ok_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_34 = {nodeIn_ar_bits_addr[31:28], nodeIn_ar_bits_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_35 = {1'h0, _r_ok_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_36 = _r_ok_T_35 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_37 = _r_ok_T_36; // @[Parameters.scala:137:46]
wire _r_ok_T_38 = _r_ok_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_39 = {nodeIn_ar_bits_addr[31:29], nodeIn_ar_bits_addr[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_40 = {1'h0, _r_ok_T_39}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_41 = _r_ok_T_40 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_42 = _r_ok_T_41; // @[Parameters.scala:137:46]
wire _r_ok_T_43 = _r_ok_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_44 = {nodeIn_ar_bits_addr[31], nodeIn_ar_bits_addr[30:0] ^ 31'h60000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_45 = {1'h0, _r_ok_T_44}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_46 = _r_ok_T_45 & 33'h1E0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_47 = _r_ok_T_46; // @[Parameters.scala:137:46]
wire _r_ok_T_48 = _r_ok_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_ok_T_49 = nodeIn_ar_bits_addr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _r_ok_T_50 = {1'h0, _r_ok_T_49}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_ok_T_51 = _r_ok_T_50 & 33'h1FFFFC000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_ok_T_52 = _r_ok_T_51; // @[Parameters.scala:137:46]
wire _r_ok_T_53 = _r_ok_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _r_ok_T_54 = _r_ok_T_18 | _r_ok_T_23; // @[Parameters.scala:685:42]
wire _r_ok_T_55 = _r_ok_T_54 | _r_ok_T_28; // @[Parameters.scala:685:42]
wire _r_ok_T_56 = _r_ok_T_55 | _r_ok_T_33; // @[Parameters.scala:685:42]
wire _r_ok_T_57 = _r_ok_T_56 | _r_ok_T_38; // @[Parameters.scala:685:42]
wire _r_ok_T_58 = _r_ok_T_57 | _r_ok_T_43; // @[Parameters.scala:685:42]
wire _r_ok_T_59 = _r_ok_T_58 | _r_ok_T_48; // @[Parameters.scala:685:42]
wire _r_ok_T_60 = _r_ok_T_59 | _r_ok_T_53; // @[Parameters.scala:685:42]
wire _r_ok_T_61 = _r_ok_T_13 & _r_ok_T_60; // @[Parameters.scala:684:{29,54}, :685:42]
wire r_ok = _r_ok_T_62 | _r_ok_T_61; // @[Parameters.scala:684:54, :686:26]
wire [2:0] _r_addr_T = nodeIn_ar_bits_addr[2:0]; // @[ToTL.scala:106:72]
wire [13:0] _r_addr_T_1 = {11'h600, _r_addr_T}; // @[ToTL.scala:106:{55,72}]
wire [31:0] r_addr = r_ok ? nodeIn_ar_bits_addr : {18'h0, _r_addr_T_1}; // @[Parameters.scala:686:26]
wire [31:0] _r_out_bits_legal_T_14 = r_addr; // @[Parameters.scala:137:31]
assign r_out_bits_a_address = r_addr; // @[Edges.scala:460:17]
reg [2:0] r_count_0; // @[ToTL.scala:107:28]
reg [2:0] r_count_1; // @[ToTL.scala:107:28]
wire [1:0] _r_id_T = nodeIn_ar_bits_id ? r_count_1[1:0] : r_count_0[1:0]; // @[ToTL.scala:107:28, :111:50]
wire [2:0] r_id_hi = {nodeIn_ar_bits_id, _r_id_T}; // @[ToTL.scala:111:{12,50}]
wire [3:0] r_id = {r_id_hi, 1'h0}; // @[ToTL.scala:111:12]
assign r_out_bits_a_source = r_id; // @[Edges.scala:460:17]
wire _r_out_bits_legal_T_2 = _r_out_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _r_out_bits_legal_T_3 = _r_out_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [31:0] _r_out_bits_legal_T_4 = {r_addr[31:14], r_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_5 = {1'h0, _r_out_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_6 = _r_out_bits_legal_T_5 & 33'hCA113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_7 = _r_out_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_8 = _r_out_bits_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _r_out_bits_legal_T_9 = _r_out_bits_legal_T_3 & _r_out_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _r_out_bits_legal_T_56 = _r_out_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _r_out_bits_legal_T_12 = _r_out_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _r_out_bits_legal_T_13 = _r_out_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [32:0] _r_out_bits_legal_T_15 = {1'h0, _r_out_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_16 = _r_out_bits_legal_T_15 & 33'hCA112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_17 = _r_out_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_18 = _r_out_bits_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_19 = {r_addr[31:17], r_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_20 = {1'h0, _r_out_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_21 = _r_out_bits_legal_T_20 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_22 = _r_out_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_23 = _r_out_bits_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_24 = {r_addr[31:21], r_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_25 = {1'h0, _r_out_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_26 = _r_out_bits_legal_T_25 & 33'hCA103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_27 = _r_out_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_28 = _r_out_bits_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_29 = {r_addr[31:26], r_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_30 = {1'h0, _r_out_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_31 = _r_out_bits_legal_T_30 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_32 = _r_out_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_33 = _r_out_bits_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_34 = {r_addr[31:28], r_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_35 = {1'h0, _r_out_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_36 = _r_out_bits_legal_T_35 & 33'hC8000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_37 = _r_out_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_38 = _r_out_bits_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_39 = {r_addr[31], r_addr[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_40 = {1'h0, _r_out_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_41 = _r_out_bits_legal_T_40 & 33'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_42 = _r_out_bits_legal_T_41; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_43 = _r_out_bits_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _r_out_bits_legal_T_44 = r_addr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _r_out_bits_legal_T_45 = {1'h0, _r_out_bits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _r_out_bits_legal_T_46 = _r_out_bits_legal_T_45 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _r_out_bits_legal_T_47 = _r_out_bits_legal_T_46; // @[Parameters.scala:137:46]
wire _r_out_bits_legal_T_48 = _r_out_bits_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _r_out_bits_legal_T_49 = _r_out_bits_legal_T_18 | _r_out_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_50 = _r_out_bits_legal_T_49 | _r_out_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_51 = _r_out_bits_legal_T_50 | _r_out_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_52 = _r_out_bits_legal_T_51 | _r_out_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_53 = _r_out_bits_legal_T_52 | _r_out_bits_legal_T_43; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_54 = _r_out_bits_legal_T_53 | _r_out_bits_legal_T_48; // @[Parameters.scala:685:42]
wire _r_out_bits_legal_T_55 = _r_out_bits_legal_T_13 & _r_out_bits_legal_T_54; // @[Parameters.scala:684:{29,54}, :685:42]
wire r_out_bits_legal = _r_out_bits_legal_T_56 | _r_out_bits_legal_T_55; // @[Parameters.scala:684:54, :686:26]
assign r_out_bits_size = r_out_bits_a_size; // @[Edges.scala:460:17]
assign r_out_bits_source = r_out_bits_a_source; // @[Edges.scala:460:17]
assign r_out_bits_address = r_out_bits_a_address; // @[Edges.scala:460:17]
wire [7:0] _r_out_bits_a_mask_T; // @[Misc.scala:222:10]
assign r_out_bits_mask = r_out_bits_a_mask; // @[Edges.scala:460:17]
wire [1:0] r_out_bits_a_mask_sizeOH_shiftAmount = _r_out_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _r_out_bits_a_mask_sizeOH_T_1 = 4'h1 << r_out_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _r_out_bits_a_mask_sizeOH_T_2 = _r_out_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] r_out_bits_a_mask_sizeOH = {_r_out_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire r_out_bits_a_mask_sub_sub_sub_0_1 = r_size > 4'h2; // @[OneHot.scala:32:10]
wire r_out_bits_a_mask_sub_sub_size = r_out_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire r_out_bits_a_mask_sub_sub_bit = r_addr[2]; // @[Misc.scala:210:26]
wire r_out_bits_a_mask_sub_sub_1_2 = r_out_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire r_out_bits_a_mask_sub_sub_nbit = ~r_out_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire r_out_bits_a_mask_sub_sub_0_2 = r_out_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_sub_sub_acc_T = r_out_bits_a_mask_sub_sub_size & r_out_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_sub_0_1 = r_out_bits_a_mask_sub_sub_sub_0_1 | _r_out_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _r_out_bits_a_mask_sub_sub_acc_T_1 = r_out_bits_a_mask_sub_sub_size & r_out_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_sub_1_1 = r_out_bits_a_mask_sub_sub_sub_0_1 | _r_out_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire r_out_bits_a_mask_sub_size = r_out_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire r_out_bits_a_mask_sub_bit = r_addr[1]; // @[Misc.scala:210:26]
wire r_out_bits_a_mask_sub_nbit = ~r_out_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire r_out_bits_a_mask_sub_0_2 = r_out_bits_a_mask_sub_sub_0_2 & r_out_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_sub_acc_T = r_out_bits_a_mask_sub_size & r_out_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_0_1 = r_out_bits_a_mask_sub_sub_0_1 | _r_out_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_sub_1_2 = r_out_bits_a_mask_sub_sub_0_2 & r_out_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_sub_acc_T_1 = r_out_bits_a_mask_sub_size & r_out_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_1_1 = r_out_bits_a_mask_sub_sub_0_1 | _r_out_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_sub_2_2 = r_out_bits_a_mask_sub_sub_1_2 & r_out_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_sub_acc_T_2 = r_out_bits_a_mask_sub_size & r_out_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_2_1 = r_out_bits_a_mask_sub_sub_1_1 | _r_out_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_sub_3_2 = r_out_bits_a_mask_sub_sub_1_2 & r_out_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_sub_acc_T_3 = r_out_bits_a_mask_sub_size & r_out_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_sub_3_1 = r_out_bits_a_mask_sub_sub_1_1 | _r_out_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_size = r_out_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire r_out_bits_a_mask_bit = r_addr[0]; // @[Misc.scala:210:26]
wire r_out_bits_a_mask_nbit = ~r_out_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire r_out_bits_a_mask_eq = r_out_bits_a_mask_sub_0_2 & r_out_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_acc_T = r_out_bits_a_mask_size & r_out_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc = r_out_bits_a_mask_sub_0_1 | _r_out_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_1 = r_out_bits_a_mask_sub_0_2 & r_out_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_acc_T_1 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_1 = r_out_bits_a_mask_sub_0_1 | _r_out_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_2 = r_out_bits_a_mask_sub_1_2 & r_out_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_acc_T_2 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_2 = r_out_bits_a_mask_sub_1_1 | _r_out_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_3 = r_out_bits_a_mask_sub_1_2 & r_out_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_acc_T_3 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_3 = r_out_bits_a_mask_sub_1_1 | _r_out_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_4 = r_out_bits_a_mask_sub_2_2 & r_out_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_acc_T_4 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_4 = r_out_bits_a_mask_sub_2_1 | _r_out_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_5 = r_out_bits_a_mask_sub_2_2 & r_out_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_acc_T_5 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_5 = r_out_bits_a_mask_sub_2_1 | _r_out_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_6 = r_out_bits_a_mask_sub_3_2 & r_out_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _r_out_bits_a_mask_acc_T_6 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_6 = r_out_bits_a_mask_sub_3_1 | _r_out_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire r_out_bits_a_mask_eq_7 = r_out_bits_a_mask_sub_3_2 & r_out_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _r_out_bits_a_mask_acc_T_7 = r_out_bits_a_mask_size & r_out_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire r_out_bits_a_mask_acc_7 = r_out_bits_a_mask_sub_3_1 | _r_out_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] r_out_bits_a_mask_lo_lo = {r_out_bits_a_mask_acc_1, r_out_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] r_out_bits_a_mask_lo_hi = {r_out_bits_a_mask_acc_3, r_out_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] r_out_bits_a_mask_lo = {r_out_bits_a_mask_lo_hi, r_out_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] r_out_bits_a_mask_hi_lo = {r_out_bits_a_mask_acc_5, r_out_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] r_out_bits_a_mask_hi_hi = {r_out_bits_a_mask_acc_7, r_out_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] r_out_bits_a_mask_hi = {r_out_bits_a_mask_hi_hi, r_out_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _r_out_bits_a_mask_T = {r_out_bits_a_mask_hi, r_out_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign r_out_bits_a_mask = _r_out_bits_a_mask_T; // @[Misc.scala:222:10]
assign _r_out_bits_user_amba_prot_privileged_T = nodeIn_ar_bits_prot[0]; // @[ToTL.scala:124:45]
assign r_out_bits_user_amba_prot_privileged = _r_out_bits_user_amba_prot_privileged_T; // @[ToTL.scala:102:30, :124:45]
wire _r_out_bits_user_amba_prot_secure_T = nodeIn_ar_bits_prot[1]; // @[ToTL.scala:125:45]
assign _r_out_bits_user_amba_prot_secure_T_1 = ~_r_out_bits_user_amba_prot_secure_T; // @[ToTL.scala:125:{29,45}]
assign r_out_bits_user_amba_prot_secure = _r_out_bits_user_amba_prot_secure_T_1; // @[ToTL.scala:102:30, :125:29]
assign _r_out_bits_user_amba_prot_fetch_T = nodeIn_ar_bits_prot[2]; // @[ToTL.scala:126:45]
assign r_out_bits_user_amba_prot_fetch = _r_out_bits_user_amba_prot_fetch_T; // @[ToTL.scala:102:30, :126:45]
assign _r_out_bits_user_amba_prot_bufferable_T = nodeIn_ar_bits_cache[0]; // @[ToTL.scala:127:46]
assign r_out_bits_user_amba_prot_bufferable = _r_out_bits_user_amba_prot_bufferable_T; // @[ToTL.scala:102:30, :127:46]
assign _r_out_bits_user_amba_prot_modifiable_T = nodeIn_ar_bits_cache[1]; // @[ToTL.scala:128:46]
assign r_out_bits_user_amba_prot_modifiable = _r_out_bits_user_amba_prot_modifiable_T; // @[ToTL.scala:102:30, :128:46]
assign _r_out_bits_user_amba_prot_readalloc_T = nodeIn_ar_bits_cache[2]; // @[ToTL.scala:129:46]
assign r_out_bits_user_amba_prot_readalloc = _r_out_bits_user_amba_prot_readalloc_T; // @[ToTL.scala:102:30, :129:46]
assign _r_out_bits_user_amba_prot_writealloc_T = nodeIn_ar_bits_cache[3]; // @[ToTL.scala:130:46]
assign r_out_bits_user_amba_prot_writealloc = _r_out_bits_user_amba_prot_writealloc_T; // @[ToTL.scala:102:30, :130:46]
wire [1:0] _r_sel_T = 2'h1 << r_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] r_sel = _r_sel_T; // @[OneHot.scala:65:{12,27}]
wire [3:0] _r_count_0_T = {1'h0, r_count_0} + 4'h1; // @[ToTL.scala:107:28, :135:41]
wire [2:0] _r_count_0_T_1 = _r_count_0_T[2:0]; // @[ToTL.scala:135:41]
wire [3:0] _r_count_1_T = {1'h0, r_count_1} + 4'h1; // @[ToTL.scala:107:28, :135:41]
wire [2:0] _r_count_1_T_1 = _r_count_1_T[2:0]; // @[ToTL.scala:135:41]
wire _w_out_ready_T; // @[Arbiter.scala:94:31]
wire _w_out_valid_T; // @[ToTL.scala:154:34]
wire [3:0] w_out_bits_a_size; // @[Edges.scala:500:17]
wire [3:0] w_out_bits_a_source; // @[Edges.scala:500:17]
wire [31:0] w_out_bits_a_address; // @[Edges.scala:500:17]
wire _w_out_bits_user_amba_prot_bufferable_T; // @[ToTL.scala:166:46]
wire _w_out_bits_user_amba_prot_modifiable_T; // @[ToTL.scala:167:46]
wire _w_out_bits_user_amba_prot_readalloc_T; // @[ToTL.scala:168:46]
wire _w_out_bits_user_amba_prot_writealloc_T; // @[ToTL.scala:169:46]
wire _w_out_bits_user_amba_prot_privileged_T; // @[ToTL.scala:163:45]
wire _w_out_bits_user_amba_prot_secure_T_1; // @[ToTL.scala:164:29]
wire _w_out_bits_user_amba_prot_fetch_T; // @[ToTL.scala:165:45]
wire w_out_bits_user_amba_prot_bufferable; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_modifiable; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_readalloc; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_writealloc; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_privileged; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_secure; // @[ToTL.scala:138:30]
wire w_out_bits_user_amba_prot_fetch; // @[ToTL.scala:138:30]
wire [3:0] w_out_bits_size; // @[ToTL.scala:138:30]
wire [3:0] w_out_bits_source; // @[ToTL.scala:138:30]
wire [31:0] w_out_bits_address; // @[ToTL.scala:138:30]
wire [7:0] w_out_bits_mask; // @[ToTL.scala:138:30]
wire [63:0] w_out_bits_data; // @[ToTL.scala:138:30]
wire w_out_ready; // @[ToTL.scala:138:30]
wire w_out_valid; // @[ToTL.scala:138:30]
wire [15:0] _w_size1_T = {nodeIn_aw_bits_len, 8'hFF}; // @[Bundles.scala:33:9]
wire [22:0] _w_size1_T_1 = {7'h0, _w_size1_T} << nodeIn_aw_bits_size; // @[Bundles.scala:33:{9,21}]
wire [14:0] w_size1 = _w_size1_T_1[22:8]; // @[Bundles.scala:33:{21,30}]
wire [15:0] _w_size_T = {w_size1, 1'h0}; // @[package.scala:241:35]
wire [15:0] _w_size_T_1 = {_w_size_T[15:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [15:0] _w_size_T_2 = {1'h0, w_size1}; // @[package.scala:241:53]
wire [15:0] _w_size_T_3 = ~_w_size_T_2; // @[package.scala:241:{49,53}]
wire [15:0] _w_size_T_4 = _w_size_T_1 & _w_size_T_3; // @[package.scala:241:{40,47,49}]
wire [7:0] w_size_hi = _w_size_T_4[15:8]; // @[OneHot.scala:30:18]
wire [7:0] w_size_lo = _w_size_T_4[7:0]; // @[OneHot.scala:31:18]
wire _w_size_T_5 = |w_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _w_size_T_6 = w_size_hi | w_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] w_size_hi_1 = _w_size_T_6[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] w_size_lo_1 = _w_size_T_6[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _w_size_T_7 = |w_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _w_size_T_8 = w_size_hi_1 | w_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] w_size_hi_2 = _w_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] w_size_lo_2 = _w_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _w_size_T_9 = |w_size_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _w_size_T_10 = w_size_hi_2 | w_size_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _w_size_T_11 = _w_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _w_size_T_12 = {_w_size_T_9, _w_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _w_size_T_13 = {_w_size_T_7, _w_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [3:0] w_size = {_w_size_T_5, _w_size_T_13}; // @[OneHot.scala:32:{10,14}]
assign w_out_bits_a_size = w_size; // @[OneHot.scala:32:10]
wire _GEN_1 = w_size < 4'hD; // @[OneHot.scala:32:10]
wire _w_ok_T_1; // @[Parameters.scala:92:38]
assign _w_ok_T_1 = _GEN_1; // @[Parameters.scala:92:38]
wire _w_out_bits_legal_T_1; // @[Parameters.scala:92:38]
assign _w_out_bits_legal_T_1 = _GEN_1; // @[Parameters.scala:92:38]
wire _w_ok_T_2 = _w_ok_T_1; // @[Parameters.scala:92:{33,38}]
wire _w_ok_T_3 = _w_ok_T_2; // @[Parameters.scala:684:29]
wire [31:0] _w_ok_T_4 = {nodeIn_aw_bits_addr[31:14], nodeIn_aw_bits_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_5 = {1'h0, _w_ok_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_6 = _w_ok_T_5 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_7 = _w_ok_T_6; // @[Parameters.scala:137:46]
wire _w_ok_T_8 = _w_ok_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_ok_T_9 = _w_ok_T_3 & _w_ok_T_8; // @[Parameters.scala:684:{29,54}]
wire _w_ok_T_67 = _w_ok_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_2 = w_size < 4'h7; // @[OneHot.scala:32:10]
wire _w_ok_T_11; // @[Parameters.scala:92:38]
assign _w_ok_T_11 = _GEN_2; // @[Parameters.scala:92:38]
wire _w_out_bits_legal_T_11; // @[Parameters.scala:92:38]
assign _w_out_bits_legal_T_11 = _GEN_2; // @[Parameters.scala:92:38]
wire _w_ok_T_12 = _w_ok_T_11; // @[Parameters.scala:92:{33,38}]
wire _w_ok_T_13 = _w_ok_T_12; // @[Parameters.scala:684:29]
wire [32:0] _w_ok_T_15 = {1'h0, _w_ok_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_16 = _w_ok_T_15 & 33'h1FFFFE000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_17 = _w_ok_T_16; // @[Parameters.scala:137:46]
wire _w_ok_T_18 = _w_ok_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_ok_T_19 = {nodeIn_aw_bits_addr[31:21], nodeIn_aw_bits_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_20 = {1'h0, _w_ok_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_21 = _w_ok_T_20 & 33'h1FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_22 = _w_ok_T_21; // @[Parameters.scala:137:46]
wire _w_ok_T_23 = _w_ok_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_ok_T_24 = {nodeIn_aw_bits_addr[31:26], nodeIn_aw_bits_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_25 = {1'h0, _w_ok_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_26 = _w_ok_T_25 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_27 = _w_ok_T_26; // @[Parameters.scala:137:46]
wire _w_ok_T_28 = _w_ok_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_ok_T_29 = {nodeIn_aw_bits_addr[31:28], nodeIn_aw_bits_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_30 = {1'h0, _w_ok_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_31 = _w_ok_T_30 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_32 = _w_ok_T_31; // @[Parameters.scala:137:46]
wire _w_ok_T_33 = _w_ok_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_ok_T_34 = {nodeIn_aw_bits_addr[31:29], nodeIn_aw_bits_addr[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_35 = {1'h0, _w_ok_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_36 = _w_ok_T_35 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_37 = _w_ok_T_36; // @[Parameters.scala:137:46]
wire _w_ok_T_38 = _w_ok_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_ok_T_39 = nodeIn_aw_bits_addr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_40 = {1'h0, _w_ok_T_39}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_41 = _w_ok_T_40 & 33'h1FFFFC000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_42 = _w_ok_T_41; // @[Parameters.scala:137:46]
wire _w_ok_T_43 = _w_ok_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_ok_T_44 = _w_ok_T_18 | _w_ok_T_23; // @[Parameters.scala:685:42]
wire _w_ok_T_45 = _w_ok_T_44 | _w_ok_T_28; // @[Parameters.scala:685:42]
wire _w_ok_T_46 = _w_ok_T_45 | _w_ok_T_33; // @[Parameters.scala:685:42]
wire _w_ok_T_47 = _w_ok_T_46 | _w_ok_T_38; // @[Parameters.scala:685:42]
wire _w_ok_T_48 = _w_ok_T_47 | _w_ok_T_43; // @[Parameters.scala:685:42]
wire _w_ok_T_49 = _w_ok_T_13 & _w_ok_T_48; // @[Parameters.scala:684:{29,54}, :685:42]
wire [31:0] _w_ok_T_51 = {nodeIn_aw_bits_addr[31:17], nodeIn_aw_bits_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_52 = {1'h0, _w_ok_T_51}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_53 = _w_ok_T_52 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_54 = _w_ok_T_53; // @[Parameters.scala:137:46]
wire _w_ok_T_55 = _w_ok_T_54 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _GEN_3 = w_size < 4'h9; // @[OneHot.scala:32:10]
wire _w_ok_T_58; // @[Parameters.scala:92:38]
assign _w_ok_T_58 = _GEN_3; // @[Parameters.scala:92:38]
wire _w_out_bits_legal_T_52; // @[Parameters.scala:92:38]
assign _w_out_bits_legal_T_52 = _GEN_3; // @[Parameters.scala:92:38]
wire _w_ok_T_59 = _w_ok_T_58; // @[Parameters.scala:92:{33,38}]
wire _w_ok_T_60 = _w_ok_T_59; // @[Parameters.scala:684:29]
wire [31:0] _w_ok_T_61 = {nodeIn_aw_bits_addr[31], nodeIn_aw_bits_addr[30:0] ^ 31'h60000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_ok_T_62 = {1'h0, _w_ok_T_61}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_ok_T_63 = _w_ok_T_62 & 33'h1E0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_ok_T_64 = _w_ok_T_63; // @[Parameters.scala:137:46]
wire _w_ok_T_65 = _w_ok_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_ok_T_66 = _w_ok_T_60 & _w_ok_T_65; // @[Parameters.scala:684:{29,54}]
wire _w_ok_T_68 = _w_ok_T_67 | _w_ok_T_49; // @[Parameters.scala:684:54, :686:26]
wire _w_ok_T_69 = _w_ok_T_68; // @[Parameters.scala:686:26]
wire w_ok = _w_ok_T_69 | _w_ok_T_66; // @[Parameters.scala:684:54, :686:26]
wire [2:0] _w_addr_T = nodeIn_aw_bits_addr[2:0]; // @[ToTL.scala:142:72]
wire [13:0] _w_addr_T_1 = {11'h600, _w_addr_T}; // @[ToTL.scala:142:{55,72}]
wire [31:0] w_addr = w_ok ? nodeIn_aw_bits_addr : {18'h0, _w_addr_T_1}; // @[Parameters.scala:686:26]
wire [31:0] _w_out_bits_legal_T_14 = w_addr; // @[Parameters.scala:137:31]
assign w_out_bits_a_address = w_addr; // @[Edges.scala:500:17]
reg [2:0] w_count_0; // @[ToTL.scala:143:28]
reg [2:0] w_count_1; // @[ToTL.scala:143:28]
wire [1:0] _w_id_T = nodeIn_aw_bits_id ? w_count_1[1:0] : w_count_0[1:0]; // @[ToTL.scala:143:28, :147:50]
wire [2:0] w_id_hi = {nodeIn_aw_bits_id, _w_id_T}; // @[ToTL.scala:147:{12,50}]
wire [3:0] w_id = {w_id_hi, 1'h1}; // @[ToTL.scala:147:12]
assign w_out_bits_a_source = w_id; // @[Edges.scala:500:17]
wire _nodeIn_aw_ready_T = w_out_ready & nodeIn_w_valid; // @[ToTL.scala:138:30, :152:34]
assign _nodeIn_aw_ready_T_1 = _nodeIn_aw_ready_T & nodeIn_w_bits_last; // @[ToTL.scala:152:{34,48}]
assign nodeIn_aw_ready = _nodeIn_aw_ready_T_1; // @[ToTL.scala:152:48]
assign _nodeIn_w_ready_T = w_out_ready & nodeIn_aw_valid; // @[ToTL.scala:138:30, :153:34]
assign nodeIn_w_ready = _nodeIn_w_ready_T; // @[ToTL.scala:153:34]
assign _w_out_valid_T = nodeIn_aw_valid & nodeIn_w_valid; // @[ToTL.scala:154:34]
assign w_out_valid = _w_out_valid_T; // @[ToTL.scala:138:30, :154:34]
wire _w_out_bits_legal_T_2 = _w_out_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _w_out_bits_legal_T_3 = _w_out_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [31:0] _w_out_bits_legal_T_4 = {w_addr[31:14], w_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_5 = {1'h0, _w_out_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_6 = _w_out_bits_legal_T_5 & 33'hCA113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_7 = _w_out_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_8 = _w_out_bits_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_out_bits_legal_T_9 = _w_out_bits_legal_T_3 & _w_out_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _w_out_bits_legal_T_61 = _w_out_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _w_out_bits_legal_T_12 = _w_out_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _w_out_bits_legal_T_13 = _w_out_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [32:0] _w_out_bits_legal_T_15 = {1'h0, _w_out_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_16 = _w_out_bits_legal_T_15 & 33'hCA112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_17 = _w_out_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_18 = _w_out_bits_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_out_bits_legal_T_19 = {w_addr[31:21], w_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_20 = {1'h0, _w_out_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_21 = _w_out_bits_legal_T_20 & 33'hCA103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_22 = _w_out_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_23 = _w_out_bits_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_out_bits_legal_T_24 = {w_addr[31:26], w_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_25 = {1'h0, _w_out_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_26 = _w_out_bits_legal_T_25 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_27 = _w_out_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_28 = _w_out_bits_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_out_bits_legal_T_29 = {w_addr[31:28], w_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_30 = {1'h0, _w_out_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_31 = _w_out_bits_legal_T_30 & 33'hC8000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_32 = _w_out_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_33 = _w_out_bits_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _w_out_bits_legal_T_34 = w_addr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_35 = {1'h0, _w_out_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_36 = _w_out_bits_legal_T_35 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_37 = _w_out_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_38 = _w_out_bits_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_out_bits_legal_T_39 = _w_out_bits_legal_T_18 | _w_out_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _w_out_bits_legal_T_40 = _w_out_bits_legal_T_39 | _w_out_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _w_out_bits_legal_T_41 = _w_out_bits_legal_T_40 | _w_out_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _w_out_bits_legal_T_42 = _w_out_bits_legal_T_41 | _w_out_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _w_out_bits_legal_T_43 = _w_out_bits_legal_T_13 & _w_out_bits_legal_T_42; // @[Parameters.scala:684:{29,54}, :685:42]
wire [31:0] _w_out_bits_legal_T_45 = {w_addr[31:17], w_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_46 = {1'h0, _w_out_bits_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_47 = _w_out_bits_legal_T_46 & 33'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_48 = _w_out_bits_legal_T_47; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_49 = _w_out_bits_legal_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_out_bits_legal_T_53 = _w_out_bits_legal_T_52; // @[Parameters.scala:92:{33,38}]
wire _w_out_bits_legal_T_54 = _w_out_bits_legal_T_53; // @[Parameters.scala:684:29]
wire [31:0] _w_out_bits_legal_T_55 = {w_addr[31], w_addr[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31]
wire [32:0] _w_out_bits_legal_T_56 = {1'h0, _w_out_bits_legal_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _w_out_bits_legal_T_57 = _w_out_bits_legal_T_56 & 33'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _w_out_bits_legal_T_58 = _w_out_bits_legal_T_57; // @[Parameters.scala:137:46]
wire _w_out_bits_legal_T_59 = _w_out_bits_legal_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _w_out_bits_legal_T_60 = _w_out_bits_legal_T_54 & _w_out_bits_legal_T_59; // @[Parameters.scala:684:{29,54}]
wire _w_out_bits_legal_T_62 = _w_out_bits_legal_T_61 | _w_out_bits_legal_T_43; // @[Parameters.scala:684:54, :686:26]
wire _w_out_bits_legal_T_63 = _w_out_bits_legal_T_62; // @[Parameters.scala:686:26]
wire w_out_bits_legal = _w_out_bits_legal_T_63 | _w_out_bits_legal_T_60; // @[Parameters.scala:684:54, :686:26]
assign w_out_bits_size = w_out_bits_a_size; // @[Edges.scala:500:17]
assign w_out_bits_source = w_out_bits_a_source; // @[Edges.scala:500:17]
assign w_out_bits_address = w_out_bits_a_address; // @[Edges.scala:500:17]
assign w_out_bits_mask = w_out_bits_a_mask; // @[Edges.scala:500:17]
assign w_out_bits_data = w_out_bits_a_data; // @[Edges.scala:500:17]
assign _w_out_bits_user_amba_prot_privileged_T = nodeIn_aw_bits_prot[0]; // @[ToTL.scala:163:45]
assign w_out_bits_user_amba_prot_privileged = _w_out_bits_user_amba_prot_privileged_T; // @[ToTL.scala:138:30, :163:45]
wire _w_out_bits_user_amba_prot_secure_T = nodeIn_aw_bits_prot[1]; // @[ToTL.scala:164:45]
assign _w_out_bits_user_amba_prot_secure_T_1 = ~_w_out_bits_user_amba_prot_secure_T; // @[ToTL.scala:164:{29,45}]
assign w_out_bits_user_amba_prot_secure = _w_out_bits_user_amba_prot_secure_T_1; // @[ToTL.scala:138:30, :164:29]
assign _w_out_bits_user_amba_prot_fetch_T = nodeIn_aw_bits_prot[2]; // @[ToTL.scala:165:45]
assign w_out_bits_user_amba_prot_fetch = _w_out_bits_user_amba_prot_fetch_T; // @[ToTL.scala:138:30, :165:45]
assign _w_out_bits_user_amba_prot_bufferable_T = nodeIn_aw_bits_cache[0]; // @[ToTL.scala:166:46]
assign w_out_bits_user_amba_prot_bufferable = _w_out_bits_user_amba_prot_bufferable_T; // @[ToTL.scala:138:30, :166:46]
assign _w_out_bits_user_amba_prot_modifiable_T = nodeIn_aw_bits_cache[1]; // @[ToTL.scala:167:46]
assign w_out_bits_user_amba_prot_modifiable = _w_out_bits_user_amba_prot_modifiable_T; // @[ToTL.scala:138:30, :167:46]
assign _w_out_bits_user_amba_prot_readalloc_T = nodeIn_aw_bits_cache[2]; // @[ToTL.scala:168:46]
assign w_out_bits_user_amba_prot_readalloc = _w_out_bits_user_amba_prot_readalloc_T; // @[ToTL.scala:138:30, :168:46]
assign _w_out_bits_user_amba_prot_writealloc_T = nodeIn_aw_bits_cache[3]; // @[ToTL.scala:169:46]
assign w_out_bits_user_amba_prot_writealloc = _w_out_bits_user_amba_prot_writealloc_T; // @[ToTL.scala:138:30, :169:46]
wire [1:0] _w_sel_T = 2'h1 << w_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] w_sel = _w_sel_T; // @[OneHot.scala:65:{12,27}]
wire [3:0] _w_count_0_T = {1'h0, w_count_0} + 4'h1; // @[ToTL.scala:143:28, :174:41]
wire [2:0] _w_count_0_T_1 = _w_count_0_T[2:0]; // @[ToTL.scala:174:41]
wire [3:0] _w_count_1_T = {1'h0, w_count_1} + 4'h1; // @[ToTL.scala:143:28, :174:41]
wire [2:0] _w_count_1_T_1 = _w_count_1_T[2:0]; // @[ToTL.scala:174:41]
reg [7:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {w_out_valid, r_out_valid}; // @[Arbiter.scala:68:51]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & r_out_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & w_out_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = r_out_valid | w_out_valid; // @[Arbiter.scala:79:31, :96:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLROM :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_53
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire rom : UInt<64>[512]
connect rom[0], UInt<64>(0h405051300000517)
connect rom[1], UInt<64>(0h301022f330551073)
connect rom[2], UInt<64>(0h12f2934122d293)
connect rom[3], UInt<64>(0h3030107300028863)
connect rom[4], UInt<64>(0h3445307322200513)
connect rom[5], UInt<64>(0h3045107300800513)
connect rom[6], UInt<64>(0h1050007330052073)
connect rom[7], UInt<64>(0hffdff06f)
connect rom[8], UInt<64>(0hf1402573020005b7)
connect rom[9], UInt<64>(0h380006f00050463)
connect rom[10], UInt<64>(0h10069300458613)
connect rom[11], UInt<64>(0h46061300d62023)
connect rom[12], UInt<64>(0hfe069ae3ffc62683)
connect rom[13], UInt<64>(0h2c0006f)
connect rom[14], UInt<64>(0h0)
connect rom[15], UInt<64>(0h0)
connect rom[16], UInt<64>(0h5a283f81ff06f)
connect rom[17], UInt<64>(0h251513fe029ee3)
connect rom[18], UInt<64>(0h5a02300b505b3)
connect rom[19], UInt<64>(0h5350300001537)
connect rom[20], UInt<64>(0hf140257334151073)
connect rom[21], UInt<64>(0h185859300000597)
connect rom[22], UInt<64>(0h3006307308000613)
connect rom[23], UInt<64>(0h1330200073)
connect rom[24], UInt<64>(0he0000edfe0dd0)
connect rom[25], UInt<64>(0ha00b000038000000)
connect rom[26], UInt<64>(0h1100000028000000)
connect rom[27], UInt<64>(0h10000000)
connect rom[28], UInt<64>(0h680b000060020000)
connect rom[29], UInt<64>(0h0)
connect rom[30], UInt<64>(0h0)
connect rom[31], UInt<64>(0h1000000)
connect rom[32], UInt<64>(0h400000003000000)
connect rom[33], UInt<64>(0h100000000000000)
connect rom[34], UInt<64>(0h400000003000000)
connect rom[35], UInt<64>(0h10000000f000000)
connect rom[36], UInt<64>(0h1500000003000000)
connect rom[37], UInt<64>(0h2d6263751b000000)
connect rom[38], UInt<64>(0h706968632c726162)
connect rom[39], UInt<64>(0h7665642d64726179)
connect rom[40], UInt<64>(0h300000000000000)
connect rom[41], UInt<64>(0h2600000011000000)
connect rom[42], UInt<64>(0h2c7261622d626375)
connect rom[43], UInt<64>(0h6472617970696863)
connect rom[44], UInt<64>(0h100000000000000)
connect rom[45], UInt<64>(0h73657361696c61)
connect rom[46], UInt<64>(0h1500000003000000)
connect rom[47], UInt<64>(0h636f732f2c000000)
connect rom[48], UInt<64>(0h406c61697265732f)
connect rom[49], UInt<64>(0h3030303032303031)
connect rom[50], UInt<64>(0h200000000000000)
connect rom[51], UInt<64>(0h736f686301000000)
connect rom[52], UInt<64>(0h300000000006e65)
connect rom[53], UInt<64>(0h3400000015000000)
connect rom[54], UInt<64>(0h7265732f636f732f)
connect rom[55], UInt<64>(0h32303031406c6169)
connect rom[56], UInt<64>(0h30303030)
connect rom[57], UInt<64>(0h100000002000000)
connect rom[58], UInt<64>(0h73757063)
connect rom[59], UInt<64>(0h400000003000000)
connect rom[60], UInt<64>(0h100000000000000)
connect rom[61], UInt<64>(0h400000003000000)
connect rom[62], UInt<64>(0hf000000)
connect rom[63], UInt<64>(0h400000003000000)
connect rom[64], UInt<64>(0h20a1070040000000)
connect rom[65], UInt<64>(0h4075706301000000)
connect rom[66], UInt<64>(0h300000000000030)
connect rom[67], UInt<64>(0h5300000004000000)
connect rom[68], UInt<64>(0h300000000000000)
connect rom[69], UInt<64>(0h1b00000014000000)
connect rom[70], UInt<64>(0h2c7261622d626375)
connect rom[71], UInt<64>(0h697200306d6f6f62)
connect rom[72], UInt<64>(0h300000000766373)
connect rom[73], UInt<64>(0h6300000004000000)
connect rom[74], UInt<64>(0h300000040000000)
connect rom[75], UInt<64>(0h7600000004000000)
connect rom[76], UInt<64>(0h300000040000000)
connect rom[77], UInt<64>(0h8300000004000000)
connect rom[78], UInt<64>(0h300000000400000)
connect rom[79], UInt<64>(0h9000000004000000)
connect rom[80], UInt<64>(0h300000001000000)
connect rom[81], UInt<64>(0h9b00000004000000)
connect rom[82], UInt<64>(0h300000008000000)
connect rom[83], UInt<64>(0ha600000004000000)
connect rom[84], UInt<64>(0h300000000757063)
connect rom[85], UInt<64>(0hb200000004000000)
connect rom[86], UInt<64>(0h300000000000000)
connect rom[87], UInt<64>(0hd100000004000000)
connect rom[88], UInt<64>(0h300000040000000)
connect rom[89], UInt<64>(0he400000004000000)
connect rom[90], UInt<64>(0h300000040000000)
connect rom[91], UInt<64>(0hf100000004000000)
connect rom[92], UInt<64>(0h300000000400000)
connect rom[93], UInt<64>(0hfe00000004000000)
connect rom[94], UInt<64>(0h300000001000000)
connect rom[95], UInt<64>(0h901000004000000)
connect rom[96], UInt<64>(0h300000020000000)
connect rom[97], UInt<64>(0h140100000b000000)
connect rom[98], UInt<64>(0h76732c7663736972)
connect rom[99], UInt<64>(0h300000000003933)
connect rom[100], UInt<64>(0h1d01000004000000)
connect rom[101], UInt<64>(0h300000001000000)
connect rom[102], UInt<64>(0h2e01000004000000)
connect rom[103], UInt<64>(0h300000000000000)
connect rom[104], UInt<64>(0h320100002c000000)
connect rom[105], UInt<64>(0h66616d6934367672)
connect rom[106], UInt<64>(0h727363697a626364)
connect rom[107], UInt<64>(0h65636e6566697a5f)
connect rom[108], UInt<64>(0h5f6d7068697a5f69)
connect rom[109], UInt<64>(0h5f62627a5f61627a)
connect rom[110], UInt<64>(0h30000000073627a)
connect rom[111], UInt<64>(0h3c01000004000000)
connect rom[112], UInt<64>(0h300000004000000)
connect rom[113], UInt<64>(0h5101000004000000)
connect rom[114], UInt<64>(0h300000008000000)
connect rom[115], UInt<64>(0h6201000005000000)
connect rom[116], UInt<64>(0h79616b6f)
connect rom[117], UInt<64>(0h400000003000000)
connect rom[118], UInt<64>(0h20a1070040000000)
connect rom[119], UInt<64>(0h3000000)
connect rom[120], UInt<64>(0h100000069010000)
connect rom[121], UInt<64>(0h7075727265746e69)
connect rom[122], UInt<64>(0h6f72746e6f632d74)
connect rom[123], UInt<64>(0h72656c6c)
connect rom[124], UInt<64>(0h400000003000000)
connect rom[125], UInt<64>(0h100000073010000)
connect rom[126], UInt<64>(0hf00000003000000)
connect rom[127], UInt<64>(0h637369721b000000)
connect rom[128], UInt<64>(0h6e692d7570632c76)
connect rom[129], UInt<64>(0h300000000006374)
connect rom[130], UInt<64>(0h8401000000000000)
connect rom[131], UInt<64>(0h400000003000000)
connect rom[132], UInt<64>(0h400000099010000)
connect rom[133], UInt<64>(0h200000002000000)
connect rom[134], UInt<64>(0h100000002000000)
connect rom[135], UInt<64>(0h66697468)
connect rom[136], UInt<64>(0ha00000003000000)
connect rom[137], UInt<64>(0h2c6263751b000000)
connect rom[138], UInt<64>(0h3066697468)
connect rom[139], UInt<64>(0h100000002000000)
connect rom[140], UInt<64>(0h384079726f6d656d)
connect rom[141], UInt<64>(0h303030303030)
connect rom[142], UInt<64>(0h700000003000000)
connect rom[143], UInt<64>(0h6f6d656da6000000)
connect rom[144], UInt<64>(0h300000000007972)
connect rom[145], UInt<64>(0h2e01000008000000)
connect rom[146], UInt<64>(0h10000000008)
connect rom[147], UInt<64>(0h900000003000000)
connect rom[148], UInt<64>(0h6173696462010000)
connect rom[149], UInt<64>(0h64656c62)
connect rom[150], UInt<64>(0h400000003000000)
connect rom[151], UInt<64>(0h300000099010000)
connect rom[152], UInt<64>(0h100000002000000)
connect rom[153], UInt<64>(0h384079726f6d656d)
connect rom[154], UInt<64>(0h30303030303030)
connect rom[155], UInt<64>(0h700000003000000)
connect rom[156], UInt<64>(0h6f6d656da6000000)
connect rom[157], UInt<64>(0h300000000007972)
connect rom[158], UInt<64>(0h2e01000008000000)
connect rom[159], UInt<64>(0h1000000080)
connect rom[160], UInt<64>(0h400000003000000)
connect rom[161], UInt<64>(0h200000099010000)
connect rom[162], UInt<64>(0h100000002000000)
connect rom[163], UInt<64>(0h300000000636f73)
connect rom[164], UInt<64>(0h4000000)
connect rom[165], UInt<64>(0h300000001000000)
connect rom[166], UInt<64>(0hf00000004000000)
connect rom[167], UInt<64>(0h300000001000000)
connect rom[168], UInt<64>(0h1b00000020000000)
connect rom[169], UInt<64>(0h2c7261622d626375)
connect rom[170], UInt<64>(0h6472617970696863)
connect rom[171], UInt<64>(0h6d697300636f732d)
connect rom[172], UInt<64>(0h7375622d656c70)
connect rom[173], UInt<64>(0h3000000)
connect rom[174], UInt<64>(0h1000000a1010000)
connect rom[175], UInt<64>(0h6464612d746f6f62)
connect rom[176], UInt<64>(0h6765722d73736572)
connect rom[177], UInt<64>(0h3030303140)
connect rom[178], UInt<64>(0h800000003000000)
connect rom[179], UInt<64>(0h1000002e010000)
connect rom[180], UInt<64>(0h300000000100000)
connect rom[181], UInt<64>(0ha801000008000000)
connect rom[182], UInt<64>(0h6c6f72746e6f63)
connect rom[183], UInt<64>(0h100000002000000)
connect rom[184], UInt<64>(0h6f632d6568636163)
connect rom[185], UInt<64>(0h72656c6c6f72746e)
connect rom[186], UInt<64>(0h3030303031303240)
connect rom[187], UInt<64>(0h300000000000000)
connect rom[188], UInt<64>(0h6500000004000000)
connect rom[189], UInt<64>(0h300000040000000)
connect rom[190], UInt<64>(0hb201000004000000)
connect rom[191], UInt<64>(0h300000002000000)
connect rom[192], UInt<64>(0h7800000004000000)
connect rom[193], UInt<64>(0h300000000040000)
connect rom[194], UInt<64>(0h8500000004000000)
connect rom[195], UInt<64>(0h300000000000800)
connect rom[196], UInt<64>(0hbe01000000000000)
connect rom[197], UInt<64>(0h1d00000003000000)
connect rom[198], UInt<64>(0h696669731b000000)
connect rom[199], UInt<64>(0h756c636e692c6576)
connect rom[200], UInt<64>(0h6863616365766973)
connect rom[201], UInt<64>(0h6568636163003065)
connect rom[202], UInt<64>(0h300000000000000)
connect rom[203], UInt<64>(0h1d01000008000000)
connect rom[204], UInt<64>(0h300000002000000)
connect rom[205], UInt<64>(0h800000003000000)
connect rom[206], UInt<64>(0h1022e010000)
connect rom[207], UInt<64>(0h300000000100000)
connect rom[208], UInt<64>(0ha801000008000000)
connect rom[209], UInt<64>(0h6c6f72746e6f63)
connect rom[210], UInt<64>(0h400000003000000)
connect rom[211], UInt<64>(0h7000000cc010000)
connect rom[212], UInt<64>(0h400000003000000)
connect rom[213], UInt<64>(0h100000099010000)
connect rom[214], UInt<64>(0h100000002000000)
connect rom[215], UInt<64>(0h6f6c635f73756263)
connect rom[216], UInt<64>(0h300000000006b63)
connect rom[217], UInt<64>(0hde01000004000000)
connect rom[218], UInt<64>(0h300000000000000)
connect rom[219], UInt<64>(0h5300000004000000)
connect rom[220], UInt<64>(0h30000000065cd1d)
connect rom[221], UInt<64>(0heb0100000b000000)
connect rom[222], UInt<64>(0h6f6c635f73756263)
connect rom[223], UInt<64>(0h300000000006b63)
connect rom[224], UInt<64>(0h1b0000000c000000)
connect rom[225], UInt<64>(0h6c632d6465786966)
connect rom[226], UInt<64>(0h2000000006b636f)
connect rom[227], UInt<64>(0h6e696c6301000000)
connect rom[228], UInt<64>(0h3030303030324074)
connect rom[229], UInt<64>(0h300000000000030)
connect rom[230], UInt<64>(0h1b0000000d000000)
connect rom[231], UInt<64>(0h6c632c7663736972)
connect rom[232], UInt<64>(0h30746e69)
connect rom[233], UInt<64>(0h1000000003000000)
connect rom[234], UInt<64>(0h4000000fe010000)
connect rom[235], UInt<64>(0h400000003000000)
connect rom[236], UInt<64>(0h300000007000000)
connect rom[237], UInt<64>(0h2e01000008000000)
connect rom[238], UInt<64>(0h10000000002)
connect rom[239], UInt<64>(0h800000003000000)
connect rom[240], UInt<64>(0h746e6f63a8010000)
connect rom[241], UInt<64>(0h2000000006c6f72)
connect rom[242], UInt<64>(0h636f6c6301000000)
connect rom[243], UInt<64>(0h4072657461672d6b)
connect rom[244], UInt<64>(0h303030303031)
connect rom[245], UInt<64>(0h800000003000000)
connect rom[246], UInt<64>(0h10002e010000)
connect rom[247], UInt<64>(0h300000000100000)
connect rom[248], UInt<64>(0ha801000008000000)
connect rom[249], UInt<64>(0h6c6f72746e6f63)
connect rom[250], UInt<64>(0h100000002000000)
connect rom[251], UInt<64>(0h6f632d6775626564)
connect rom[252], UInt<64>(0h72656c6c6f72746e)
connect rom[253], UInt<64>(0h300000000003040)
connect rom[254], UInt<64>(0h1b00000021000000)
connect rom[255], UInt<64>(0h642c657669666973)
connect rom[256], UInt<64>(0h3331302d67756265)
connect rom[257], UInt<64>(0h642c766373697200)
connect rom[258], UInt<64>(0h3331302d67756265)
connect rom[259], UInt<64>(0h300000000000000)
connect rom[260], UInt<64>(0h1202000005000000)
connect rom[261], UInt<64>(0h6761746a)
connect rom[262], UInt<64>(0h800000003000000)
connect rom[263], UInt<64>(0h4000000fe010000)
connect rom[264], UInt<64>(0h3000000ffff0000)
connect rom[265], UInt<64>(0h2e01000008000000)
connect rom[266], UInt<64>(0h10000000000000)
connect rom[267], UInt<64>(0h800000003000000)
connect rom[268], UInt<64>(0h746e6f63a8010000)
connect rom[269], UInt<64>(0h2000000006c6f72)
connect rom[270], UInt<64>(0h6f72726501000000)
connect rom[271], UInt<64>(0h6563697665642d72)
connect rom[272], UInt<64>(0h3030303340)
connect rom[273], UInt<64>(0he00000003000000)
connect rom[274], UInt<64>(0h696669731b000000)
connect rom[275], UInt<64>(0h726f7272652c6576)
connect rom[276], UInt<64>(0h300000000000030)
connect rom[277], UInt<64>(0h2e01000008000000)
connect rom[278], UInt<64>(0h10000000300000)
connect rom[279], UInt<64>(0h100000002000000)
connect rom[280], UInt<64>(0h6f6c635f73756266)
connect rom[281], UInt<64>(0h300000000006b63)
connect rom[282], UInt<64>(0hde01000004000000)
connect rom[283], UInt<64>(0h300000000000000)
connect rom[284], UInt<64>(0h5300000004000000)
connect rom[285], UInt<64>(0h30000000065cd1d)
connect rom[286], UInt<64>(0heb0100000b000000)
connect rom[287], UInt<64>(0h6f6c635f73756266)
connect rom[288], UInt<64>(0h300000000006b63)
connect rom[289], UInt<64>(0h1b0000000c000000)
connect rom[290], UInt<64>(0h6c632d6465786966)
connect rom[291], UInt<64>(0h2000000006b636f)
connect rom[292], UInt<64>(0h65746e6901000000)
connect rom[293], UInt<64>(0h6f632d7470757272)
connect rom[294], UInt<64>(0h72656c6c6f72746e)
connect rom[295], UInt<64>(0h3030303030306340)
connect rom[296], UInt<64>(0h300000000000000)
connect rom[297], UInt<64>(0h7301000004000000)
connect rom[298], UInt<64>(0h300000001000000)
connect rom[299], UInt<64>(0h1b0000000c000000)
connect rom[300], UInt<64>(0h6c702c7663736972)
connect rom[301], UInt<64>(0h300000000306369)
connect rom[302], UInt<64>(0h8401000000000000)
connect rom[303], UInt<64>(0h1000000003000000)
connect rom[304], UInt<64>(0h4000000fe010000)
connect rom[305], UInt<64>(0h40000000b000000)
connect rom[306], UInt<64>(0h300000009000000)
connect rom[307], UInt<64>(0h2e01000008000000)
connect rom[308], UInt<64>(0h40000000c)
connect rom[309], UInt<64>(0h800000003000000)
connect rom[310], UInt<64>(0h746e6f63a8010000)
connect rom[311], UInt<64>(0h3000000006c6f72)
connect rom[312], UInt<64>(0h1f02000004000000)
connect rom[313], UInt<64>(0h300000001000000)
connect rom[314], UInt<64>(0h3202000004000000)
connect rom[315], UInt<64>(0h300000001000000)
connect rom[316], UInt<64>(0h9901000004000000)
connect rom[317], UInt<64>(0h200000006000000)
connect rom[318], UInt<64>(0h7375626d01000000)
connect rom[319], UInt<64>(0h6b636f6c635f)
connect rom[320], UInt<64>(0h400000003000000)
connect rom[321], UInt<64>(0hde010000)
connect rom[322], UInt<64>(0h400000003000000)
connect rom[323], UInt<64>(0h65cd1d53000000)
connect rom[324], UInt<64>(0hb00000003000000)
connect rom[325], UInt<64>(0h7375626deb010000)
connect rom[326], UInt<64>(0h6b636f6c635f)
connect rom[327], UInt<64>(0hc00000003000000)
connect rom[328], UInt<64>(0h657869661b000000)
connect rom[329], UInt<64>(0h6b636f6c632d64)
connect rom[330], UInt<64>(0h100000002000000)
connect rom[331], UInt<64>(0h6f6c635f73756270)
connect rom[332], UInt<64>(0h300000000006b63)
connect rom[333], UInt<64>(0hde01000004000000)
connect rom[334], UInt<64>(0h300000000000000)
connect rom[335], UInt<64>(0h5300000004000000)
connect rom[336], UInt<64>(0h30000000065cd1d)
connect rom[337], UInt<64>(0heb0100000b000000)
connect rom[338], UInt<64>(0h6f6c635f73756270)
connect rom[339], UInt<64>(0h300000000006b63)
connect rom[340], UInt<64>(0h1b0000000c000000)
connect rom[341], UInt<64>(0h6c632d6465786966)
connect rom[342], UInt<64>(0h3000000006b636f)
connect rom[343], UInt<64>(0h9901000004000000)
connect rom[344], UInt<64>(0h200000005000000)
connect rom[345], UInt<64>(0h406d6f7201000000)
connect rom[346], UInt<64>(0h3030303031)
connect rom[347], UInt<64>(0hc00000003000000)
connect rom[348], UInt<64>(0h696669731b000000)
connect rom[349], UInt<64>(0h306d6f722c6576)
connect rom[350], UInt<64>(0h800000003000000)
connect rom[351], UInt<64>(0h1002e010000)
connect rom[352], UInt<64>(0h300000000000100)
connect rom[353], UInt<64>(0ha801000004000000)
connect rom[354], UInt<64>(0h2000000006d656d)
connect rom[355], UInt<64>(0h7375627301000000)
connect rom[356], UInt<64>(0h6b636f6c635f)
connect rom[357], UInt<64>(0h400000003000000)
connect rom[358], UInt<64>(0hde010000)
connect rom[359], UInt<64>(0h400000003000000)
connect rom[360], UInt<64>(0h65cd1d53000000)
connect rom[361], UInt<64>(0hb00000003000000)
connect rom[362], UInt<64>(0h73756273eb010000)
connect rom[363], UInt<64>(0h6b636f6c635f)
connect rom[364], UInt<64>(0hc00000003000000)
connect rom[365], UInt<64>(0h657869661b000000)
connect rom[366], UInt<64>(0h6b636f6c632d64)
connect rom[367], UInt<64>(0h100000002000000)
connect rom[368], UInt<64>(0h31406c6169726573)
connect rom[369], UInt<64>(0h30303030323030)
connect rom[370], UInt<64>(0h400000003000000)
connect rom[371], UInt<64>(0h50000003d020000)
connect rom[372], UInt<64>(0hd00000003000000)
connect rom[373], UInt<64>(0h696669731b000000)
connect rom[374], UInt<64>(0h30747261752c6576)
connect rom[375], UInt<64>(0h300000000000000)
connect rom[376], UInt<64>(0h4402000004000000)
connect rom[377], UInt<64>(0h300000006000000)
connect rom[378], UInt<64>(0h5502000004000000)
connect rom[379], UInt<64>(0h300000001000000)
connect rom[380], UInt<64>(0h2e01000008000000)
connect rom[381], UInt<64>(0h10000000000210)
connect rom[382], UInt<64>(0h800000003000000)
connect rom[383], UInt<64>(0h746e6f63a8010000)
connect rom[384], UInt<64>(0h2000000006c6f72)
connect rom[385], UInt<64>(0h656c697401000000)
connect rom[386], UInt<64>(0h732d74657365722d)
connect rom[387], UInt<64>(0h3131407265747465)
connect rom[388], UInt<64>(0h30303030)
connect rom[389], UInt<64>(0h800000003000000)
connect rom[390], UInt<64>(0h11002e010000)
connect rom[391], UInt<64>(0h300000000100000)
connect rom[392], UInt<64>(0ha801000008000000)
connect rom[393], UInt<64>(0h6c6f72746e6f63)
connect rom[394], UInt<64>(0h200000002000000)
connect rom[395], UInt<64>(0h900000002000000)
connect rom[396], UInt<64>(0h7373657264646123)
connect rom[397], UInt<64>(0h2300736c6c65632d)
connect rom[398], UInt<64>(0h6c65632d657a6973)
connect rom[399], UInt<64>(0h61706d6f6300736c)
connect rom[400], UInt<64>(0h6f6d00656c626974)
connect rom[401], UInt<64>(0h69726573006c6564)
connect rom[402], UInt<64>(0h6f64747300306c61)
connect rom[403], UInt<64>(0h687461702d7475)
connect rom[404], UInt<64>(0h65736162656d6974)
connect rom[405], UInt<64>(0h6e6575716572662d)
connect rom[406], UInt<64>(0h6b636f6c63007963)
connect rom[407], UInt<64>(0h6e6575716572662d)
connect rom[408], UInt<64>(0h6361632d64007963)
connect rom[409], UInt<64>(0h6b636f6c622d6568)
connect rom[410], UInt<64>(0h2d6400657a69732d)
connect rom[411], UInt<64>(0h65732d6568636163)
connect rom[412], UInt<64>(0h6361632d64007374)
connect rom[413], UInt<64>(0h657a69732d6568)
connect rom[414], UInt<64>(0h65732d626c742d64)
connect rom[415], UInt<64>(0h626c742d64007374)
connect rom[416], UInt<64>(0h656400657a69732d)
connect rom[417], UInt<64>(0h7079745f65636976)
connect rom[418], UInt<64>(0h6177647261680065)
connect rom[419], UInt<64>(0h2d636578652d6572)
connect rom[420], UInt<64>(0h696f706b61657262)
connect rom[421], UInt<64>(0h746e756f632d746e)
connect rom[422], UInt<64>(0h65686361632d6900)
connect rom[423], UInt<64>(0h732d6b636f6c622d)
connect rom[424], UInt<64>(0h61632d6900657a69)
connect rom[425], UInt<64>(0h737465732d656863)
connect rom[426], UInt<64>(0h65686361632d6900)
connect rom[427], UInt<64>(0h2d6900657a69732d)
connect rom[428], UInt<64>(0h737465732d626c74)
connect rom[429], UInt<64>(0h732d626c742d6900)
connect rom[430], UInt<64>(0h2d756d6d00657a69)
connect rom[431], UInt<64>(0h78656e0065707974)
connect rom[432], UInt<64>(0h2d6c6576656c2d74)
connect rom[433], UInt<64>(0h6572006568636163)
connect rom[434], UInt<64>(0h2c76637369720067)
connect rom[435], UInt<64>(0h6373697200617369)
connect rom[436], UInt<64>(0h617267706d702c76)
connect rom[437], UInt<64>(0h79746972616c756e)
connect rom[438], UInt<64>(0h702c766373697200)
connect rom[439], UInt<64>(0h6e6f69676572706d)
connect rom[440], UInt<64>(0h7375746174730073)
connect rom[441], UInt<64>(0h6c70732d626c7400)
connect rom[442], UInt<64>(0h65746e6923007469)
connect rom[443], UInt<64>(0h65632d7470757272)
connect rom[444], UInt<64>(0h65746e6900736c6c)
connect rom[445], UInt<64>(0h6f632d7470757272)
connect rom[446], UInt<64>(0h72656c6c6f72746e)
connect rom[447], UInt<64>(0h656c646e61687000)
connect rom[448], UInt<64>(0h7365676e617200)
connect rom[449], UInt<64>(0h656d616e2d676572)
connect rom[450], UInt<64>(0h2d65686361630073)
connect rom[451], UInt<64>(0h6163006c6576656c)
connect rom[452], UInt<64>(0h66696e752d656863)
connect rom[453], UInt<64>(0h6966697300646569)
connect rom[454], UInt<64>(0h2d7268736d2c6576)
connect rom[455], UInt<64>(0h632300746e756f63)
connect rom[456], UInt<64>(0h6c65632d6b636f6c)
connect rom[457], UInt<64>(0h6b636f6c6300736c)
connect rom[458], UInt<64>(0h2d74757074756f2d)
connect rom[459], UInt<64>(0h6e690073656d616e)
connect rom[460], UInt<64>(0h7374707572726574)
connect rom[461], UInt<64>(0h65646e657478652d)
connect rom[462], UInt<64>(0h2d67756265640064)
connect rom[463], UInt<64>(0h7200686361747461)
connect rom[464], UInt<64>(0h78616d2c76637369)
connect rom[465], UInt<64>(0h7469726f6972702d)
connect rom[466], UInt<64>(0h2c76637369720079)
connect rom[467], UInt<64>(0h6f6c63007665646e)
connect rom[468], UInt<64>(0h65746e6900736b63)
connect rom[469], UInt<64>(0h61702d7470757272)
connect rom[470], UInt<64>(0h746e6900746e6572)
connect rom[471], UInt<64>(0h73747075727265)
connect rom[472], UInt<64>(0h0)
connect rom[473], UInt<64>(0h0)
connect rom[474], UInt<64>(0h0)
connect rom[475], UInt<64>(0h0)
connect rom[476], UInt<64>(0h0)
connect rom[477], UInt<64>(0h0)
connect rom[478], UInt<64>(0h0)
connect rom[479], UInt<64>(0h0)
connect rom[480], UInt<64>(0h0)
connect rom[481], UInt<64>(0h0)
connect rom[482], UInt<64>(0h0)
connect rom[483], UInt<64>(0h0)
connect rom[484], UInt<64>(0h0)
connect rom[485], UInt<64>(0h0)
connect rom[486], UInt<64>(0h0)
connect rom[487], UInt<64>(0h0)
connect rom[488], UInt<64>(0h0)
connect rom[489], UInt<64>(0h0)
connect rom[490], UInt<64>(0h0)
connect rom[491], UInt<64>(0h0)
connect rom[492], UInt<64>(0h0)
connect rom[493], UInt<64>(0h0)
connect rom[494], UInt<64>(0h0)
connect rom[495], UInt<64>(0h0)
connect rom[496], UInt<64>(0h0)
connect rom[497], UInt<64>(0h0)
connect rom[498], UInt<64>(0h0)
connect rom[499], UInt<64>(0h0)
connect rom[500], UInt<64>(0h0)
connect rom[501], UInt<64>(0h0)
connect rom[502], UInt<64>(0h0)
connect rom[503], UInt<64>(0h0)
connect rom[504], UInt<64>(0h0)
connect rom[505], UInt<64>(0h0)
connect rom[506], UInt<64>(0h0)
connect rom[507], UInt<64>(0h0)
connect rom[508], UInt<64>(0h0)
connect rom[509], UInt<64>(0h0)
connect rom[510], UInt<64>(0h0)
connect rom[511], UInt<64>(0h0)
connect nodeIn.d.valid, nodeIn.a.valid
connect nodeIn.a.ready, nodeIn.d.ready
node index = bits(nodeIn.a.bits.address, 11, 3)
node high = bits(nodeIn.a.bits.address, 15, 12)
node _nodeIn_d_bits_T = orr(high)
node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index])
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h1)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, nodeIn.a.bits.size
connect nodeIn_d_bits_d.source, nodeIn.a.bits.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h73747075727265,
64'h746E6900746E6572,
64'h61702D7470757272,
64'h65746E6900736B63,
64'h6F6C63007665646E,
64'h2C76637369720079,
64'h7469726F6972702D,
64'h78616D2C76637369,
64'h7200686361747461,
64'h2D67756265640064,
64'h65646E657478652D,
64'h7374707572726574,
64'h6E690073656D616E,
64'h2D74757074756F2D,
64'h6B636F6C6300736C,
64'h6C65632D6B636F6C,
64'h632300746E756F63,
64'h2D7268736D2C6576,
64'h6966697300646569,
64'h66696E752D656863,
64'h6163006C6576656C,
64'h2D65686361630073,
64'h656D616E2D676572,
64'h7365676E617200,
64'h656C646E61687000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6900736C6C,
64'h65632D7470757272,
64'h65746E6923007469,
64'h6C70732D626C7400,
64'h7375746174730073,
64'h6E6F69676572706D,
64'h702C766373697200,
64'h79746972616C756E,
64'h617267706D702C76,
64'h6373697200617369,
64'h2C76637369720067,
64'h6572006568636163,
64'h2D6C6576656C2D74,
64'h78656E0065707974,
64'h2D756D6D00657A69,
64'h732D626C742D6900,
64'h737465732D626C74,
64'h2D6900657A69732D,
64'h65686361632D6900,
64'h737465732D656863,
64'h61632D6900657A69,
64'h732D6B636F6C622D,
64'h65686361632D6900,
64'h746E756F632D746E,
64'h696F706B61657262,
64'h2D636578652D6572,
64'h6177647261680065,
64'h7079745F65636976,
64'h656400657A69732D,
64'h626C742D64007374,
64'h65732D626C742D64,
64'h657A69732D6568,
64'h6361632D64007374,
64'h65732D6568636163,
64'h2D6400657A69732D,
64'h6B636F6C622D6568,
64'h6361632D64007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
64'h200000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h11002E010000,
64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000210,
64'h2E01000008000000,
64'h300000001000000,
64'h5502000004000000,
64'h300000006000000,
64'h4402000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h50000003D020000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756273EB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
64'hA801000004000000,
64'h300000000000100,
64'h1002E010000,
64'h800000003000000,
64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000005000000,
64'h9901000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h7375626DEB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626D01000000,
64'h200000006000000,
64'h9901000004000000,
64'h300000001000000,
64'h3202000004000000,
64'h300000001000000,
64'h1F02000004000000,
64'h3000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h40000000C,
64'h2E01000008000000,
64'h300000009000000,
64'h40000000B000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h8401000000000000,
64'h300000000306369,
64'h6C702C7663736972,
64'h1B0000000C000000,
64'h300000001000000,
64'h7301000004000000,
64'h300000000000000,
64'h3030303030306340,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'h100000002000000,
64'h10000000300000,
64'h2E01000008000000,
64'h300000000000030,
64'h726F7272652C6576,
64'h696669731B000000,
64'hE00000003000000,
64'h3030303340,
64'h6563697665642D72,
64'h6F72726501000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000000,
64'h2E01000008000000,
64'h3000000FFFF0000,
64'h4000000FE010000,
64'h800000003000000,
64'h6761746A,
64'h1202000005000000,
64'h300000000000000,
64'h3331302D67756265,
64'h642C766373697200,
64'h3331302D67756265,
64'h642C657669666973,
64'h1B00000021000000,
64'h300000000003040,
64'h72656C6C6F72746E,
64'h6F632D6775626564,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h10002E010000,
64'h800000003000000,
64'h303030303031,
64'h4072657461672D6B,
64'h636F6C6301000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000002,
64'h2E01000008000000,
64'h300000007000000,
64'h400000003000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h30746E69,
64'h6C632C7663736972,
64'h1B0000000D000000,
64'h300000000000030,
64'h3030303030324074,
64'h6E696C6301000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'h100000002000000,
64'h100000099010000,
64'h400000003000000,
64'h7000000CC010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1022E010000,
64'h800000003000000,
64'h300000002000000,
64'h1D01000008000000,
64'h300000000000000,
64'h6568636163003065,
64'h6863616365766973,
64'h756C636E692C6576,
64'h696669731B000000,
64'h1D00000003000000,
64'hBE01000000000000,
64'h300000000000800,
64'h8500000004000000,
64'h300000000040000,
64'h7800000004000000,
64'h300000002000000,
64'hB201000004000000,
64'h300000040000000,
64'h6500000004000000,
64'h300000000000000,
64'h3030303031303240,
64'h72656C6C6F72746E,
64'h6F632D6568636163,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1000002E010000,
64'h800000003000000,
64'h3030303140,
64'h6765722D73736572,
64'h6464612D746F6F62,
64'h1000000A1010000,
64'h3000000,
64'h7375622D656C70,
64'h6D697300636F732D,
64'h6472617970696863,
64'h2C7261622D626375,
64'h1B00000020000000,
64'h300000001000000,
64'hF00000004000000,
64'h300000001000000,
64'h4000000,
64'h300000000636F73,
64'h100000002000000,
64'h200000099010000,
64'h400000003000000,
64'h1000000080,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h30303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'h400000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000073627A,
64'h5F62627A5F61627A,
64'h5F6D7068697A5F69,
64'h65636E6566697A5F,
64'h727363697A626364,
64'h66616D6934367672,
64'h320100002C000000,
64'h300000000000000,
64'h2E01000004000000,
64'h300000001000000,
64'h1D01000004000000,
64'h300000000003933,
64'h76732C7663736972,
64'h140100000B000000,
64'h300000020000000,
64'h901000004000000,
64'h300000001000000,
64'hFE00000004000000,
64'h300000000400000,
64'hF100000004000000,
64'h300000040000000,
64'hE400000004000000,
64'h300000040000000,
64'hD100000004000000,
64'h300000000000000,
64'hB200000004000000,
64'h300000000757063,
64'hA600000004000000,
64'h300000008000000,
64'h9B00000004000000,
64'h300000001000000,
64'h9000000004000000,
64'h300000000400000,
64'h8300000004000000,
64'h300000040000000,
64'h7600000004000000,
64'h300000040000000,
64'h6300000004000000,
64'h300000000766373,
64'h697200306D6F6F62,
64'h2C7261622D626375,
64'h1B00000014000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'h680B000060020000,
64'h10000000,
64'h1100000028000000,
64'hA00B000038000000,
64'hE0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'hE0000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hA00B000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'h680B000060020000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000014000000; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h697200306D6F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h300000000766373; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h6300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h7600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h8300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h9000000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h9B00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'hA600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'h300000000757063; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'hB200000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'hD100000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'hE400000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'hF100000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h300000000400000; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h300000000400000; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'hFE00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'h300000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'h140100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'h76732C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h300000000003933; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'h1D01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h2E01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h320100002C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h66616D6934367672; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h727363697A626364; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h65636E6566697A5F; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h5F6D7068697A5F69; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h30000000073627A; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h3C01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h5101000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h6201000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'h100000069010000; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h72656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h100000073010000; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'hF00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h300000000006374; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h400000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h66697468; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'hA00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h2C6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'h3066697468; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h10000000008; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h900000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h6173696462010000; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'h64656C62; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h300000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h30303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'h1000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h200000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h300000000636F73; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'h4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'hF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'h1B00000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h6D697300636F732D; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h7375622D656C70; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h1000000A1010000; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h6765722D73736572; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h3030303140; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'h1000002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h6F632D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h3030303031303240; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'h6500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'hB201000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'h7800000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'h300000000040000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h8500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'h300000000000800; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'hBE01000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h1D00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h756C636E692C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h6863616365766973; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h6568636163003065; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h1D01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'h1022E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'h7000000CC010000; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h100000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'h6E696C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'h3030303030324074; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h1B0000000D000000; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'h6C632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'h30746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h300000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h10000000002; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h636F6C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h4072657461672D6B; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h303030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h10002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h6F632D6775626564; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h300000000003040; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h1B00000021000000; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h642C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h642C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h1202000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h6761746A; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h10000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'h6F72726501000000; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h6563697665642D72; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h3030303340; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'hE00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'h726F7272652C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h10000000300000; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h3030303030306340; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h7301000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h6C702C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h300000000306369; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h40000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h300000009000000; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h40000000C; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h3000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h1F02000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h3202000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h200000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h7375626D01000000; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h7375626DEB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h200000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'h1002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'hA801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h73756273EB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h50000003D020000; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h4402000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h300000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h5502000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h11002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'h6361632D64007963; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h65732D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h6361632D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h657A69732D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h65732D626C742D64; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h626C742D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h656400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h7079745F65636976; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'h6177647261680065; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h2D636578652D6572; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h696F706B61657262; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h746E756F632D746E; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'h61632D6900657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h737465732D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h737465732D626C74; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'h732D626C742D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h78656E0065707974; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h6572006568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h2C76637369720067; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'h6373697200617369; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h617267706D702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h79746972616C756E; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h702C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h7375746174730073; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h65746E6923007469; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'h65632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h656C646E61687000; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h7365676E617200; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h656D616E2D676572; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h2D65686361630073; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h6163006C6576656C; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h66696E752D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h6966697300646569; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h632300746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h6E690073656D616E; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h7374707572726574; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h65646E657478652D; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h2D67756265640064; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'h7200686361747461; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h78616D2C76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h7469726F6972702D; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h2C76637369720079; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h65746E6900736B63; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h61702D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h746E6900746E6572; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h73747075727265; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34]
wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_53 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_49 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_49
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_49
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_69
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_49( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_49 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_49 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_69 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_39 :
input clock : Clock
input reset : Reset
output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, `1` : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, `0` : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5]}}
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire in_arb_reqs : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}[3]
wire in_arb_vals : UInt<1>[3]
node in_arb_filter_hi = cat(in_arb_vals[2], in_arb_vals[1])
node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_vals[0])
node in_arb_filter_hi_1 = cat(in_arb_vals[2], in_arb_vals[1])
node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_vals[0])
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4)
node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5)
node _in_arb_filter_T_11 = mux(_in_arb_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _in_arb_filter_T_12 = mux(_in_arb_filter_T_9, UInt<6>(0h10), _in_arb_filter_T_11)
node _in_arb_filter_T_13 = mux(_in_arb_filter_T_8, UInt<6>(0h8), _in_arb_filter_T_12)
node _in_arb_filter_T_14 = mux(_in_arb_filter_T_7, UInt<6>(0h4), _in_arb_filter_T_13)
node _in_arb_filter_T_15 = mux(_in_arb_filter_T_6, UInt<6>(0h2), _in_arb_filter_T_14)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<6>(0h1), _in_arb_filter_T_15)
node _in_arb_sel_T = bits(in_arb_filter, 2, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 3)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
node _T_1 = or(_T, in_arb_vals[2])
when _T_1 :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = not(UInt<3>(0h0))
node _mask_T_3 = bits(in_arb_sel, 0, 0)
node _mask_T_4 = bits(in_arb_sel, 1, 1)
node _mask_T_5 = bits(in_arb_sel, 2, 2)
node _mask_T_6 = mux(_mask_T_3, _mask_T, UInt<1>(0h0))
node _mask_T_7 = mux(_mask_T_4, _mask_T_1, UInt<1>(0h0))
node _mask_T_8 = mux(_mask_T_5, _mask_T_2, UInt<1>(0h0))
node _mask_T_9 = or(_mask_T_6, _mask_T_7)
node _mask_T_10 = or(_mask_T_9, _mask_T_8)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_10
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T)
connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1
node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T)
connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T)
connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1
node _in_arb_reqs_0_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_2_T_1 = and(io.req.`0`.bits.vc_sel.`1`[2], _in_arb_reqs_0_1_2_T)
connect in_arb_reqs[0].`1`[2], _in_arb_reqs_0_1_2_T_1
node _in_arb_reqs_0_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_3_T_1 = and(io.req.`0`.bits.vc_sel.`1`[3], _in_arb_reqs_0_1_3_T)
connect in_arb_reqs[0].`1`[3], _in_arb_reqs_0_1_3_T_1
node _in_arb_reqs_0_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_4_T_1 = and(io.req.`0`.bits.vc_sel.`1`[4], _in_arb_reqs_0_1_4_T)
connect in_arb_reqs[0].`1`[4], _in_arb_reqs_0_1_4_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_reqs_0_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_1_T_1 = and(io.req.`0`.bits.vc_sel.`2`[1], _in_arb_reqs_0_2_1_T)
connect in_arb_reqs[0].`2`[1], _in_arb_reqs_0_2_1_T_1
node _in_arb_reqs_0_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_2_T_1 = and(io.req.`0`.bits.vc_sel.`2`[2], _in_arb_reqs_0_2_2_T)
connect in_arb_reqs[0].`2`[2], _in_arb_reqs_0_2_2_T_1
node _in_arb_reqs_0_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_3_T_1 = and(io.req.`0`.bits.vc_sel.`2`[3], _in_arb_reqs_0_2_3_T)
connect in_arb_reqs[0].`2`[3], _in_arb_reqs_0_2_3_T_1
node _in_arb_reqs_0_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_4_T_1 = and(io.req.`0`.bits.vc_sel.`2`[4], _in_arb_reqs_0_2_4_T)
connect in_arb_reqs[0].`2`[4], _in_arb_reqs_0_2_4_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4])
node _in_arb_vals_0_T_4 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1])
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`1`[2])
node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`1`[3])
node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`1`[4])
node _in_arb_vals_0_T_8 = or(in_arb_reqs[0].`2`[0], in_arb_reqs[0].`2`[1])
node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`2`[2])
node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`2`[3])
node _in_arb_vals_0_T_11 = or(_in_arb_vals_0_T_10, in_arb_reqs[0].`2`[4])
node _in_arb_vals_0_T_12 = or(_in_arb_vals_0_T_3, _in_arb_vals_0_T_7)
node _in_arb_vals_0_T_13 = or(_in_arb_vals_0_T_12, _in_arb_vals_0_T_11)
node _in_arb_vals_0_T_14 = and(io.req.`0`.valid, _in_arb_vals_0_T_13)
connect in_arb_vals[0], _in_arb_vals_0_T_14
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T)
connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1
node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T)
connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T)
connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1
node _in_arb_reqs_1_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_2_T_1 = and(io.req.`1`.bits.vc_sel.`1`[2], _in_arb_reqs_1_1_2_T)
connect in_arb_reqs[1].`1`[2], _in_arb_reqs_1_1_2_T_1
node _in_arb_reqs_1_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_3_T_1 = and(io.req.`1`.bits.vc_sel.`1`[3], _in_arb_reqs_1_1_3_T)
connect in_arb_reqs[1].`1`[3], _in_arb_reqs_1_1_3_T_1
node _in_arb_reqs_1_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_4_T_1 = and(io.req.`1`.bits.vc_sel.`1`[4], _in_arb_reqs_1_1_4_T)
connect in_arb_reqs[1].`1`[4], _in_arb_reqs_1_1_4_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_reqs_1_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_1_T_1 = and(io.req.`1`.bits.vc_sel.`2`[1], _in_arb_reqs_1_2_1_T)
connect in_arb_reqs[1].`2`[1], _in_arb_reqs_1_2_1_T_1
node _in_arb_reqs_1_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_2_T_1 = and(io.req.`1`.bits.vc_sel.`2`[2], _in_arb_reqs_1_2_2_T)
connect in_arb_reqs[1].`2`[2], _in_arb_reqs_1_2_2_T_1
node _in_arb_reqs_1_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_3_T_1 = and(io.req.`1`.bits.vc_sel.`2`[3], _in_arb_reqs_1_2_3_T)
connect in_arb_reqs[1].`2`[3], _in_arb_reqs_1_2_3_T_1
node _in_arb_reqs_1_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_4_T_1 = and(io.req.`1`.bits.vc_sel.`2`[4], _in_arb_reqs_1_2_4_T)
connect in_arb_reqs[1].`2`[4], _in_arb_reqs_1_2_4_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4])
node _in_arb_vals_1_T_4 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1])
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`1`[2])
node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`1`[3])
node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`1`[4])
node _in_arb_vals_1_T_8 = or(in_arb_reqs[1].`2`[0], in_arb_reqs[1].`2`[1])
node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`2`[2])
node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`2`[3])
node _in_arb_vals_1_T_11 = or(_in_arb_vals_1_T_10, in_arb_reqs[1].`2`[4])
node _in_arb_vals_1_T_12 = or(_in_arb_vals_1_T_3, _in_arb_vals_1_T_7)
node _in_arb_vals_1_T_13 = or(_in_arb_vals_1_T_12, _in_arb_vals_1_T_11)
node _in_arb_vals_1_T_14 = and(io.req.`1`.valid, _in_arb_vals_1_T_13)
connect in_arb_vals[1], _in_arb_vals_1_T_14
node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T)
connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1
node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T)
connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1
node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T)
connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1
node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T)
connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1
node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T)
connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1
node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T)
connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1
node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T)
connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1
node _in_arb_reqs_2_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_2_T_1 = and(io.req.`2`.bits.vc_sel.`1`[2], _in_arb_reqs_2_1_2_T)
connect in_arb_reqs[2].`1`[2], _in_arb_reqs_2_1_2_T_1
node _in_arb_reqs_2_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_3_T_1 = and(io.req.`2`.bits.vc_sel.`1`[3], _in_arb_reqs_2_1_3_T)
connect in_arb_reqs[2].`1`[3], _in_arb_reqs_2_1_3_T_1
node _in_arb_reqs_2_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_4_T_1 = and(io.req.`2`.bits.vc_sel.`1`[4], _in_arb_reqs_2_1_4_T)
connect in_arb_reqs[2].`1`[4], _in_arb_reqs_2_1_4_T_1
node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T)
connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1
node _in_arb_reqs_2_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_1_T_1 = and(io.req.`2`.bits.vc_sel.`2`[1], _in_arb_reqs_2_2_1_T)
connect in_arb_reqs[2].`2`[1], _in_arb_reqs_2_2_1_T_1
node _in_arb_reqs_2_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_2_T_1 = and(io.req.`2`.bits.vc_sel.`2`[2], _in_arb_reqs_2_2_2_T)
connect in_arb_reqs[2].`2`[2], _in_arb_reqs_2_2_2_T_1
node _in_arb_reqs_2_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_3_T_1 = and(io.req.`2`.bits.vc_sel.`2`[3], _in_arb_reqs_2_2_3_T)
connect in_arb_reqs[2].`2`[3], _in_arb_reqs_2_2_3_T_1
node _in_arb_reqs_2_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_4_T_1 = and(io.req.`2`.bits.vc_sel.`2`[4], _in_arb_reqs_2_2_4_T)
connect in_arb_reqs[2].`2`[4], _in_arb_reqs_2_2_4_T_1
node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1])
node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2])
node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3])
node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4])
node _in_arb_vals_2_T_4 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1])
node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`1`[2])
node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`1`[3])
node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`1`[4])
node _in_arb_vals_2_T_8 = or(in_arb_reqs[2].`2`[0], in_arb_reqs[2].`2`[1])
node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`2`[2])
node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`2`[3])
node _in_arb_vals_2_T_11 = or(_in_arb_vals_2_T_10, in_arb_reqs[2].`2`[4])
node _in_arb_vals_2_T_12 = or(_in_arb_vals_2_T_3, _in_arb_vals_2_T_7)
node _in_arb_vals_2_T_13 = or(_in_arb_vals_2_T_12, _in_arb_vals_2_T_11)
node _in_arb_vals_2_T_14 = and(io.req.`2`.valid, _in_arb_vals_2_T_13)
connect in_arb_vals[2], _in_arb_vals_2_T_14
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h0)
wire in_alloc : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
node _in_flow_T_2 = bits(in_arb_sel, 2, 2)
wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _in_flow_T_3 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_4 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_5 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_6 = or(_in_flow_T_3, _in_flow_T_4)
node _in_flow_T_7 = or(_in_flow_T_6, _in_flow_T_5)
wire _in_flow_WIRE : UInt<2>
connect _in_flow_WIRE, _in_flow_T_7
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_10 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_11 = or(_in_flow_T_8, _in_flow_T_9)
node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_10)
wire _in_flow_WIRE_1 : UInt<5>
connect _in_flow_WIRE_1, _in_flow_T_12
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_13 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_14 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_15 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_16 = or(_in_flow_T_13, _in_flow_T_14)
node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_15)
wire _in_flow_WIRE_2 : UInt<2>
connect _in_flow_WIRE_2, _in_flow_T_17
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_21 = or(_in_flow_T_18, _in_flow_T_19)
node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_20)
wire _in_flow_WIRE_3 : UInt<5>
connect _in_flow_WIRE_3, _in_flow_T_22
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_26 = or(_in_flow_T_23, _in_flow_T_24)
node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_25)
wire _in_flow_WIRE_4 : UInt<3>
connect _in_flow_WIRE_4, _in_flow_T_27
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_T_3 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_4 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_5 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_6 = or(_in_vc_T_3, _in_vc_T_4)
node _in_vc_T_7 = or(_in_vc_T_6, _in_vc_T_5)
wire in_vc : UInt<3>
connect in_vc, _in_vc_T_7
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2)
wire in_vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
wire _in_vc_sel_WIRE : UInt<1>[5]
node _in_vc_sel_T_3 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_4 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_5 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_6 = or(_in_vc_sel_T_3, _in_vc_sel_T_4)
node _in_vc_sel_T_7 = or(_in_vc_sel_T_6, _in_vc_sel_T_5)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_7
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_10 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_11 = or(_in_vc_sel_T_8, _in_vc_sel_T_9)
node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_10)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_12
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_13 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_14 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_15 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_16 = or(_in_vc_sel_T_13, _in_vc_sel_T_14)
node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_15)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_17
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_21 = or(_in_vc_sel_T_18, _in_vc_sel_T_19)
node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_20)
wire _in_vc_sel_WIRE_4 : UInt<1>
connect _in_vc_sel_WIRE_4, _in_vc_sel_T_22
connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4
node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_26 = or(_in_vc_sel_T_23, _in_vc_sel_T_24)
node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_25)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_27
connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_6 : UInt<1>[5]
node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_31 = or(_in_vc_sel_T_28, _in_vc_sel_T_29)
node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_30)
wire _in_vc_sel_WIRE_7 : UInt<1>
connect _in_vc_sel_WIRE_7, _in_vc_sel_T_32
connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7
node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_36 = or(_in_vc_sel_T_33, _in_vc_sel_T_34)
node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_35)
wire _in_vc_sel_WIRE_8 : UInt<1>
connect _in_vc_sel_WIRE_8, _in_vc_sel_T_37
connect _in_vc_sel_WIRE_6[1], _in_vc_sel_WIRE_8
node _in_vc_sel_T_38 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_39 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_40 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_41 = or(_in_vc_sel_T_38, _in_vc_sel_T_39)
node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_40)
wire _in_vc_sel_WIRE_9 : UInt<1>
connect _in_vc_sel_WIRE_9, _in_vc_sel_T_42
connect _in_vc_sel_WIRE_6[2], _in_vc_sel_WIRE_9
node _in_vc_sel_T_43 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[3], UInt<1>(0h0))
node _in_vc_sel_T_44 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[3], UInt<1>(0h0))
node _in_vc_sel_T_45 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[3], UInt<1>(0h0))
node _in_vc_sel_T_46 = or(_in_vc_sel_T_43, _in_vc_sel_T_44)
node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_45)
wire _in_vc_sel_WIRE_10 : UInt<1>
connect _in_vc_sel_WIRE_10, _in_vc_sel_T_47
connect _in_vc_sel_WIRE_6[3], _in_vc_sel_WIRE_10
node _in_vc_sel_T_48 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[4], UInt<1>(0h0))
node _in_vc_sel_T_49 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[4], UInt<1>(0h0))
node _in_vc_sel_T_50 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[4], UInt<1>(0h0))
node _in_vc_sel_T_51 = or(_in_vc_sel_T_48, _in_vc_sel_T_49)
node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_50)
wire _in_vc_sel_WIRE_11 : UInt<1>
connect _in_vc_sel_WIRE_11, _in_vc_sel_T_52
connect _in_vc_sel_WIRE_6[4], _in_vc_sel_WIRE_11
connect in_vc_sel.`1`, _in_vc_sel_WIRE_6
wire _in_vc_sel_WIRE_12 : UInt<1>[5]
node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_56 = or(_in_vc_sel_T_53, _in_vc_sel_T_54)
node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_55)
wire _in_vc_sel_WIRE_13 : UInt<1>
connect _in_vc_sel_WIRE_13, _in_vc_sel_T_57
connect _in_vc_sel_WIRE_12[0], _in_vc_sel_WIRE_13
node _in_vc_sel_T_58 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_59 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_60 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_61 = or(_in_vc_sel_T_58, _in_vc_sel_T_59)
node _in_vc_sel_T_62 = or(_in_vc_sel_T_61, _in_vc_sel_T_60)
wire _in_vc_sel_WIRE_14 : UInt<1>
connect _in_vc_sel_WIRE_14, _in_vc_sel_T_62
connect _in_vc_sel_WIRE_12[1], _in_vc_sel_WIRE_14
node _in_vc_sel_T_63 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_64 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_65 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_66 = or(_in_vc_sel_T_63, _in_vc_sel_T_64)
node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_65)
wire _in_vc_sel_WIRE_15 : UInt<1>
connect _in_vc_sel_WIRE_15, _in_vc_sel_T_67
connect _in_vc_sel_WIRE_12[2], _in_vc_sel_WIRE_15
node _in_vc_sel_T_68 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[3], UInt<1>(0h0))
node _in_vc_sel_T_69 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[3], UInt<1>(0h0))
node _in_vc_sel_T_70 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[3], UInt<1>(0h0))
node _in_vc_sel_T_71 = or(_in_vc_sel_T_68, _in_vc_sel_T_69)
node _in_vc_sel_T_72 = or(_in_vc_sel_T_71, _in_vc_sel_T_70)
wire _in_vc_sel_WIRE_16 : UInt<1>
connect _in_vc_sel_WIRE_16, _in_vc_sel_T_72
connect _in_vc_sel_WIRE_12[3], _in_vc_sel_WIRE_16
node _in_vc_sel_T_73 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[4], UInt<1>(0h0))
node _in_vc_sel_T_74 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[4], UInt<1>(0h0))
node _in_vc_sel_T_75 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[4], UInt<1>(0h0))
node _in_vc_sel_T_76 = or(_in_vc_sel_T_73, _in_vc_sel_T_74)
node _in_vc_sel_T_77 = or(_in_vc_sel_T_76, _in_vc_sel_T_75)
wire _in_vc_sel_WIRE_17 : UInt<1>
connect _in_vc_sel_WIRE_17, _in_vc_sel_T_77
connect _in_vc_sel_WIRE_12[4], _in_vc_sel_WIRE_17
connect in_vc_sel.`2`, _in_vc_sel_WIRE_12
node _T_2 = or(in_arb_vals[0], in_arb_vals[1])
node _T_3 = or(_T_2, in_arb_vals[2])
node hi = bits(in_arb_sel, 2, 2)
node lo = bits(in_arb_sel, 1, 0)
node _T_4 = orr(hi)
node _T_5 = or(hi, lo)
node _T_6 = bits(_T_5, 1, 1)
node _T_7 = cat(_T_4, _T_6)
node _T_8 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_9 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_10 = and(io.req.`2`.ready, io.req.`2`.valid)
node _T_11 = or(_T_8, _T_9)
node _T_12 = or(_T_11, _T_10)
node lo_1 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0])
node hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3])
node hi_1 = cat(hi_hi, in_vc_sel.`0`[2])
node _T_13 = cat(hi_1, lo_1)
node lo_2 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0])
node hi_hi_1 = cat(in_vc_sel.`1`[4], in_vc_sel.`1`[3])
node hi_2 = cat(hi_hi_1, in_vc_sel.`1`[2])
node _T_14 = cat(hi_2, lo_2)
node lo_3 = cat(in_vc_sel.`2`[1], in_vc_sel.`2`[0])
node hi_hi_2 = cat(in_vc_sel.`2`[4], in_vc_sel.`2`[3])
node hi_3 = cat(hi_hi_2, in_vc_sel.`2`[2])
node _T_15 = cat(hi_3, lo_3)
node hi_4 = cat(_T_15, _T_14)
node _T_16 = cat(hi_4, _T_13)
regreset mask_1 : UInt<15>, clock, reset, UInt<15>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_16, _full_T)
node full = cat(_T_16, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = bits(full, 16, 16)
node _oh_T_17 = bits(full, 17, 17)
node _oh_T_18 = bits(full, 18, 18)
node _oh_T_19 = bits(full, 19, 19)
node _oh_T_20 = bits(full, 20, 20)
node _oh_T_21 = bits(full, 21, 21)
node _oh_T_22 = bits(full, 22, 22)
node _oh_T_23 = bits(full, 23, 23)
node _oh_T_24 = bits(full, 24, 24)
node _oh_T_25 = bits(full, 25, 25)
node _oh_T_26 = bits(full, 26, 26)
node _oh_T_27 = bits(full, 27, 27)
node _oh_T_28 = bits(full, 28, 28)
node _oh_T_29 = bits(full, 29, 29)
node _oh_T_30 = mux(_oh_T_29, UInt<30>(0h20000000), UInt<30>(0h0))
node _oh_T_31 = mux(_oh_T_28, UInt<30>(0h10000000), _oh_T_30)
node _oh_T_32 = mux(_oh_T_27, UInt<30>(0h8000000), _oh_T_31)
node _oh_T_33 = mux(_oh_T_26, UInt<30>(0h4000000), _oh_T_32)
node _oh_T_34 = mux(_oh_T_25, UInt<30>(0h2000000), _oh_T_33)
node _oh_T_35 = mux(_oh_T_24, UInt<30>(0h1000000), _oh_T_34)
node _oh_T_36 = mux(_oh_T_23, UInt<30>(0h800000), _oh_T_35)
node _oh_T_37 = mux(_oh_T_22, UInt<30>(0h400000), _oh_T_36)
node _oh_T_38 = mux(_oh_T_21, UInt<30>(0h200000), _oh_T_37)
node _oh_T_39 = mux(_oh_T_20, UInt<30>(0h100000), _oh_T_38)
node _oh_T_40 = mux(_oh_T_19, UInt<30>(0h80000), _oh_T_39)
node _oh_T_41 = mux(_oh_T_18, UInt<30>(0h40000), _oh_T_40)
node _oh_T_42 = mux(_oh_T_17, UInt<30>(0h20000), _oh_T_41)
node _oh_T_43 = mux(_oh_T_16, UInt<30>(0h10000), _oh_T_42)
node _oh_T_44 = mux(_oh_T_15, UInt<30>(0h8000), _oh_T_43)
node _oh_T_45 = mux(_oh_T_14, UInt<30>(0h4000), _oh_T_44)
node _oh_T_46 = mux(_oh_T_13, UInt<30>(0h2000), _oh_T_45)
node _oh_T_47 = mux(_oh_T_12, UInt<30>(0h1000), _oh_T_46)
node _oh_T_48 = mux(_oh_T_11, UInt<30>(0h800), _oh_T_47)
node _oh_T_49 = mux(_oh_T_10, UInt<30>(0h400), _oh_T_48)
node _oh_T_50 = mux(_oh_T_9, UInt<30>(0h200), _oh_T_49)
node _oh_T_51 = mux(_oh_T_8, UInt<30>(0h100), _oh_T_50)
node _oh_T_52 = mux(_oh_T_7, UInt<30>(0h80), _oh_T_51)
node _oh_T_53 = mux(_oh_T_6, UInt<30>(0h40), _oh_T_52)
node _oh_T_54 = mux(_oh_T_5, UInt<30>(0h20), _oh_T_53)
node _oh_T_55 = mux(_oh_T_4, UInt<30>(0h10), _oh_T_54)
node _oh_T_56 = mux(_oh_T_3, UInt<30>(0h8), _oh_T_55)
node _oh_T_57 = mux(_oh_T_2, UInt<30>(0h4), _oh_T_56)
node _oh_T_58 = mux(_oh_T_1, UInt<30>(0h2), _oh_T_57)
node oh = mux(_oh_T, UInt<30>(0h1), _oh_T_58)
node _sel_T = bits(oh, 14, 0)
node _sel_T_1 = shr(oh, 15)
node sel = or(_sel_T, _sel_T_1)
when _T_12 :
node _mask_T_11 = bits(sel, 0, 0)
node _mask_T_12 = not(UInt<1>(0h0))
node _mask_T_13 = bits(sel, 1, 1)
node _mask_T_14 = not(UInt<2>(0h0))
node _mask_T_15 = bits(sel, 2, 2)
node _mask_T_16 = not(UInt<3>(0h0))
node _mask_T_17 = bits(sel, 3, 3)
node _mask_T_18 = not(UInt<4>(0h0))
node _mask_T_19 = bits(sel, 4, 4)
node _mask_T_20 = not(UInt<5>(0h0))
node _mask_T_21 = bits(sel, 5, 5)
node _mask_T_22 = not(UInt<6>(0h0))
node _mask_T_23 = bits(sel, 6, 6)
node _mask_T_24 = not(UInt<7>(0h0))
node _mask_T_25 = bits(sel, 7, 7)
node _mask_T_26 = not(UInt<8>(0h0))
node _mask_T_27 = bits(sel, 8, 8)
node _mask_T_28 = not(UInt<9>(0h0))
node _mask_T_29 = bits(sel, 9, 9)
node _mask_T_30 = not(UInt<10>(0h0))
node _mask_T_31 = bits(sel, 10, 10)
node _mask_T_32 = not(UInt<11>(0h0))
node _mask_T_33 = bits(sel, 11, 11)
node _mask_T_34 = not(UInt<12>(0h0))
node _mask_T_35 = bits(sel, 12, 12)
node _mask_T_36 = not(UInt<13>(0h0))
node _mask_T_37 = bits(sel, 13, 13)
node _mask_T_38 = not(UInt<14>(0h0))
node _mask_T_39 = bits(sel, 14, 14)
node _mask_T_40 = not(UInt<15>(0h0))
node _mask_T_41 = mux(_mask_T_39, _mask_T_40, UInt<1>(0h0))
node _mask_T_42 = mux(_mask_T_37, _mask_T_38, _mask_T_41)
node _mask_T_43 = mux(_mask_T_35, _mask_T_36, _mask_T_42)
node _mask_T_44 = mux(_mask_T_33, _mask_T_34, _mask_T_43)
node _mask_T_45 = mux(_mask_T_31, _mask_T_32, _mask_T_44)
node _mask_T_46 = mux(_mask_T_29, _mask_T_30, _mask_T_45)
node _mask_T_47 = mux(_mask_T_27, _mask_T_28, _mask_T_46)
node _mask_T_48 = mux(_mask_T_25, _mask_T_26, _mask_T_47)
node _mask_T_49 = mux(_mask_T_23, _mask_T_24, _mask_T_48)
node _mask_T_50 = mux(_mask_T_21, _mask_T_22, _mask_T_49)
node _mask_T_51 = mux(_mask_T_19, _mask_T_20, _mask_T_50)
node _mask_T_52 = mux(_mask_T_17, _mask_T_18, _mask_T_51)
node _mask_T_53 = mux(_mask_T_15, _mask_T_16, _mask_T_52)
node _mask_T_54 = mux(_mask_T_13, _mask_T_14, _mask_T_53)
node _mask_T_55 = mux(_mask_T_11, _mask_T_12, _mask_T_54)
connect mask_1, _mask_T_55
wire _WIRE : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
wire _WIRE_1 : UInt<15>
connect _WIRE_1, sel
node _T_17 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_17
node _T_18 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_18
node _T_19 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_19
node _T_20 = bits(_WIRE_1, 3, 3)
connect _WIRE.`0`[3], _T_20
node _T_21 = bits(_WIRE_1, 4, 4)
connect _WIRE.`0`[4], _T_21
node _T_22 = bits(_WIRE_1, 5, 5)
connect _WIRE.`1`[0], _T_22
node _T_23 = bits(_WIRE_1, 6, 6)
connect _WIRE.`1`[1], _T_23
node _T_24 = bits(_WIRE_1, 7, 7)
connect _WIRE.`1`[2], _T_24
node _T_25 = bits(_WIRE_1, 8, 8)
connect _WIRE.`1`[3], _T_25
node _T_26 = bits(_WIRE_1, 9, 9)
connect _WIRE.`1`[4], _T_26
node _T_27 = bits(_WIRE_1, 10, 10)
connect _WIRE.`2`[0], _T_27
node _T_28 = bits(_WIRE_1, 11, 11)
connect _WIRE.`2`[1], _T_28
node _T_29 = bits(_WIRE_1, 12, 12)
connect _WIRE.`2`[2], _T_29
node _T_30 = bits(_WIRE_1, 13, 13)
connect _WIRE.`2`[3], _T_30
node _T_31 = bits(_WIRE_1, 14, 14)
connect _WIRE.`2`[4], _T_31
wire _WIRE_2 : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`0`[3], UInt<1>(0h0)
connect _WIRE_2.`0`[4], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`1`[1], UInt<1>(0h0)
connect _WIRE_2.`1`[2], UInt<1>(0h0)
connect _WIRE_2.`1`[3], UInt<1>(0h0)
connect _WIRE_2.`1`[4], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
connect _WIRE_2.`2`[1], UInt<1>(0h0)
connect _WIRE_2.`2`[2], UInt<1>(0h0)
connect _WIRE_2.`2`[3], UInt<1>(0h0)
connect _WIRE_2.`2`[4], UInt<1>(0h0)
node _T_32 = mux(_T_3, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_32.`0`
connect in_alloc.`1`, _T_32.`1`
connect in_alloc.`2`, _T_32.`2`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`0`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`0`.vc_sel.`1`[3], in_alloc.`1`[3]
connect io.resp.`0`.vc_sel.`1`[4], in_alloc.`1`[4]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`0`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`0`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`0`.vc_sel.`2`[3], in_alloc.`2`[3]
connect io.resp.`0`.vc_sel.`2`[4], in_alloc.`2`[4]
node lo_4 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0])
node hi_hi_3 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3])
node hi_5 = cat(hi_hi_3, io.resp.`0`.vc_sel.`0`[2])
node _T_33 = cat(hi_5, lo_4)
node lo_5 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0])
node hi_hi_4 = cat(io.resp.`0`.vc_sel.`1`[4], io.resp.`0`.vc_sel.`1`[3])
node hi_6 = cat(hi_hi_4, io.resp.`0`.vc_sel.`1`[2])
node _T_34 = cat(hi_6, lo_5)
node lo_6 = cat(io.resp.`0`.vc_sel.`2`[1], io.resp.`0`.vc_sel.`2`[0])
node hi_hi_5 = cat(io.resp.`0`.vc_sel.`2`[4], io.resp.`0`.vc_sel.`2`[3])
node hi_7 = cat(hi_hi_5, io.resp.`0`.vc_sel.`2`[2])
node _T_35 = cat(hi_7, lo_6)
node hi_8 = cat(_T_35, _T_34)
node _T_36 = cat(hi_8, _T_33)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_36, 4, 4)
node _T_42 = bits(_T_36, 5, 5)
node _T_43 = bits(_T_36, 6, 6)
node _T_44 = bits(_T_36, 7, 7)
node _T_45 = bits(_T_36, 8, 8)
node _T_46 = bits(_T_36, 9, 9)
node _T_47 = bits(_T_36, 10, 10)
node _T_48 = bits(_T_36, 11, 11)
node _T_49 = bits(_T_36, 12, 12)
node _T_50 = bits(_T_36, 13, 13)
node _T_51 = bits(_T_36, 14, 14)
node _T_52 = add(_T_38, _T_39)
node _T_53 = bits(_T_52, 1, 0)
node _T_54 = add(_T_37, _T_53)
node _T_55 = bits(_T_54, 1, 0)
node _T_56 = add(_T_40, _T_41)
node _T_57 = bits(_T_56, 1, 0)
node _T_58 = add(_T_42, _T_43)
node _T_59 = bits(_T_58, 1, 0)
node _T_60 = add(_T_57, _T_59)
node _T_61 = bits(_T_60, 2, 0)
node _T_62 = add(_T_55, _T_61)
node _T_63 = bits(_T_62, 2, 0)
node _T_64 = add(_T_44, _T_45)
node _T_65 = bits(_T_64, 1, 0)
node _T_66 = add(_T_46, _T_47)
node _T_67 = bits(_T_66, 1, 0)
node _T_68 = add(_T_65, _T_67)
node _T_69 = bits(_T_68, 2, 0)
node _T_70 = add(_T_48, _T_49)
node _T_71 = bits(_T_70, 1, 0)
node _T_72 = add(_T_50, _T_51)
node _T_73 = bits(_T_72, 1, 0)
node _T_74 = add(_T_71, _T_73)
node _T_75 = bits(_T_74, 2, 0)
node _T_76 = add(_T_69, _T_75)
node _T_77 = bits(_T_76, 3, 0)
node _T_78 = add(_T_63, _T_77)
node _T_79 = bits(_T_78, 3, 0)
node _T_80 = leq(_T_79, UInt<1>(0h1))
node _T_81 = asUInt(reset)
node _T_82 = eq(_T_81, UInt<1>(0h0))
when _T_82 :
node _T_83 = eq(_T_80, UInt<1>(0h0))
when _T_83 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_80, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`1`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`1`.vc_sel.`1`[3], in_alloc.`1`[3]
connect io.resp.`1`.vc_sel.`1`[4], in_alloc.`1`[4]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`1`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`1`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`1`.vc_sel.`2`[3], in_alloc.`2`[3]
connect io.resp.`1`.vc_sel.`2`[4], in_alloc.`2`[4]
node lo_7 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0])
node hi_hi_6 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3])
node hi_9 = cat(hi_hi_6, io.resp.`1`.vc_sel.`0`[2])
node _T_84 = cat(hi_9, lo_7)
node lo_8 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0])
node hi_hi_7 = cat(io.resp.`1`.vc_sel.`1`[4], io.resp.`1`.vc_sel.`1`[3])
node hi_10 = cat(hi_hi_7, io.resp.`1`.vc_sel.`1`[2])
node _T_85 = cat(hi_10, lo_8)
node lo_9 = cat(io.resp.`1`.vc_sel.`2`[1], io.resp.`1`.vc_sel.`2`[0])
node hi_hi_8 = cat(io.resp.`1`.vc_sel.`2`[4], io.resp.`1`.vc_sel.`2`[3])
node hi_11 = cat(hi_hi_8, io.resp.`1`.vc_sel.`2`[2])
node _T_86 = cat(hi_11, lo_9)
node hi_12 = cat(_T_86, _T_85)
node _T_87 = cat(hi_12, _T_84)
node _T_88 = bits(_T_87, 0, 0)
node _T_89 = bits(_T_87, 1, 1)
node _T_90 = bits(_T_87, 2, 2)
node _T_91 = bits(_T_87, 3, 3)
node _T_92 = bits(_T_87, 4, 4)
node _T_93 = bits(_T_87, 5, 5)
node _T_94 = bits(_T_87, 6, 6)
node _T_95 = bits(_T_87, 7, 7)
node _T_96 = bits(_T_87, 8, 8)
node _T_97 = bits(_T_87, 9, 9)
node _T_98 = bits(_T_87, 10, 10)
node _T_99 = bits(_T_87, 11, 11)
node _T_100 = bits(_T_87, 12, 12)
node _T_101 = bits(_T_87, 13, 13)
node _T_102 = bits(_T_87, 14, 14)
node _T_103 = add(_T_89, _T_90)
node _T_104 = bits(_T_103, 1, 0)
node _T_105 = add(_T_88, _T_104)
node _T_106 = bits(_T_105, 1, 0)
node _T_107 = add(_T_91, _T_92)
node _T_108 = bits(_T_107, 1, 0)
node _T_109 = add(_T_93, _T_94)
node _T_110 = bits(_T_109, 1, 0)
node _T_111 = add(_T_108, _T_110)
node _T_112 = bits(_T_111, 2, 0)
node _T_113 = add(_T_106, _T_112)
node _T_114 = bits(_T_113, 2, 0)
node _T_115 = add(_T_95, _T_96)
node _T_116 = bits(_T_115, 1, 0)
node _T_117 = add(_T_97, _T_98)
node _T_118 = bits(_T_117, 1, 0)
node _T_119 = add(_T_116, _T_118)
node _T_120 = bits(_T_119, 2, 0)
node _T_121 = add(_T_99, _T_100)
node _T_122 = bits(_T_121, 1, 0)
node _T_123 = add(_T_101, _T_102)
node _T_124 = bits(_T_123, 1, 0)
node _T_125 = add(_T_122, _T_124)
node _T_126 = bits(_T_125, 2, 0)
node _T_127 = add(_T_120, _T_126)
node _T_128 = bits(_T_127, 3, 0)
node _T_129 = add(_T_114, _T_128)
node _T_130 = bits(_T_129, 3, 0)
node _T_131 = leq(_T_130, UInt<1>(0h1))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _io_req_2_ready_T = bits(in_arb_sel, 2, 2)
connect io.req.`2`.ready, _io_req_2_ready_T
connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`2`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`2`.vc_sel.`1`[3], in_alloc.`1`[3]
connect io.resp.`2`.vc_sel.`1`[4], in_alloc.`1`[4]
connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`2`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`2`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`2`.vc_sel.`2`[3], in_alloc.`2`[3]
connect io.resp.`2`.vc_sel.`2`[4], in_alloc.`2`[4]
node lo_10 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0])
node hi_hi_9 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3])
node hi_13 = cat(hi_hi_9, io.resp.`2`.vc_sel.`0`[2])
node _T_135 = cat(hi_13, lo_10)
node lo_11 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0])
node hi_hi_10 = cat(io.resp.`2`.vc_sel.`1`[4], io.resp.`2`.vc_sel.`1`[3])
node hi_14 = cat(hi_hi_10, io.resp.`2`.vc_sel.`1`[2])
node _T_136 = cat(hi_14, lo_11)
node lo_12 = cat(io.resp.`2`.vc_sel.`2`[1], io.resp.`2`.vc_sel.`2`[0])
node hi_hi_11 = cat(io.resp.`2`.vc_sel.`2`[4], io.resp.`2`.vc_sel.`2`[3])
node hi_15 = cat(hi_hi_11, io.resp.`2`.vc_sel.`2`[2])
node _T_137 = cat(hi_15, lo_12)
node hi_16 = cat(_T_137, _T_136)
node _T_138 = cat(hi_16, _T_135)
node _T_139 = bits(_T_138, 0, 0)
node _T_140 = bits(_T_138, 1, 1)
node _T_141 = bits(_T_138, 2, 2)
node _T_142 = bits(_T_138, 3, 3)
node _T_143 = bits(_T_138, 4, 4)
node _T_144 = bits(_T_138, 5, 5)
node _T_145 = bits(_T_138, 6, 6)
node _T_146 = bits(_T_138, 7, 7)
node _T_147 = bits(_T_138, 8, 8)
node _T_148 = bits(_T_138, 9, 9)
node _T_149 = bits(_T_138, 10, 10)
node _T_150 = bits(_T_138, 11, 11)
node _T_151 = bits(_T_138, 12, 12)
node _T_152 = bits(_T_138, 13, 13)
node _T_153 = bits(_T_138, 14, 14)
node _T_154 = add(_T_140, _T_141)
node _T_155 = bits(_T_154, 1, 0)
node _T_156 = add(_T_139, _T_155)
node _T_157 = bits(_T_156, 1, 0)
node _T_158 = add(_T_142, _T_143)
node _T_159 = bits(_T_158, 1, 0)
node _T_160 = add(_T_144, _T_145)
node _T_161 = bits(_T_160, 1, 0)
node _T_162 = add(_T_159, _T_161)
node _T_163 = bits(_T_162, 2, 0)
node _T_164 = add(_T_157, _T_163)
node _T_165 = bits(_T_164, 2, 0)
node _T_166 = add(_T_146, _T_147)
node _T_167 = bits(_T_166, 1, 0)
node _T_168 = add(_T_148, _T_149)
node _T_169 = bits(_T_168, 1, 0)
node _T_170 = add(_T_167, _T_169)
node _T_171 = bits(_T_170, 2, 0)
node _T_172 = add(_T_150, _T_151)
node _T_173 = bits(_T_172, 1, 0)
node _T_174 = add(_T_152, _T_153)
node _T_175 = bits(_T_174, 1, 0)
node _T_176 = add(_T_173, _T_175)
node _T_177 = bits(_T_176, 2, 0)
node _T_178 = add(_T_171, _T_177)
node _T_179 = bits(_T_178, 3, 0)
node _T_180 = add(_T_165, _T_179)
node _T_181 = bits(_T_180, 3, 0)
node _T_182 = leq(_T_181, UInt<1>(0h1))
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(_T_182, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2
assert(clock, _T_182, UInt<1>(0h1), "") : assert_2
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3]
connect io.out_allocs.`0`[3].flow, in_flow
connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4]
connect io.out_allocs.`0`[4].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1]
connect io.out_allocs.`1`[1].flow, in_flow
connect io.out_allocs.`1`[2].alloc, in_alloc.`1`[2]
connect io.out_allocs.`1`[2].flow, in_flow
connect io.out_allocs.`1`[3].alloc, in_alloc.`1`[3]
connect io.out_allocs.`1`[3].flow, in_flow
connect io.out_allocs.`1`[4].alloc, in_alloc.`1`[4]
connect io.out_allocs.`1`[4].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow
connect io.out_allocs.`2`[1].alloc, in_alloc.`2`[1]
connect io.out_allocs.`2`[1].flow, in_flow
connect io.out_allocs.`2`[2].alloc, in_alloc.`2`[2]
connect io.out_allocs.`2`[2].flow, in_flow
connect io.out_allocs.`2`[3].alloc, in_alloc.`2`[3]
connect io.out_allocs.`2`[3].flow, in_flow
connect io.out_allocs.`2`[4].alloc, in_alloc.`2`[4]
connect io.out_allocs.`2`[4].flow, in_flow | module RotatingSingleVCAllocator_39( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_2_ready, // @[VCAllocator.scala:49:14]
input io_req_2_valid, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_channel_status_2_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [2:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : in_arb_vals_1 ? 6'h10 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71]
wire [2:0] in_arb_sel = in_arb_filter[2:0] | in_arb_filter[5:3]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2; // @[package.scala:81:59]
wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & in_arb_reqs_0_1_1; // @[SingleVCAllocator.scala:28:61, :32:39]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_4 = io_req_1_bits_vc_sel_2_4 & ~io_channel_status_2_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_4 | in_arb_reqs_1_2_4); // @[package.scala:81:59]
wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_2 = io_req_2_valid & in_arb_reqs_2_1_1; // @[SingleVCAllocator.scala:28:61, :32:39]
wire _in_vc_sel_T_24 = in_arb_sel[1] & in_arb_reqs_1_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_37 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_74 = in_arb_sel[1] & in_arb_reqs_1_2_4; // @[Mux.scala:30:73, :32:36]
reg [14:0] mask_1; // @[ISLIP.scala:17:25]
wire [14:0] _full_T_1 = {_in_vc_sel_T_74, 7'h0, _in_vc_sel_T_37, 1'h0, _in_vc_sel_T_24, 4'h0} & ~mask_1; // @[Mux.scala:30:73]
wire [29:0] oh = _full_T_1[0] ? 30'h1 : _full_T_1[1] ? 30'h2 : _full_T_1[2] ? 30'h4 : _full_T_1[3] ? 30'h8 : _full_T_1[4] ? 30'h10 : _full_T_1[5] ? 30'h20 : _full_T_1[6] ? 30'h40 : _full_T_1[7] ? 30'h80 : _full_T_1[8] ? 30'h100 : _full_T_1[9] ? 30'h200 : _full_T_1[10] ? 30'h400 : _full_T_1[11] ? 30'h800 : _full_T_1[12] ? 30'h1000 : _full_T_1[13] ? 30'h2000 : _full_T_1[14] ? 30'h4000 : _in_vc_sel_T_24 ? 30'h80000 : _in_vc_sel_T_37 ? 30'h200000 : {_in_vc_sel_T_74, 29'h0}; // @[OneHot.scala:85:71]
wire [14:0] sel = oh[14:0] | oh[29:15]; // @[Mux.scala:50:70]
wire in_alloc_2_4 = _GEN & sel[14]; // @[package.scala:81:59]
wire in_alloc_1_1 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i1_o1 :
output auto : { flip anon_in : UInt<1>[1], anon_out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : UInt<1>[1]
invalidate anonIn[0]
wire anonOut : UInt<1>[1]
invalidate anonOut[0]
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
connect anonOut[0], anonIn[0] | module IntXbar_i1_o1( // @[Xbar.scala:22:9]
input auto_anon_in_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_0_0 = auto_anon_in_0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire auto_anon_out_0_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = and(_T_11, _T_24)
node _T_81 = and(_T_80, _T_37)
node _T_82 = and(_T_81, _T_50)
node _T_83 = and(_T_82, _T_63)
node _T_84 = and(_T_83, _T_71)
node _T_85 = and(_T_84, _T_79)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_85, UInt<1>(0h1), "") : assert_1
node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_89 :
node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_100 = shr(io.in.a.bits.source, 2)
node _T_101 = eq(_T_100, UInt<1>(0h1))
node _T_102 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_103 = and(_T_101, _T_102)
node _T_104 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_105 = and(_T_103, _T_104)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_106 = shr(io.in.a.bits.source, 2)
node _T_107 = eq(_T_106, UInt<2>(0h2))
node _T_108 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_109 = and(_T_107, _T_108)
node _T_110 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_111 = and(_T_109, _T_110)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<2>(0h3))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_119 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_120 = or(_T_93, _T_99)
node _T_121 = or(_T_120, _T_105)
node _T_122 = or(_T_121, _T_111)
node _T_123 = or(_T_122, _T_117)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_124, _T_119)
node _T_126 = and(_T_92, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = and(_T_128, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = and(_T_127, _T_135)
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_136, UInt<1>(0h1), "") : assert_2
node _T_140 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_141 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_142 = and(_T_140, _T_141)
node _T_143 = or(UInt<1>(0h0), _T_142)
node _T_144 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = and(_T_143, _T_148)
node _T_150 = or(UInt<1>(0h0), _T_149)
node _T_151 = and(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_151, UInt<1>(0h1), "") : assert_3
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(source_ok, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_158 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_158, UInt<1>(0h1), "") : assert_5
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(is_aligned, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_165 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_165, UInt<1>(0h1), "") : assert_7
node _T_169 = not(io.in.a.bits.mask)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_170, UInt<1>(0h1), "") : assert_8
node _T_174 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_175 = asUInt(reset)
node _T_176 = eq(_T_175, UInt<1>(0h0))
when _T_176 :
node _T_177 = eq(_T_174, UInt<1>(0h0))
when _T_177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_174, UInt<1>(0h1), "") : assert_9
node _T_178 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_178 :
node _T_179 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_180 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_183 = shr(io.in.a.bits.source, 2)
node _T_184 = eq(_T_183, UInt<1>(0h0))
node _T_185 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_186 = and(_T_184, _T_185)
node _T_187 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_188 = and(_T_186, _T_187)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_189 = shr(io.in.a.bits.source, 2)
node _T_190 = eq(_T_189, UInt<1>(0h1))
node _T_191 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_192 = and(_T_190, _T_191)
node _T_193 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_194 = and(_T_192, _T_193)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_195 = shr(io.in.a.bits.source, 2)
node _T_196 = eq(_T_195, UInt<2>(0h2))
node _T_197 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_198 = and(_T_196, _T_197)
node _T_199 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_200 = and(_T_198, _T_199)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_201 = shr(io.in.a.bits.source, 2)
node _T_202 = eq(_T_201, UInt<2>(0h3))
node _T_203 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_204 = and(_T_202, _T_203)
node _T_205 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_206 = and(_T_204, _T_205)
node _T_207 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_208 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_209 = or(_T_182, _T_188)
node _T_210 = or(_T_209, _T_194)
node _T_211 = or(_T_210, _T_200)
node _T_212 = or(_T_211, _T_206)
node _T_213 = or(_T_212, _T_207)
node _T_214 = or(_T_213, _T_208)
node _T_215 = and(_T_181, _T_214)
node _T_216 = or(UInt<1>(0h0), _T_215)
node _T_217 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = and(_T_217, _T_222)
node _T_224 = or(UInt<1>(0h0), _T_223)
node _T_225 = and(_T_216, _T_224)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_225, UInt<1>(0h1), "") : assert_10
node _T_229 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_230 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_231 = and(_T_229, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_234 = cvt(_T_233)
node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000)))
node _T_236 = asSInt(_T_235)
node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0)))
node _T_238 = and(_T_232, _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = and(UInt<1>(0h0), _T_239)
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_240, UInt<1>(0h1), "") : assert_11
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(source_ok, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_248 = asUInt(reset)
node _T_249 = eq(_T_248, UInt<1>(0h0))
when _T_249 :
node _T_250 = eq(_T_247, UInt<1>(0h0))
when _T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_247, UInt<1>(0h1), "") : assert_13
node _T_251 = asUInt(reset)
node _T_252 = eq(_T_251, UInt<1>(0h0))
when _T_252 :
node _T_253 = eq(is_aligned, UInt<1>(0h0))
when _T_253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_254, UInt<1>(0h1), "") : assert_15
node _T_258 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_258, UInt<1>(0h1), "") : assert_16
node _T_262 = not(io.in.a.bits.mask)
node _T_263 = eq(_T_262, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_263, UInt<1>(0h1), "") : assert_17
node _T_267 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_267, UInt<1>(0h1), "") : assert_18
node _T_271 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_271 :
node _T_272 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_273 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_276 = shr(io.in.a.bits.source, 2)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_281 = and(_T_279, _T_280)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_282 = shr(io.in.a.bits.source, 2)
node _T_283 = eq(_T_282, UInt<1>(0h1))
node _T_284 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_285 = and(_T_283, _T_284)
node _T_286 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_287 = and(_T_285, _T_286)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_288 = shr(io.in.a.bits.source, 2)
node _T_289 = eq(_T_288, UInt<2>(0h2))
node _T_290 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_291 = and(_T_289, _T_290)
node _T_292 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_293 = and(_T_291, _T_292)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_294 = shr(io.in.a.bits.source, 2)
node _T_295 = eq(_T_294, UInt<2>(0h3))
node _T_296 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_297 = and(_T_295, _T_296)
node _T_298 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_301 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_302 = or(_T_275, _T_281)
node _T_303 = or(_T_302, _T_287)
node _T_304 = or(_T_303, _T_293)
node _T_305 = or(_T_304, _T_299)
node _T_306 = or(_T_305, _T_300)
node _T_307 = or(_T_306, _T_301)
node _T_308 = and(_T_274, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_309, UInt<1>(0h1), "") : assert_19
node _T_313 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_314 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_315 = and(_T_313, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<13>(0h1000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = and(_T_316, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(_T_323, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_323, UInt<1>(0h1), "") : assert_20
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(source_ok, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_330 = asUInt(reset)
node _T_331 = eq(_T_330, UInt<1>(0h0))
when _T_331 :
node _T_332 = eq(is_aligned, UInt<1>(0h0))
when _T_332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_333 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_333, UInt<1>(0h1), "") : assert_23
node _T_337 = eq(io.in.a.bits.mask, mask)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_337, UInt<1>(0h1), "") : assert_24
node _T_341 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_341, UInt<1>(0h1), "") : assert_25
node _T_345 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_345 :
node _T_346 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_347 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_350 = shr(io.in.a.bits.source, 2)
node _T_351 = eq(_T_350, UInt<1>(0h0))
node _T_352 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_353 = and(_T_351, _T_352)
node _T_354 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_355 = and(_T_353, _T_354)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_356 = shr(io.in.a.bits.source, 2)
node _T_357 = eq(_T_356, UInt<1>(0h1))
node _T_358 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_359 = and(_T_357, _T_358)
node _T_360 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_361 = and(_T_359, _T_360)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_362 = shr(io.in.a.bits.source, 2)
node _T_363 = eq(_T_362, UInt<2>(0h2))
node _T_364 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_365 = and(_T_363, _T_364)
node _T_366 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_367 = and(_T_365, _T_366)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_368 = shr(io.in.a.bits.source, 2)
node _T_369 = eq(_T_368, UInt<2>(0h3))
node _T_370 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_371 = and(_T_369, _T_370)
node _T_372 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_375 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_376 = or(_T_349, _T_355)
node _T_377 = or(_T_376, _T_361)
node _T_378 = or(_T_377, _T_367)
node _T_379 = or(_T_378, _T_373)
node _T_380 = or(_T_379, _T_374)
node _T_381 = or(_T_380, _T_375)
node _T_382 = and(_T_348, _T_381)
node _T_383 = or(UInt<1>(0h0), _T_382)
node _T_384 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_385 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_386 = and(_T_384, _T_385)
node _T_387 = or(UInt<1>(0h0), _T_386)
node _T_388 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_389 = cvt(_T_388)
node _T_390 = and(_T_389, asSInt(UInt<13>(0h1000)))
node _T_391 = asSInt(_T_390)
node _T_392 = eq(_T_391, asSInt(UInt<1>(0h0)))
node _T_393 = and(_T_387, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = and(_T_383, _T_394)
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_395, UInt<1>(0h1), "") : assert_26
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(source_ok, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(is_aligned, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_405 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_405, UInt<1>(0h1), "") : assert_29
node _T_409 = eq(io.in.a.bits.mask, mask)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_409, UInt<1>(0h1), "") : assert_30
node _T_413 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_413 :
node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_418 = shr(io.in.a.bits.source, 2)
node _T_419 = eq(_T_418, UInt<1>(0h0))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_424 = shr(io.in.a.bits.source, 2)
node _T_425 = eq(_T_424, UInt<1>(0h1))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_430 = shr(io.in.a.bits.source, 2)
node _T_431 = eq(_T_430, UInt<2>(0h2))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_436 = shr(io.in.a.bits.source, 2)
node _T_437 = eq(_T_436, UInt<2>(0h3))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_444 = or(_T_417, _T_423)
node _T_445 = or(_T_444, _T_429)
node _T_446 = or(_T_445, _T_435)
node _T_447 = or(_T_446, _T_441)
node _T_448 = or(_T_447, _T_442)
node _T_449 = or(_T_448, _T_443)
node _T_450 = and(_T_416, _T_449)
node _T_451 = or(UInt<1>(0h0), _T_450)
node _T_452 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_453 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_454 = and(_T_452, _T_453)
node _T_455 = or(UInt<1>(0h0), _T_454)
node _T_456 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = and(_T_455, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = and(_T_451, _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_463, UInt<1>(0h1), "") : assert_31
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(source_ok, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(is_aligned, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_473 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_473, UInt<1>(0h1), "") : assert_34
node _T_477 = not(mask)
node _T_478 = and(io.in.a.bits.mask, _T_477)
node _T_479 = eq(_T_478, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_479, UInt<1>(0h1), "") : assert_35
node _T_483 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_483 :
node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_488 = shr(io.in.a.bits.source, 2)
node _T_489 = eq(_T_488, UInt<1>(0h0))
node _T_490 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_491 = and(_T_489, _T_490)
node _T_492 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_493 = and(_T_491, _T_492)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_494 = shr(io.in.a.bits.source, 2)
node _T_495 = eq(_T_494, UInt<1>(0h1))
node _T_496 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_497 = and(_T_495, _T_496)
node _T_498 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_499 = and(_T_497, _T_498)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_500 = shr(io.in.a.bits.source, 2)
node _T_501 = eq(_T_500, UInt<2>(0h2))
node _T_502 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_503 = and(_T_501, _T_502)
node _T_504 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_505 = and(_T_503, _T_504)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_506 = shr(io.in.a.bits.source, 2)
node _T_507 = eq(_T_506, UInt<2>(0h3))
node _T_508 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_509 = and(_T_507, _T_508)
node _T_510 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_511 = and(_T_509, _T_510)
node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_513 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_514 = or(_T_487, _T_493)
node _T_515 = or(_T_514, _T_499)
node _T_516 = or(_T_515, _T_505)
node _T_517 = or(_T_516, _T_511)
node _T_518 = or(_T_517, _T_512)
node _T_519 = or(_T_518, _T_513)
node _T_520 = and(_T_486, _T_519)
node _T_521 = or(UInt<1>(0h0), _T_520)
node _T_522 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_523 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _T_525 = or(UInt<1>(0h0), _T_524)
node _T_526 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<13>(0h1000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_531)
node _T_533 = and(_T_521, _T_532)
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(_T_533, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_533, UInt<1>(0h1), "") : assert_36
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(source_ok, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_540 = asUInt(reset)
node _T_541 = eq(_T_540, UInt<1>(0h0))
when _T_541 :
node _T_542 = eq(is_aligned, UInt<1>(0h0))
when _T_542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_543 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_543, UInt<1>(0h1), "") : assert_39
node _T_547 = eq(io.in.a.bits.mask, mask)
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(_T_547, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_547, UInt<1>(0h1), "") : assert_40
node _T_551 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_551 :
node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_556 = shr(io.in.a.bits.source, 2)
node _T_557 = eq(_T_556, UInt<1>(0h0))
node _T_558 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_559 = and(_T_557, _T_558)
node _T_560 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_561 = and(_T_559, _T_560)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_562 = shr(io.in.a.bits.source, 2)
node _T_563 = eq(_T_562, UInt<1>(0h1))
node _T_564 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_565 = and(_T_563, _T_564)
node _T_566 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_567 = and(_T_565, _T_566)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_568 = shr(io.in.a.bits.source, 2)
node _T_569 = eq(_T_568, UInt<2>(0h2))
node _T_570 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_571 = and(_T_569, _T_570)
node _T_572 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_573 = and(_T_571, _T_572)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_574 = shr(io.in.a.bits.source, 2)
node _T_575 = eq(_T_574, UInt<2>(0h3))
node _T_576 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_577 = and(_T_575, _T_576)
node _T_578 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_581 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_582 = or(_T_555, _T_561)
node _T_583 = or(_T_582, _T_567)
node _T_584 = or(_T_583, _T_573)
node _T_585 = or(_T_584, _T_579)
node _T_586 = or(_T_585, _T_580)
node _T_587 = or(_T_586, _T_581)
node _T_588 = and(_T_554, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = or(UInt<1>(0h0), _T_599)
node _T_601 = and(_T_589, _T_600)
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_601, UInt<1>(0h1), "") : assert_41
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(source_ok, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(is_aligned, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_611 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_611, UInt<1>(0h1), "") : assert_44
node _T_615 = eq(io.in.a.bits.mask, mask)
node _T_616 = asUInt(reset)
node _T_617 = eq(_T_616, UInt<1>(0h0))
when _T_617 :
node _T_618 = eq(_T_615, UInt<1>(0h0))
when _T_618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_615, UInt<1>(0h1), "") : assert_45
node _T_619 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_619 :
node _T_620 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_621 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_622 = and(_T_620, _T_621)
node _T_623 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_624 = shr(io.in.a.bits.source, 2)
node _T_625 = eq(_T_624, UInt<1>(0h0))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_630 = shr(io.in.a.bits.source, 2)
node _T_631 = eq(_T_630, UInt<1>(0h1))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_636 = shr(io.in.a.bits.source, 2)
node _T_637 = eq(_T_636, UInt<2>(0h2))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_641 = and(_T_639, _T_640)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_642 = shr(io.in.a.bits.source, 2)
node _T_643 = eq(_T_642, UInt<2>(0h3))
node _T_644 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_645 = and(_T_643, _T_644)
node _T_646 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_647 = and(_T_645, _T_646)
node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_650 = or(_T_623, _T_629)
node _T_651 = or(_T_650, _T_635)
node _T_652 = or(_T_651, _T_641)
node _T_653 = or(_T_652, _T_647)
node _T_654 = or(_T_653, _T_648)
node _T_655 = or(_T_654, _T_649)
node _T_656 = and(_T_622, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = or(UInt<1>(0h0), _T_660)
node _T_662 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_663 = cvt(_T_662)
node _T_664 = and(_T_663, asSInt(UInt<13>(0h1000)))
node _T_665 = asSInt(_T_664)
node _T_666 = eq(_T_665, asSInt(UInt<1>(0h0)))
node _T_667 = and(_T_661, _T_666)
node _T_668 = or(UInt<1>(0h0), _T_667)
node _T_669 = and(_T_657, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_669, UInt<1>(0h1), "") : assert_46
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(source_ok, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(is_aligned, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_679 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_679, UInt<1>(0h1), "") : assert_49
node _T_683 = eq(io.in.a.bits.mask, mask)
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(_T_683, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_683, UInt<1>(0h1), "") : assert_50
node _T_687 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_688 = asUInt(reset)
node _T_689 = eq(_T_688, UInt<1>(0h0))
when _T_689 :
node _T_690 = eq(_T_687, UInt<1>(0h0))
when _T_690 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_687, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_691 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_691, UInt<1>(0h1), "") : assert_52
node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_33 = shr(io.in.d.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_32
connect _source_ok_WIRE_1[1], _source_ok_T_38
connect _source_ok_WIRE_1[2], _source_ok_T_44
connect _source_ok_WIRE_1[3], _source_ok_T_50
connect _source_ok_WIRE_1[4], _source_ok_T_56
connect _source_ok_WIRE_1[5], _source_ok_T_57
connect _source_ok_WIRE_1[6], _source_ok_T_58
node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_695 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_695 :
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(source_ok_1, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_699 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(_T_699, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_699, UInt<1>(0h1), "") : assert_54
node _T_703 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_703, UInt<1>(0h1), "") : assert_55
node _T_707 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_707, UInt<1>(0h1), "") : assert_56
node _T_711 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_711, UInt<1>(0h1), "") : assert_57
node _T_715 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_715 :
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(source_ok_1, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(sink_ok, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_722 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(_T_722, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_722, UInt<1>(0h1), "") : assert_60
node _T_726 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_726, UInt<1>(0h1), "") : assert_61
node _T_730 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_730, UInt<1>(0h1), "") : assert_62
node _T_734 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(_T_734, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_734, UInt<1>(0h1), "") : assert_63
node _T_738 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_739 = or(UInt<1>(0h1), _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_739, UInt<1>(0h1), "") : assert_64
node _T_743 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_743 :
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(source_ok_1, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(sink_ok, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_750 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_750, UInt<1>(0h1), "") : assert_67
node _T_754 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_754, UInt<1>(0h1), "") : assert_68
node _T_758 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(_T_758, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_758, UInt<1>(0h1), "") : assert_69
node _T_762 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_763 = or(_T_762, io.in.d.bits.corrupt)
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_763, UInt<1>(0h1), "") : assert_70
node _T_767 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_768 = or(UInt<1>(0h1), _T_767)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_768, UInt<1>(0h1), "") : assert_71
node _T_772 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_772 :
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(source_ok_1, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_776 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_776, UInt<1>(0h1), "") : assert_73
node _T_780 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(_T_780, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_780, UInt<1>(0h1), "") : assert_74
node _T_784 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_785 = or(UInt<1>(0h1), _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_785, UInt<1>(0h1), "") : assert_75
node _T_789 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_789 :
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(source_ok_1, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_793 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_793, UInt<1>(0h1), "") : assert_77
node _T_797 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_798 = or(_T_797, io.in.d.bits.corrupt)
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(_T_798, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_798, UInt<1>(0h1), "") : assert_78
node _T_802 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_803 = or(UInt<1>(0h1), _T_802)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_803, UInt<1>(0h1), "") : assert_79
node _T_807 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_807 :
node _T_808 = asUInt(reset)
node _T_809 = eq(_T_808, UInt<1>(0h0))
when _T_809 :
node _T_810 = eq(source_ok_1, UInt<1>(0h0))
when _T_810 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_811 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_811, UInt<1>(0h1), "") : assert_81
node _T_815 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(_T_815, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_815, UInt<1>(0h1), "") : assert_82
node _T_819 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_820 = or(UInt<1>(0h1), _T_819)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_820, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_824 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_824, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_828 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_828, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_832 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_832, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_836 = eq(a_first, UInt<1>(0h0))
node _T_837 = and(io.in.a.valid, _T_836)
when _T_837 :
node _T_838 = eq(io.in.a.bits.opcode, opcode)
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_838, UInt<1>(0h1), "") : assert_87
node _T_842 = eq(io.in.a.bits.param, param)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_842, UInt<1>(0h1), "") : assert_88
node _T_846 = eq(io.in.a.bits.size, size)
node _T_847 = asUInt(reset)
node _T_848 = eq(_T_847, UInt<1>(0h0))
when _T_848 :
node _T_849 = eq(_T_846, UInt<1>(0h0))
when _T_849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_846, UInt<1>(0h1), "") : assert_89
node _T_850 = eq(io.in.a.bits.source, source)
node _T_851 = asUInt(reset)
node _T_852 = eq(_T_851, UInt<1>(0h0))
when _T_852 :
node _T_853 = eq(_T_850, UInt<1>(0h0))
when _T_853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_850, UInt<1>(0h1), "") : assert_90
node _T_854 = eq(io.in.a.bits.address, address)
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(_T_854, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_854, UInt<1>(0h1), "") : assert_91
node _T_858 = and(io.in.a.ready, io.in.a.valid)
node _T_859 = and(_T_858, a_first)
when _T_859 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_860 = eq(d_first, UInt<1>(0h0))
node _T_861 = and(io.in.d.valid, _T_860)
when _T_861 :
node _T_862 = eq(io.in.d.bits.opcode, opcode_1)
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_862, UInt<1>(0h1), "") : assert_92
node _T_866 = eq(io.in.d.bits.param, param_1)
node _T_867 = asUInt(reset)
node _T_868 = eq(_T_867, UInt<1>(0h0))
when _T_868 :
node _T_869 = eq(_T_866, UInt<1>(0h0))
when _T_869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_866, UInt<1>(0h1), "") : assert_93
node _T_870 = eq(io.in.d.bits.size, size_1)
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_870, UInt<1>(0h1), "") : assert_94
node _T_874 = eq(io.in.d.bits.source, source_1)
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_874, UInt<1>(0h1), "") : assert_95
node _T_878 = eq(io.in.d.bits.sink, sink)
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_878, UInt<1>(0h1), "") : assert_96
node _T_882 = eq(io.in.d.bits.denied, denied)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_882, UInt<1>(0h1), "") : assert_97
node _T_886 = and(io.in.d.ready, io.in.d.valid)
node _T_887 = and(_T_886, d_first)
when _T_887 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_888 = and(io.in.a.valid, a_first_1)
node _T_889 = and(_T_888, UInt<1>(0h1))
when _T_889 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_890 = and(io.in.a.ready, io.in.a.valid)
node _T_891 = and(_T_890, a_first_1)
node _T_892 = and(_T_891, UInt<1>(0h1))
when _T_892 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_893 = dshr(inflight, io.in.a.bits.source)
node _T_894 = bits(_T_893, 0, 0)
node _T_895 = eq(_T_894, UInt<1>(0h0))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_895, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_899 = and(io.in.d.valid, d_first_1)
node _T_900 = and(_T_899, UInt<1>(0h1))
node _T_901 = eq(d_release_ack, UInt<1>(0h0))
node _T_902 = and(_T_900, _T_901)
when _T_902 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_903 = and(io.in.d.ready, io.in.d.valid)
node _T_904 = and(_T_903, d_first_1)
node _T_905 = and(_T_904, UInt<1>(0h1))
node _T_906 = eq(d_release_ack, UInt<1>(0h0))
node _T_907 = and(_T_905, _T_906)
when _T_907 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_908 = and(io.in.d.valid, d_first_1)
node _T_909 = and(_T_908, UInt<1>(0h1))
node _T_910 = eq(d_release_ack, UInt<1>(0h0))
node _T_911 = and(_T_909, _T_910)
when _T_911 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_912 = dshr(inflight, io.in.d.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = or(_T_913, same_cycle_resp)
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_914, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_918 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_919 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_920 = or(_T_918, _T_919)
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_920, UInt<1>(0h1), "") : assert_100
node _T_924 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_924, UInt<1>(0h1), "") : assert_101
else :
node _T_928 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_929 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_930 = or(_T_928, _T_929)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_930, UInt<1>(0h1), "") : assert_102
node _T_934 = eq(io.in.d.bits.size, a_size_lookup)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_934, UInt<1>(0h1), "") : assert_103
node _T_938 = and(io.in.d.valid, d_first_1)
node _T_939 = and(_T_938, a_first_1)
node _T_940 = and(_T_939, io.in.a.valid)
node _T_941 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(d_release_ack, UInt<1>(0h0))
node _T_944 = and(_T_942, _T_943)
when _T_944 :
node _T_945 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_946 = or(_T_945, io.in.a.ready)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_946, UInt<1>(0h1), "") : assert_104
node _T_950 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_951 = orr(a_set_wo_ready)
node _T_952 = eq(_T_951, UInt<1>(0h0))
node _T_953 = or(_T_950, _T_952)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_953, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_42
node _T_957 = orr(inflight)
node _T_958 = eq(_T_957, UInt<1>(0h0))
node _T_959 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_960 = or(_T_958, _T_959)
node _T_961 = lt(watchdog, plusarg_reader.out)
node _T_962 = or(_T_960, _T_961)
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(_T_962, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_962, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_966 = and(io.in.a.ready, io.in.a.valid)
node _T_967 = and(io.in.d.ready, io.in.d.valid)
node _T_968 = or(_T_966, _T_967)
when _T_968 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_969 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<14>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_970 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_971 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_972 = and(_T_970, _T_971)
node _T_973 = and(_T_969, _T_972)
when _T_973 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_974 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_975 = and(_T_974, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_976 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_977 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_978 = and(_T_976, _T_977)
node _T_979 = and(_T_975, _T_978)
when _T_979 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_980 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_981 = bits(_T_980, 0, 0)
node _T_982 = eq(_T_981, UInt<1>(0h0))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_982, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_986 = and(io.in.d.valid, d_first_2)
node _T_987 = and(_T_986, UInt<1>(0h1))
node _T_988 = and(_T_987, d_release_ack_1)
when _T_988 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_989 = and(io.in.d.ready, io.in.d.valid)
node _T_990 = and(_T_989, d_first_2)
node _T_991 = and(_T_990, UInt<1>(0h1))
node _T_992 = and(_T_991, d_release_ack_1)
when _T_992 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_993 = and(io.in.d.valid, d_first_2)
node _T_994 = and(_T_993, UInt<1>(0h1))
node _T_995 = and(_T_994, d_release_ack_1)
when _T_995 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_996 = dshr(inflight_1, io.in.d.bits.source)
node _T_997 = bits(_T_996, 0, 0)
node _T_998 = or(_T_997, same_cycle_resp_1)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_998, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1002 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_109
else :
node _T_1006 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_110
node _T_1010 = and(io.in.d.valid, d_first_2)
node _T_1011 = and(_T_1010, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1012 = and(_T_1011, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1013 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1014 = and(_T_1012, _T_1013)
node _T_1015 = and(_T_1014, d_release_ack_1)
node _T_1016 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1017 = and(_T_1015, _T_1016)
when _T_1017 :
node _T_1018 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1019 = or(_T_1018, _WIRE_23.ready)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_111
node _T_1023 = orr(c_set_wo_ready)
when _T_1023 :
node _T_1024 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_43
node _T_1028 = orr(inflight_1)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
node _T_1030 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1031 = or(_T_1029, _T_1030)
node _T_1032 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1033 = or(_T_1031, _T_1032)
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1037 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1038 = and(io.in.d.ready, io.in.d.valid)
node _T_1039 = or(_T_1037, _T_1038)
when _T_1039 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_33 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_45 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_51 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_966 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1039 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1039; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1039; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1039; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_892 = _T_966 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_892 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_892 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_892 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_892 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_892 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_938 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_938 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_907 = _T_1039 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_907 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_907 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_907 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1010 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1010 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_992 = _T_1039 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_992 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_992 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_992 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<7>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 6, 0)
node _source_ok_T = shr(io.in.a.bits.source, 7)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<7>(0h73))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits = bits(_uncommonBits_T, 6, 0)
node _T_4 = shr(io.in.a.bits.source, 7)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<7>(0h73))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 6, 0)
node _T_24 = shr(io.in.a.bits.source, 7)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<7>(0h73))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 6, 0)
node _T_86 = shr(io.in.a.bits.source, 7)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<7>(0h73))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 6, 0)
node _T_152 = shr(io.in.a.bits.source, 7)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<7>(0h73))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 6, 0)
node _T_199 = shr(io.in.a.bits.source, 7)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<7>(0h73))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 6, 0)
node _T_240 = shr(io.in.a.bits.source, 7)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<7>(0h73))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 6, 0)
node _T_283 = shr(io.in.a.bits.source, 7)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<7>(0h73))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 6, 0)
node _T_321 = shr(io.in.a.bits.source, 7)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<7>(0h73))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<7>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 6, 0)
node _T_359 = shr(io.in.a.bits.source, 7)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<7>(0h73))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<7>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 6, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 7)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<7>(0h73))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h1), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h1), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h1), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h1), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h1), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<116>, clock, reset, UInt<116>(0h0)
regreset inflight_opcodes : UInt<464>, clock, reset, UInt<464>(0h0)
regreset inflight_sizes : UInt<464>, clock, reset, UInt<464>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<116>
connect a_set, UInt<116>(0h0)
wire a_set_wo_ready : UInt<116>
connect a_set_wo_ready, UInt<116>(0h0)
wire a_opcodes_set : UInt<464>
connect a_opcodes_set, UInt<464>(0h0)
wire a_sizes_set : UInt<464>
connect a_sizes_set, UInt<464>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<116>
connect d_clr, UInt<116>(0h0)
wire d_clr_wo_ready : UInt<116>
connect d_clr_wo_ready, UInt<116>(0h0)
wire d_opcodes_clr : UInt<464>
connect d_opcodes_clr, UInt<464>(0h0)
wire d_sizes_clr : UInt<464>
connect d_sizes_clr, UInt<464>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_126
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<116>, clock, reset, UInt<116>(0h0)
regreset inflight_opcodes_1 : UInt<464>, clock, reset, UInt<464>(0h0)
regreset inflight_sizes_1 : UInt<464>, clock, reset, UInt<464>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<116>
connect c_set, UInt<116>(0h0)
wire c_set_wo_ready : UInt<116>
connect c_set_wo_ready, UInt<116>(0h0)
wire c_opcodes_set : UInt<464>
connect c_opcodes_set, UInt<464>(0h0)
wire c_sizes_set : UInt<464>
connect c_sizes_set, UInt<464>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<116>
connect d_clr_1, UInt<116>(0h0)
wire d_clr_wo_ready_1 : UInt<116>
connect d_clr_wo_ready_1, UInt<116>(0h0)
wire d_opcodes_clr_1 : UInt<464>
connect d_opcodes_clr_1, UInt<464>(0h0)
wire d_sizes_clr_1 : UInt<464>
connect d_sizes_clr_1, UInt<464>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_127
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [115:0] inflight; // @[Monitor.scala:614:27]
reg [463:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [463:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [115:0] inflight_1; // @[Monitor.scala:726:35]
reg [463:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_81 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_81( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_33 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_43
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_33( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_43 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_ShuttleTile_i0_o0_a1d8s1k1z1u :
input clock : Clock
input reset : Reset
output auto : { }
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] | module TLXbar_SlaveXbar_ShuttleTile_i0_o0_a1d8s1k1z1u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset // @[Xbar.scala:74:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i32_12 :
input clock : Clock
input reset : Reset
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node magGeOne = bits(rawIn.sExp, 8, 8)
node posExp = bits(rawIn.sExp, 7, 0)
node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0))
node _magJustBelowOne_T_1 = andr(posExp)
node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1)
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _shiftedSig_T = bits(rawIn.sig, 22, 0)
node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T)
node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0)
node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0))
node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3)
node _alignedSig_T = shr(shiftedSig, 22)
node _alignedSig_T_1 = bits(shiftedSig, 21, 0)
node _alignedSig_T_2 = orr(_alignedSig_T_1)
node alignedSig = cat(_alignedSig_T, _alignedSig_T_2)
node _unroundedInt_T = shr(alignedSig, 2)
node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T)
node _common_inexact_T = bits(alignedSig, 1, 0)
node _common_inexact_T_1 = orr(_common_inexact_T)
node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0))
node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2)
node _roundIncr_near_even_T = bits(alignedSig, 2, 1)
node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T)
node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2)
node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3)
node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4)
node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0)
node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6)
node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7)
node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8)
node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1)
node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T)
node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne)
node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even)
node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag)
node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1)
node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd)
node _roundIncr_T_4 = and(rawIn.sign, common_inexact)
node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4)
node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5)
node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0))
node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact)
node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8)
node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9)
node _complUnroundedInt_T = not(unroundedInt)
node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt)
node _roundedInt_T = xor(roundIncr, rawIn.sign)
node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1))
node _roundedInt_T_2 = tail(_roundedInt_T_1, 1)
node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt)
node _roundedInt_T_4 = and(roundingMode_odd, common_inexact)
node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4)
node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f))
node _roundCarryBut2_T = bits(unroundedInt, 29, 0)
node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T)
node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr)
node _common_overflow_T = geq(posExp, UInt<6>(0h20))
node _common_overflow_T_1 = bits(unroundedInt, 30, 0)
node _common_overflow_T_2 = orr(_common_overflow_T_1)
node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr)
node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3)
node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e))
node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2)
node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6)
node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7)
node _common_overflow_T_9 = bits(unroundedInt, 30, 30)
node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9)
node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2)
node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11)
node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12)
node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13)
node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0))
node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign)
node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr)
node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17)
node invalidExc = or(rawIn.isNaN, rawIn.isInf)
node _overflow_T = eq(invalidExc, UInt<1>(0h0))
node overflow = and(_overflow_T, common_overflow)
node _inexact_T = eq(invalidExc, UInt<1>(0h0))
node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0))
node _inexact_T_2 = and(_inexact_T, _inexact_T_1)
node inexact = and(_inexact_T_2, common_inexact)
node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0))
node excSign = and(_excSign_T, rawIn.sign)
node _excOut_T = eq(io.signedOut, excSign)
node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0))
node _excOut_T_2 = eq(excSign, UInt<1>(0h0))
node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0))
node excOut = or(_excOut_T_1, _excOut_T_3)
node _io_out_T = or(invalidExc, common_overflow)
node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt)
connect io.out, _io_out_T_1
node _io_intExceptionFlags_T = cat(invalidExc, overflow)
node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact)
connect io.intExceptionFlags, _io_intExceptionFlags_T_1 | module RecFNToIN_e8_s24_i32_12( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [32:0] io_in, // @[RecFNToIN.scala:49:16]
output [31:0] io_out, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53]
wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53]
wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53]
wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53]
wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53]
wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35]
wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28]
wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49]
wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27]
wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31]
wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13]
wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27]
wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41]
wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7]
wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7]
wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [31:0] io_out_0; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [54:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [32:0] _alignedSig_T = shiftedSig[54:22]; // @[RecFNToIN.scala:83:49, :89:20]
wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}]
wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31]
wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire [31:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11]
wire magGeOne_atOverflowEdge = posExp == 8'h1F; // @[RecFNToIN.scala:62:28, :110:43]
wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[7:5]); // @[RecFNToIN.scala:62:28, :116:21]
wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 8'h1E; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24]
wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27]
wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_out = io_out_0; // @[RecFNToIN.scala:46:7]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_18 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_18( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_7 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_7
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e11_s53_7( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_7 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
connect _source_ok_WIRE[2], _source_ok_T_2
node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_23 = cvt(_T_22)
node _T_24 = and(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = asSInt(_T_24)
node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = or(_T_21, _T_26)
node _T_28 = and(_T_11, _T_19)
node _T_29 = and(_T_28, _T_27)
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_33 :
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_40 = or(_T_37, _T_38)
node _T_41 = or(_T_40, _T_39)
node _T_42 = and(_T_36, _T_41)
node _T_43 = or(UInt<1>(0h0), _T_42)
node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = or(_T_49, _T_54)
node _T_86 = or(_T_85, _T_59)
node _T_87 = or(_T_86, _T_64)
node _T_88 = or(_T_87, _T_69)
node _T_89 = or(_T_88, _T_74)
node _T_90 = or(_T_89, _T_79)
node _T_91 = or(_T_90, _T_84)
node _T_92 = and(_T_44, _T_91)
node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_94, _T_105)
node _T_107 = or(UInt<1>(0h0), _T_92)
node _T_108 = or(_T_107, _T_106)
node _T_109 = and(_T_43, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_109, UInt<1>(0h1), "") : assert_2
node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_113
connect _WIRE[1], _T_114
connect _WIRE[2], _T_115
node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0))
node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_120 = or(_T_117, _T_118)
node _T_121 = or(_T_120, _T_119)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_121
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(_WIRE_1, _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_221 = or(_T_218, _T_219)
node _T_222 = or(_T_221, _T_220)
node _T_223 = and(_T_217, _T_222)
node _T_224 = or(UInt<1>(0h0), _T_223)
node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_230, _T_235)
node _T_267 = or(_T_266, _T_240)
node _T_268 = or(_T_267, _T_245)
node _T_269 = or(_T_268, _T_250)
node _T_270 = or(_T_269, _T_255)
node _T_271 = or(_T_270, _T_260)
node _T_272 = or(_T_271, _T_265)
node _T_273 = and(_T_225, _T_272)
node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_280, _T_285)
node _T_287 = and(_T_275, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_273)
node _T_289 = or(_T_288, _T_287)
node _T_290 = and(_T_224, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_290, UInt<1>(0h1), "") : assert_10
node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_294
connect _WIRE_2[1], _T_295
connect _WIRE_2[2], _T_296
node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0))
node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = or(_T_298, _T_299)
node _T_302 = or(_T_301, _T_300)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_302
node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_305 = and(_T_303, _T_304)
node _T_306 = or(UInt<1>(0h0), _T_305)
node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = or(_T_311, _T_316)
node _T_358 = or(_T_357, _T_321)
node _T_359 = or(_T_358, _T_326)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_336)
node _T_362 = or(_T_361, _T_341)
node _T_363 = or(_T_362, _T_346)
node _T_364 = or(_T_363, _T_351)
node _T_365 = or(_T_364, _T_356)
node _T_366 = and(_T_306, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_WIRE_3, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_368, UInt<1>(0h1), "") : assert_11
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(source_ok, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_375, UInt<1>(0h1), "") : assert_13
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(is_aligned, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_382, UInt<1>(0h1), "") : assert_15
node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_386, UInt<1>(0h1), "") : assert_16
node _T_390 = not(io.in.a.bits.mask)
node _T_391 = eq(_T_390, UInt<1>(0h0))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_391, UInt<1>(0h1), "") : assert_17
node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_395, UInt<1>(0h1), "") : assert_18
node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_399 :
node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_406 = or(_T_403, _T_404)
node _T_407 = or(_T_406, _T_405)
node _T_408 = and(_T_402, _T_407)
node _T_409 = or(UInt<1>(0h0), _T_408)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_409, UInt<1>(0h1), "") : assert_19
node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_415 = and(_T_413, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = and(_T_416, _T_421)
node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_425 = and(_T_423, _T_424)
node _T_426 = or(UInt<1>(0h0), _T_425)
node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_433 = cvt(_T_432)
node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000)))
node _T_435 = asSInt(_T_434)
node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0)))
node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_438 = cvt(_T_437)
node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000)))
node _T_440 = asSInt(_T_439)
node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0)))
node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_443 = cvt(_T_442)
node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000)))
node _T_445 = asSInt(_T_444)
node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0)))
node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = or(_T_431, _T_436)
node _T_473 = or(_T_472, _T_441)
node _T_474 = or(_T_473, _T_446)
node _T_475 = or(_T_474, _T_451)
node _T_476 = or(_T_475, _T_456)
node _T_477 = or(_T_476, _T_461)
node _T_478 = or(_T_477, _T_466)
node _T_479 = or(_T_478, _T_471)
node _T_480 = and(_T_426, _T_479)
node _T_481 = or(UInt<1>(0h0), _T_422)
node _T_482 = or(_T_481, _T_480)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_482, UInt<1>(0h1), "") : assert_20
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(source_ok, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(is_aligned, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_492, UInt<1>(0h1), "") : assert_23
node _T_496 = eq(io.in.a.bits.mask, mask)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_496, UInt<1>(0h1), "") : assert_24
node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_500, UInt<1>(0h1), "") : assert_25
node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_504 :
node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_511 = or(_T_508, _T_509)
node _T_512 = or(_T_511, _T_510)
node _T_513 = and(_T_507, _T_512)
node _T_514 = or(UInt<1>(0h0), _T_513)
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = and(_T_518, _T_523)
node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_527 = and(_T_525, _T_526)
node _T_528 = or(UInt<1>(0h0), _T_527)
node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = or(_T_533, _T_538)
node _T_570 = or(_T_569, _T_543)
node _T_571 = or(_T_570, _T_548)
node _T_572 = or(_T_571, _T_553)
node _T_573 = or(_T_572, _T_558)
node _T_574 = or(_T_573, _T_563)
node _T_575 = or(_T_574, _T_568)
node _T_576 = and(_T_528, _T_575)
node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = and(_T_577, _T_582)
node _T_584 = or(UInt<1>(0h0), _T_524)
node _T_585 = or(_T_584, _T_576)
node _T_586 = or(_T_585, _T_583)
node _T_587 = and(_T_514, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_587, UInt<1>(0h1), "") : assert_26
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(is_aligned, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_597, UInt<1>(0h1), "") : assert_29
node _T_601 = eq(io.in.a.bits.mask, mask)
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_601, UInt<1>(0h1), "") : assert_30
node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_605 :
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_608 = and(_T_606, _T_607)
node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_612 = or(_T_609, _T_610)
node _T_613 = or(_T_612, _T_611)
node _T_614 = and(_T_608, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = and(_T_619, _T_624)
node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_628 = and(_T_626, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_628)
node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_656 = cvt(_T_655)
node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000)))
node _T_658 = asSInt(_T_657)
node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0)))
node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = or(_T_634, _T_639)
node _T_671 = or(_T_670, _T_644)
node _T_672 = or(_T_671, _T_649)
node _T_673 = or(_T_672, _T_654)
node _T_674 = or(_T_673, _T_659)
node _T_675 = or(_T_674, _T_664)
node _T_676 = or(_T_675, _T_669)
node _T_677 = and(_T_629, _T_676)
node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_680 = cvt(_T_679)
node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000)))
node _T_682 = asSInt(_T_681)
node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0)))
node _T_684 = and(_T_678, _T_683)
node _T_685 = or(UInt<1>(0h0), _T_625)
node _T_686 = or(_T_685, _T_677)
node _T_687 = or(_T_686, _T_684)
node _T_688 = and(_T_615, _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_688, UInt<1>(0h1), "") : assert_31
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(source_ok, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(is_aligned, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_698, UInt<1>(0h1), "") : assert_34
node _T_702 = not(mask)
node _T_703 = and(io.in.a.bits.mask, _T_702)
node _T_704 = eq(_T_703, UInt<1>(0h0))
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_704, UInt<1>(0h1), "") : assert_35
node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_708 :
node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_711 = and(_T_709, _T_710)
node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_715 = or(_T_712, _T_713)
node _T_716 = or(_T_715, _T_714)
node _T_717 = and(_T_711, _T_716)
node _T_718 = or(UInt<1>(0h0), _T_717)
node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_744 = cvt(_T_743)
node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000)))
node _T_746 = asSInt(_T_745)
node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0)))
node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_749 = cvt(_T_748)
node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000)))
node _T_751 = asSInt(_T_750)
node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0)))
node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_764 = cvt(_T_763)
node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000)))
node _T_766 = asSInt(_T_765)
node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0)))
node _T_768 = or(_T_727, _T_732)
node _T_769 = or(_T_768, _T_737)
node _T_770 = or(_T_769, _T_742)
node _T_771 = or(_T_770, _T_747)
node _T_772 = or(_T_771, _T_752)
node _T_773 = or(_T_772, _T_757)
node _T_774 = or(_T_773, _T_762)
node _T_775 = or(_T_774, _T_767)
node _T_776 = and(_T_722, _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_776)
node _T_785 = or(_T_784, _T_783)
node _T_786 = and(_T_718, _T_785)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_786, UInt<1>(0h1), "") : assert_36
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(source_ok, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(is_aligned, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_796, UInt<1>(0h1), "") : assert_39
node _T_800 = eq(io.in.a.bits.mask, mask)
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_800, UInt<1>(0h1), "") : assert_40
node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_811 = or(_T_808, _T_809)
node _T_812 = or(_T_811, _T_810)
node _T_813 = and(_T_807, _T_812)
node _T_814 = or(UInt<1>(0h0), _T_813)
node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_817 = and(_T_815, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = or(_T_823, _T_828)
node _T_865 = or(_T_864, _T_833)
node _T_866 = or(_T_865, _T_838)
node _T_867 = or(_T_866, _T_843)
node _T_868 = or(_T_867, _T_848)
node _T_869 = or(_T_868, _T_853)
node _T_870 = or(_T_869, _T_858)
node _T_871 = or(_T_870, _T_863)
node _T_872 = and(_T_818, _T_871)
node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = and(_T_873, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_872)
node _T_881 = or(_T_880, _T_879)
node _T_882 = and(_T_814, _T_881)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_882, UInt<1>(0h1), "") : assert_41
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(is_aligned, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_892, UInt<1>(0h1), "") : assert_44
node _T_896 = eq(io.in.a.bits.mask, mask)
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_896, UInt<1>(0h1), "") : assert_45
node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_907 = or(_T_904, _T_905)
node _T_908 = or(_T_907, _T_906)
node _T_909 = and(_T_903, _T_908)
node _T_910 = or(UInt<1>(0h0), _T_909)
node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_913 = and(_T_911, _T_912)
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = and(_T_914, _T_919)
node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_933 = cvt(_T_932)
node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000)))
node _T_935 = asSInt(_T_934)
node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0)))
node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_948 = cvt(_T_947)
node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000)))
node _T_950 = asSInt(_T_949)
node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0)))
node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_953 = cvt(_T_952)
node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000)))
node _T_955 = asSInt(_T_954)
node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0)))
node _T_957 = or(_T_926, _T_931)
node _T_958 = or(_T_957, _T_936)
node _T_959 = or(_T_958, _T_941)
node _T_960 = or(_T_959, _T_946)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_956)
node _T_963 = and(_T_921, _T_962)
node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_966 = and(_T_964, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_969 = cvt(_T_968)
node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000)))
node _T_971 = asSInt(_T_970)
node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0)))
node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_974 = cvt(_T_973)
node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000)))
node _T_976 = asSInt(_T_975)
node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0)))
node _T_978 = or(_T_972, _T_977)
node _T_979 = and(_T_967, _T_978)
node _T_980 = or(UInt<1>(0h0), _T_920)
node _T_981 = or(_T_980, _T_963)
node _T_982 = or(_T_981, _T_979)
node _T_983 = and(_T_910, _T_982)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_983, UInt<1>(0h1), "") : assert_46
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(source_ok, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(is_aligned, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_993, UInt<1>(0h1), "") : assert_49
node _T_997 = eq(io.in.a.bits.mask, mask)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_997, UInt<1>(0h1), "") : assert_50
node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52
node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1))
node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_4
connect _source_ok_WIRE_1[1], _source_ok_T_5
connect _source_ok_WIRE_1[2], _source_ok_T_6
node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1009 :
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(source_ok_1, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54
node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55
node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56
node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57
node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1029 :
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(source_ok_1, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(sink_ok, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60
node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61
node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62
node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63
node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1053 = or(UInt<1>(0h1), _T_1052)
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64
node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1057 :
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(source_ok_1, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(sink_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67
node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68
node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69
node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1077 = or(_T_1076, io.in.d.bits.corrupt)
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70
node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1082 = or(UInt<1>(0h1), _T_1081)
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71
node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73
node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74
node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1099 = or(UInt<1>(0h1), _T_1098)
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75
node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1103 :
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(source_ok_1, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77
node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.d.bits.corrupt)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78
node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1117 = or(UInt<1>(0h1), _T_1116)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79
node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1121 :
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(source_ok_1, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81
node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h1), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84
node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = or(_T_1143, _T_1148)
node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = or(_T_1151, _T_1156)
node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1161 = cvt(_T_1160)
node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0)))
node _T_1163 = asSInt(_T_1162)
node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0)))
node _T_1165 = or(_T_1159, _T_1164)
node _T_1166 = and(_T_1149, _T_1157)
node _T_1167 = and(_T_1166, _T_1165)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
connect _legal_source_WIRE[2], _legal_source_T_2
node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0))
node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5)
wire _legal_source_WIRE_1 : UInt<2>
connect _legal_source_WIRE_1, _legal_source_T_7
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1171 :
node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1172
connect _WIRE_4[1], _T_1173
connect _WIRE_4[2], _T_1174
node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0))
node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1179 = or(_T_1176, _T_1177)
node _T_1180 = or(_T_1179, _T_1178)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1180
node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = or(UInt<1>(0h0), _T_1183)
node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1191 = cvt(_T_1190)
node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000)))
node _T_1193 = asSInt(_T_1192)
node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0)))
node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1196 = cvt(_T_1195)
node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000)))
node _T_1198 = asSInt(_T_1197)
node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0)))
node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1201 = cvt(_T_1200)
node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000)))
node _T_1203 = asSInt(_T_1202)
node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0)))
node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1206 = cvt(_T_1205)
node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000)))
node _T_1208 = asSInt(_T_1207)
node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0)))
node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1216 = cvt(_T_1215)
node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000)))
node _T_1218 = asSInt(_T_1217)
node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0)))
node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1231 = cvt(_T_1230)
node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000)))
node _T_1233 = asSInt(_T_1232)
node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = or(_T_1189, _T_1194)
node _T_1236 = or(_T_1235, _T_1199)
node _T_1237 = or(_T_1236, _T_1204)
node _T_1238 = or(_T_1237, _T_1209)
node _T_1239 = or(_T_1238, _T_1214)
node _T_1240 = or(_T_1239, _T_1219)
node _T_1241 = or(_T_1240, _T_1224)
node _T_1242 = or(_T_1241, _T_1229)
node _T_1243 = or(_T_1242, _T_1234)
node _T_1244 = and(_T_1184, _T_1243)
node _T_1245 = or(UInt<1>(0h0), _T_1244)
node _T_1246 = and(_WIRE_5, _T_1245)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(address_ok, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(legal_source, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90
node _T_1263 = eq(io.in.b.bits.mask, mask_1)
node _T_1264 = asUInt(reset)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
when _T_1265 :
node _T_1266 = eq(_T_1263, UInt<1>(0h0))
when _T_1266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91
node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(_T_1267, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92
node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1271 :
node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = or(UInt<1>(0h0), _T_1274)
node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1277 = cvt(_T_1276)
node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000)))
node _T_1279 = asSInt(_T_1278)
node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0)))
node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1282 = cvt(_T_1281)
node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000)))
node _T_1284 = asSInt(_T_1283)
node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0)))
node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1287 = cvt(_T_1286)
node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000)))
node _T_1289 = asSInt(_T_1288)
node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0)))
node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1292 = cvt(_T_1291)
node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000)))
node _T_1294 = asSInt(_T_1293)
node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0)))
node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1297 = cvt(_T_1296)
node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000)))
node _T_1299 = asSInt(_T_1298)
node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0)))
node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1302 = cvt(_T_1301)
node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000)))
node _T_1304 = asSInt(_T_1303)
node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0)))
node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1307 = cvt(_T_1306)
node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000)))
node _T_1309 = asSInt(_T_1308)
node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0)))
node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1312 = cvt(_T_1311)
node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000)))
node _T_1314 = asSInt(_T_1313)
node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0)))
node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1317 = cvt(_T_1316)
node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000)))
node _T_1319 = asSInt(_T_1318)
node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0)))
node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1322 = cvt(_T_1321)
node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000)))
node _T_1324 = asSInt(_T_1323)
node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0)))
node _T_1326 = or(_T_1280, _T_1285)
node _T_1327 = or(_T_1326, _T_1290)
node _T_1328 = or(_T_1327, _T_1295)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1305)
node _T_1331 = or(_T_1330, _T_1310)
node _T_1332 = or(_T_1331, _T_1315)
node _T_1333 = or(_T_1332, _T_1320)
node _T_1334 = or(_T_1333, _T_1325)
node _T_1335 = and(_T_1275, _T_1334)
node _T_1336 = or(UInt<1>(0h0), _T_1335)
node _T_1337 = and(UInt<1>(0h0), _T_1336)
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(_T_1337, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(address_ok, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(legal_source, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1347 = asUInt(reset)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
when _T_1348 :
node _T_1349 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97
node _T_1354 = eq(io.in.b.bits.mask, mask_1)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98
node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99
node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1365 = and(_T_1363, _T_1364)
node _T_1366 = or(UInt<1>(0h0), _T_1365)
node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1368 = cvt(_T_1367)
node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000)))
node _T_1370 = asSInt(_T_1369)
node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0)))
node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1373 = cvt(_T_1372)
node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000)))
node _T_1375 = asSInt(_T_1374)
node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0)))
node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1378 = cvt(_T_1377)
node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000)))
node _T_1380 = asSInt(_T_1379)
node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0)))
node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1383 = cvt(_T_1382)
node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000)))
node _T_1385 = asSInt(_T_1384)
node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0)))
node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1388 = cvt(_T_1387)
node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000)))
node _T_1390 = asSInt(_T_1389)
node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0)))
node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1393 = cvt(_T_1392)
node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000)))
node _T_1395 = asSInt(_T_1394)
node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0)))
node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1398 = cvt(_T_1397)
node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000)))
node _T_1400 = asSInt(_T_1399)
node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0)))
node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1403 = cvt(_T_1402)
node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000)))
node _T_1405 = asSInt(_T_1404)
node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0)))
node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1408 = cvt(_T_1407)
node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000)))
node _T_1410 = asSInt(_T_1409)
node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0)))
node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1413 = cvt(_T_1412)
node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000)))
node _T_1415 = asSInt(_T_1414)
node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0)))
node _T_1417 = or(_T_1371, _T_1376)
node _T_1418 = or(_T_1417, _T_1381)
node _T_1419 = or(_T_1418, _T_1386)
node _T_1420 = or(_T_1419, _T_1391)
node _T_1421 = or(_T_1420, _T_1396)
node _T_1422 = or(_T_1421, _T_1401)
node _T_1423 = or(_T_1422, _T_1406)
node _T_1424 = or(_T_1423, _T_1411)
node _T_1425 = or(_T_1424, _T_1416)
node _T_1426 = and(_T_1366, _T_1425)
node _T_1427 = or(UInt<1>(0h0), _T_1426)
node _T_1428 = and(UInt<1>(0h0), _T_1427)
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(_T_1428, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(address_ok, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(legal_source, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104
node _T_1445 = eq(io.in.b.bits.mask, mask_1)
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105
node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1449 :
node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1452 = and(_T_1450, _T_1451)
node _T_1453 = or(UInt<1>(0h0), _T_1452)
node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1455 = cvt(_T_1454)
node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000)))
node _T_1457 = asSInt(_T_1456)
node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0)))
node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1460 = cvt(_T_1459)
node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000)))
node _T_1462 = asSInt(_T_1461)
node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0)))
node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1465 = cvt(_T_1464)
node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000)))
node _T_1467 = asSInt(_T_1466)
node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0)))
node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1470 = cvt(_T_1469)
node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000)))
node _T_1472 = asSInt(_T_1471)
node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0)))
node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1475 = cvt(_T_1474)
node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000)))
node _T_1477 = asSInt(_T_1476)
node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0)))
node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1480 = cvt(_T_1479)
node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000)))
node _T_1482 = asSInt(_T_1481)
node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0)))
node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1485 = cvt(_T_1484)
node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000)))
node _T_1487 = asSInt(_T_1486)
node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0)))
node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1490 = cvt(_T_1489)
node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000)))
node _T_1492 = asSInt(_T_1491)
node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0)))
node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1495 = cvt(_T_1494)
node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000)))
node _T_1497 = asSInt(_T_1496)
node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0)))
node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1500 = cvt(_T_1499)
node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000)))
node _T_1502 = asSInt(_T_1501)
node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0)))
node _T_1504 = or(_T_1458, _T_1463)
node _T_1505 = or(_T_1504, _T_1468)
node _T_1506 = or(_T_1505, _T_1473)
node _T_1507 = or(_T_1506, _T_1478)
node _T_1508 = or(_T_1507, _T_1483)
node _T_1509 = or(_T_1508, _T_1488)
node _T_1510 = or(_T_1509, _T_1493)
node _T_1511 = or(_T_1510, _T_1498)
node _T_1512 = or(_T_1511, _T_1503)
node _T_1513 = and(_T_1453, _T_1512)
node _T_1514 = or(UInt<1>(0h0), _T_1513)
node _T_1515 = and(UInt<1>(0h0), _T_1514)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(address_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(legal_source, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(_T_1528, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110
node _T_1532 = not(mask_1)
node _T_1533 = and(io.in.b.bits.mask, _T_1532)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111
node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1538 :
node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1541 = and(_T_1539, _T_1540)
node _T_1542 = or(UInt<1>(0h0), _T_1541)
node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1544 = cvt(_T_1543)
node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000)))
node _T_1546 = asSInt(_T_1545)
node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0)))
node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1549 = cvt(_T_1548)
node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000)))
node _T_1551 = asSInt(_T_1550)
node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0)))
node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1554 = cvt(_T_1553)
node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000)))
node _T_1556 = asSInt(_T_1555)
node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0)))
node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1559 = cvt(_T_1558)
node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000)))
node _T_1561 = asSInt(_T_1560)
node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0)))
node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1564 = cvt(_T_1563)
node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000)))
node _T_1566 = asSInt(_T_1565)
node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0)))
node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1574 = cvt(_T_1573)
node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000)))
node _T_1576 = asSInt(_T_1575)
node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0)))
node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1579 = cvt(_T_1578)
node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000)))
node _T_1581 = asSInt(_T_1580)
node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0)))
node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1584 = cvt(_T_1583)
node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000)))
node _T_1586 = asSInt(_T_1585)
node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0)))
node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1589 = cvt(_T_1588)
node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000)))
node _T_1591 = asSInt(_T_1590)
node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0)))
node _T_1593 = or(_T_1547, _T_1552)
node _T_1594 = or(_T_1593, _T_1557)
node _T_1595 = or(_T_1594, _T_1562)
node _T_1596 = or(_T_1595, _T_1567)
node _T_1597 = or(_T_1596, _T_1572)
node _T_1598 = or(_T_1597, _T_1577)
node _T_1599 = or(_T_1598, _T_1582)
node _T_1600 = or(_T_1599, _T_1587)
node _T_1601 = or(_T_1600, _T_1592)
node _T_1602 = and(_T_1542, _T_1601)
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = and(UInt<1>(0h0), _T_1603)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(address_ok, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(legal_source, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1614 = asUInt(reset)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
when _T_1615 :
node _T_1616 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(_T_1617, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116
node _T_1621 = eq(io.in.b.bits.mask, mask_1)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117
node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1625 :
node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1628 = and(_T_1626, _T_1627)
node _T_1629 = or(UInt<1>(0h0), _T_1628)
node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1631 = cvt(_T_1630)
node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000)))
node _T_1633 = asSInt(_T_1632)
node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0)))
node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1636 = cvt(_T_1635)
node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000)))
node _T_1638 = asSInt(_T_1637)
node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0)))
node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1641 = cvt(_T_1640)
node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000)))
node _T_1643 = asSInt(_T_1642)
node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1646 = cvt(_T_1645)
node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000)))
node _T_1648 = asSInt(_T_1647)
node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0)))
node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1651 = cvt(_T_1650)
node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000)))
node _T_1653 = asSInt(_T_1652)
node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0)))
node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1661 = cvt(_T_1660)
node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000)))
node _T_1663 = asSInt(_T_1662)
node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0)))
node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1666 = cvt(_T_1665)
node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000)))
node _T_1668 = asSInt(_T_1667)
node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0)))
node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1671 = cvt(_T_1670)
node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000)))
node _T_1673 = asSInt(_T_1672)
node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0)))
node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1676 = cvt(_T_1675)
node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000)))
node _T_1678 = asSInt(_T_1677)
node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0)))
node _T_1680 = or(_T_1634, _T_1639)
node _T_1681 = or(_T_1680, _T_1644)
node _T_1682 = or(_T_1681, _T_1649)
node _T_1683 = or(_T_1682, _T_1654)
node _T_1684 = or(_T_1683, _T_1659)
node _T_1685 = or(_T_1684, _T_1664)
node _T_1686 = or(_T_1685, _T_1669)
node _T_1687 = or(_T_1686, _T_1674)
node _T_1688 = or(_T_1687, _T_1679)
node _T_1689 = and(_T_1629, _T_1688)
node _T_1690 = or(UInt<1>(0h0), _T_1689)
node _T_1691 = and(UInt<1>(0h0), _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118
node _T_1695 = asUInt(reset)
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
when _T_1696 :
node _T_1697 = eq(address_ok, UInt<1>(0h0))
when _T_1697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1698 = asUInt(reset)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
when _T_1699 :
node _T_1700 = eq(legal_source, UInt<1>(0h0))
when _T_1700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1701 = asUInt(reset)
node _T_1702 = eq(_T_1701, UInt<1>(0h0))
when _T_1702 :
node _T_1703 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1705 = asUInt(reset)
node _T_1706 = eq(_T_1705, UInt<1>(0h0))
when _T_1706 :
node _T_1707 = eq(_T_1704, UInt<1>(0h0))
when _T_1707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122
node _T_1708 = eq(io.in.b.bits.mask, mask_1)
node _T_1709 = asUInt(reset)
node _T_1710 = eq(_T_1709, UInt<1>(0h0))
when _T_1710 :
node _T_1711 = eq(_T_1708, UInt<1>(0h0))
when _T_1711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123
node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1712 :
node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1715 = and(_T_1713, _T_1714)
node _T_1716 = or(UInt<1>(0h0), _T_1715)
node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1718 = cvt(_T_1717)
node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000)))
node _T_1720 = asSInt(_T_1719)
node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0)))
node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1723 = cvt(_T_1722)
node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000)))
node _T_1725 = asSInt(_T_1724)
node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0)))
node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1728 = cvt(_T_1727)
node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000)))
node _T_1730 = asSInt(_T_1729)
node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0)))
node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1733 = cvt(_T_1732)
node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000)))
node _T_1735 = asSInt(_T_1734)
node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0)))
node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1738 = cvt(_T_1737)
node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000)))
node _T_1740 = asSInt(_T_1739)
node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0)))
node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1743 = cvt(_T_1742)
node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000)))
node _T_1745 = asSInt(_T_1744)
node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0)))
node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1748 = cvt(_T_1747)
node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000)))
node _T_1750 = asSInt(_T_1749)
node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0)))
node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1753 = cvt(_T_1752)
node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000)))
node _T_1755 = asSInt(_T_1754)
node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0)))
node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1758 = cvt(_T_1757)
node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000)))
node _T_1760 = asSInt(_T_1759)
node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0)))
node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1721, _T_1726)
node _T_1768 = or(_T_1767, _T_1731)
node _T_1769 = or(_T_1768, _T_1736)
node _T_1770 = or(_T_1769, _T_1741)
node _T_1771 = or(_T_1770, _T_1746)
node _T_1772 = or(_T_1771, _T_1751)
node _T_1773 = or(_T_1772, _T_1756)
node _T_1774 = or(_T_1773, _T_1761)
node _T_1775 = or(_T_1774, _T_1766)
node _T_1776 = and(_T_1716, _T_1775)
node _T_1777 = or(UInt<1>(0h0), _T_1776)
node _T_1778 = and(UInt<1>(0h0), _T_1777)
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(address_ok, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1785 = asUInt(reset)
node _T_1786 = eq(_T_1785, UInt<1>(0h0))
when _T_1786 :
node _T_1787 = eq(legal_source, UInt<1>(0h0))
when _T_1787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1791 = eq(io.in.b.bits.mask, mask_1)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128
node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130
node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_8
connect _source_ok_WIRE_2[1], _source_ok_T_9
connect _source_ok_WIRE_2[2], _source_ok_T_10
node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1806 = cvt(_T_1805)
node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0)))
node _T_1808 = asSInt(_T_1807)
node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0)))
node _T_1810 = or(_T_1804, _T_1809)
node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1812 = eq(_T_1811, UInt<1>(0h0))
node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1814 = cvt(_T_1813)
node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0)))
node _T_1816 = asSInt(_T_1815)
node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0)))
node _T_1818 = or(_T_1812, _T_1817)
node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1820 = eq(_T_1819, UInt<1>(0h0))
node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1822 = cvt(_T_1821)
node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0)))
node _T_1824 = asSInt(_T_1823)
node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0)))
node _T_1826 = or(_T_1820, _T_1825)
node _T_1827 = and(_T_1810, _T_1818)
node _T_1828 = and(_T_1827, _T_1826)
node _T_1829 = asUInt(reset)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
when _T_1830 :
node _T_1831 = eq(_T_1828, UInt<1>(0h0))
when _T_1831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131
node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1832 :
node _T_1833 = asUInt(reset)
node _T_1834 = eq(_T_1833, UInt<1>(0h0))
when _T_1834 :
node _T_1835 = eq(address_ok_1, UInt<1>(0h0))
when _T_1835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1836 = asUInt(reset)
node _T_1837 = eq(_T_1836, UInt<1>(0h0))
when _T_1837 :
node _T_1838 = eq(source_ok_2, UInt<1>(0h0))
when _T_1838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1840 = asUInt(reset)
node _T_1841 = eq(_T_1840, UInt<1>(0h0))
when _T_1841 :
node _T_1842 = eq(_T_1839, UInt<1>(0h0))
when _T_1842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134
node _T_1843 = asUInt(reset)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
when _T_1844 :
node _T_1845 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136
node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1851 = asUInt(reset)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
when _T_1852 :
node _T_1853 = eq(_T_1850, UInt<1>(0h0))
when _T_1853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137
node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1854 :
node _T_1855 = asUInt(reset)
node _T_1856 = eq(_T_1855, UInt<1>(0h0))
when _T_1856 :
node _T_1857 = eq(address_ok_1, UInt<1>(0h0))
when _T_1857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1858 = asUInt(reset)
node _T_1859 = eq(_T_1858, UInt<1>(0h0))
when _T_1859 :
node _T_1860 = eq(source_ok_2, UInt<1>(0h0))
when _T_1860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1862 = asUInt(reset)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
when _T_1863 :
node _T_1864 = eq(_T_1861, UInt<1>(0h0))
when _T_1864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1869 = asUInt(reset)
node _T_1870 = eq(_T_1869, UInt<1>(0h0))
when _T_1870 :
node _T_1871 = eq(_T_1868, UInt<1>(0h0))
when _T_1871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142
node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1872 :
node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1875 = and(_T_1873, _T_1874)
node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1879 = or(_T_1876, _T_1877)
node _T_1880 = or(_T_1879, _T_1878)
node _T_1881 = and(_T_1875, _T_1880)
node _T_1882 = or(UInt<1>(0h0), _T_1881)
node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1885 = cvt(_T_1884)
node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000)))
node _T_1887 = asSInt(_T_1886)
node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0)))
node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1890 = cvt(_T_1889)
node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000)))
node _T_1892 = asSInt(_T_1891)
node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1895 = cvt(_T_1894)
node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000)))
node _T_1897 = asSInt(_T_1896)
node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0)))
node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1900 = cvt(_T_1899)
node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000)))
node _T_1902 = asSInt(_T_1901)
node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0)))
node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1905 = cvt(_T_1904)
node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000)))
node _T_1907 = asSInt(_T_1906)
node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0)))
node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1910 = cvt(_T_1909)
node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000)))
node _T_1912 = asSInt(_T_1911)
node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0)))
node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1915 = cvt(_T_1914)
node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000)))
node _T_1917 = asSInt(_T_1916)
node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0)))
node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1920 = cvt(_T_1919)
node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000)))
node _T_1922 = asSInt(_T_1921)
node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0)))
node _T_1924 = or(_T_1888, _T_1893)
node _T_1925 = or(_T_1924, _T_1898)
node _T_1926 = or(_T_1925, _T_1903)
node _T_1927 = or(_T_1926, _T_1908)
node _T_1928 = or(_T_1927, _T_1913)
node _T_1929 = or(_T_1928, _T_1918)
node _T_1930 = or(_T_1929, _T_1923)
node _T_1931 = and(_T_1883, _T_1930)
node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1933 = or(UInt<1>(0h0), _T_1932)
node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1935 = cvt(_T_1934)
node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000)))
node _T_1937 = asSInt(_T_1936)
node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0)))
node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1940 = cvt(_T_1939)
node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000)))
node _T_1942 = asSInt(_T_1941)
node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0)))
node _T_1944 = or(_T_1938, _T_1943)
node _T_1945 = and(_T_1933, _T_1944)
node _T_1946 = or(UInt<1>(0h0), _T_1931)
node _T_1947 = or(_T_1946, _T_1945)
node _T_1948 = and(_T_1882, _T_1947)
node _T_1949 = asUInt(reset)
node _T_1950 = eq(_T_1949, UInt<1>(0h0))
when _T_1950 :
node _T_1951 = eq(_T_1948, UInt<1>(0h0))
when _T_1951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143
node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_1952
connect _WIRE_6[1], _T_1953
connect _WIRE_6[2], _T_1954
node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0))
node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = or(_T_1956, _T_1957)
node _T_1960 = or(_T_1959, _T_1958)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1960
node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1963 = and(_T_1961, _T_1962)
node _T_1964 = or(UInt<1>(0h0), _T_1963)
node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1966 = cvt(_T_1965)
node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000)))
node _T_1968 = asSInt(_T_1967)
node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0)))
node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1971 = cvt(_T_1970)
node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000)))
node _T_1973 = asSInt(_T_1972)
node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0)))
node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1976 = cvt(_T_1975)
node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000)))
node _T_1978 = asSInt(_T_1977)
node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0)))
node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1981 = cvt(_T_1980)
node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000)))
node _T_1983 = asSInt(_T_1982)
node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0)))
node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1986 = cvt(_T_1985)
node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000)))
node _T_1988 = asSInt(_T_1987)
node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0)))
node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1991 = cvt(_T_1990)
node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000)))
node _T_1993 = asSInt(_T_1992)
node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0)))
node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1996 = cvt(_T_1995)
node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000)))
node _T_1998 = asSInt(_T_1997)
node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0)))
node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2001 = cvt(_T_2000)
node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000)))
node _T_2003 = asSInt(_T_2002)
node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0)))
node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2006 = cvt(_T_2005)
node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000)))
node _T_2008 = asSInt(_T_2007)
node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0)))
node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2011 = cvt(_T_2010)
node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000)))
node _T_2013 = asSInt(_T_2012)
node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0)))
node _T_2015 = or(_T_1969, _T_1974)
node _T_2016 = or(_T_2015, _T_1979)
node _T_2017 = or(_T_2016, _T_1984)
node _T_2018 = or(_T_2017, _T_1989)
node _T_2019 = or(_T_2018, _T_1994)
node _T_2020 = or(_T_2019, _T_1999)
node _T_2021 = or(_T_2020, _T_2004)
node _T_2022 = or(_T_2021, _T_2009)
node _T_2023 = or(_T_2022, _T_2014)
node _T_2024 = and(_T_1964, _T_2023)
node _T_2025 = or(UInt<1>(0h0), _T_2024)
node _T_2026 = and(_WIRE_7, _T_2025)
node _T_2027 = asUInt(reset)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
when _T_2028 :
node _T_2029 = eq(_T_2026, UInt<1>(0h0))
when _T_2029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144
node _T_2030 = asUInt(reset)
node _T_2031 = eq(_T_2030, UInt<1>(0h0))
when _T_2031 :
node _T_2032 = eq(source_ok_2, UInt<1>(0h0))
when _T_2032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2034 = asUInt(reset)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
when _T_2035 :
node _T_2036 = eq(_T_2033, UInt<1>(0h0))
when _T_2036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146
node _T_2037 = asUInt(reset)
node _T_2038 = eq(_T_2037, UInt<1>(0h0))
when _T_2038 :
node _T_2039 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2041 = asUInt(reset)
node _T_2042 = eq(_T_2041, UInt<1>(0h0))
when _T_2042 :
node _T_2043 = eq(_T_2040, UInt<1>(0h0))
when _T_2043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148
node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2045 = asUInt(reset)
node _T_2046 = eq(_T_2045, UInt<1>(0h0))
when _T_2046 :
node _T_2047 = eq(_T_2044, UInt<1>(0h0))
when _T_2047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149
node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2048 :
node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2051 = and(_T_2049, _T_2050)
node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2055 = or(_T_2052, _T_2053)
node _T_2056 = or(_T_2055, _T_2054)
node _T_2057 = and(_T_2051, _T_2056)
node _T_2058 = or(UInt<1>(0h0), _T_2057)
node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2096 = cvt(_T_2095)
node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000)))
node _T_2098 = asSInt(_T_2097)
node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0)))
node _T_2100 = or(_T_2064, _T_2069)
node _T_2101 = or(_T_2100, _T_2074)
node _T_2102 = or(_T_2101, _T_2079)
node _T_2103 = or(_T_2102, _T_2084)
node _T_2104 = or(_T_2103, _T_2089)
node _T_2105 = or(_T_2104, _T_2094)
node _T_2106 = or(_T_2105, _T_2099)
node _T_2107 = and(_T_2059, _T_2106)
node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2109 = or(UInt<1>(0h0), _T_2108)
node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2111 = cvt(_T_2110)
node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000)))
node _T_2113 = asSInt(_T_2112)
node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0)))
node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2116 = cvt(_T_2115)
node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000)))
node _T_2118 = asSInt(_T_2117)
node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0)))
node _T_2120 = or(_T_2114, _T_2119)
node _T_2121 = and(_T_2109, _T_2120)
node _T_2122 = or(UInt<1>(0h0), _T_2107)
node _T_2123 = or(_T_2122, _T_2121)
node _T_2124 = and(_T_2058, _T_2123)
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150
node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2128
connect _WIRE_8[1], _T_2129
connect _WIRE_8[2], _T_2130
node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0))
node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2135 = or(_T_2132, _T_2133)
node _T_2136 = or(_T_2135, _T_2134)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2136
node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2139 = and(_T_2137, _T_2138)
node _T_2140 = or(UInt<1>(0h0), _T_2139)
node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2142 = cvt(_T_2141)
node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000)))
node _T_2144 = asSInt(_T_2143)
node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0)))
node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2147 = cvt(_T_2146)
node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000)))
node _T_2149 = asSInt(_T_2148)
node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0)))
node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2152 = cvt(_T_2151)
node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000)))
node _T_2154 = asSInt(_T_2153)
node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0)))
node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2157 = cvt(_T_2156)
node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000)))
node _T_2159 = asSInt(_T_2158)
node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0)))
node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2162 = cvt(_T_2161)
node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000)))
node _T_2164 = asSInt(_T_2163)
node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0)))
node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2167 = cvt(_T_2166)
node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000)))
node _T_2169 = asSInt(_T_2168)
node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0)))
node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2172 = cvt(_T_2171)
node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000)))
node _T_2174 = asSInt(_T_2173)
node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0)))
node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2177 = cvt(_T_2176)
node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000)))
node _T_2179 = asSInt(_T_2178)
node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0)))
node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2182 = cvt(_T_2181)
node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000)))
node _T_2184 = asSInt(_T_2183)
node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0)))
node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2187 = cvt(_T_2186)
node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000)))
node _T_2189 = asSInt(_T_2188)
node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0)))
node _T_2191 = or(_T_2145, _T_2150)
node _T_2192 = or(_T_2191, _T_2155)
node _T_2193 = or(_T_2192, _T_2160)
node _T_2194 = or(_T_2193, _T_2165)
node _T_2195 = or(_T_2194, _T_2170)
node _T_2196 = or(_T_2195, _T_2175)
node _T_2197 = or(_T_2196, _T_2180)
node _T_2198 = or(_T_2197, _T_2185)
node _T_2199 = or(_T_2198, _T_2190)
node _T_2200 = and(_T_2140, _T_2199)
node _T_2201 = or(UInt<1>(0h0), _T_2200)
node _T_2202 = and(_WIRE_9, _T_2201)
node _T_2203 = asUInt(reset)
node _T_2204 = eq(_T_2203, UInt<1>(0h0))
when _T_2204 :
node _T_2205 = eq(_T_2202, UInt<1>(0h0))
when _T_2205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(source_ok_2, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153
node _T_2213 = asUInt(reset)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
when _T_2214 :
node _T_2215 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2217 = asUInt(reset)
node _T_2218 = eq(_T_2217, UInt<1>(0h0))
when _T_2218 :
node _T_2219 = eq(_T_2216, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155
node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = asUInt(reset)
node _T_2222 = eq(_T_2221, UInt<1>(0h0))
when _T_2222 :
node _T_2223 = eq(address_ok_1, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(source_ok_2, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2231 = asUInt(reset)
node _T_2232 = eq(_T_2231, UInt<1>(0h0))
when _T_2232 :
node _T_2233 = eq(_T_2230, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159
node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2235 = asUInt(reset)
node _T_2236 = eq(_T_2235, UInt<1>(0h0))
when _T_2236 :
node _T_2237 = eq(_T_2234, UInt<1>(0h0))
when _T_2237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160
node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2238 :
node _T_2239 = asUInt(reset)
node _T_2240 = eq(_T_2239, UInt<1>(0h0))
when _T_2240 :
node _T_2241 = eq(address_ok_1, UInt<1>(0h0))
when _T_2241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(source_ok_2, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2245 = asUInt(reset)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
when _T_2246 :
node _T_2247 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164
node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2252 :
node _T_2253 = asUInt(reset)
node _T_2254 = eq(_T_2253, UInt<1>(0h0))
when _T_2254 :
node _T_2255 = eq(address_ok_1, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
node _T_2258 = eq(source_ok_2, UInt<1>(0h0))
when _T_2258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2259 = asUInt(reset)
node _T_2260 = eq(_T_2259, UInt<1>(0h0))
when _T_2260 :
node _T_2261 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2263 = asUInt(reset)
node _T_2264 = eq(_T_2263, UInt<1>(0h0))
when _T_2264 :
node _T_2265 = eq(_T_2262, UInt<1>(0h0))
when _T_2265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168
node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2267 = asUInt(reset)
node _T_2268 = eq(_T_2267, UInt<1>(0h0))
when _T_2268 :
node _T_2269 = eq(_T_2266, UInt<1>(0h0))
when _T_2269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2273 = eq(a_first, UInt<1>(0h0))
node _T_2274 = and(io.in.a.valid, _T_2273)
when _T_2274 :
node _T_2275 = eq(io.in.a.bits.opcode, opcode)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171
node _T_2279 = eq(io.in.a.bits.param, param)
node _T_2280 = asUInt(reset)
node _T_2281 = eq(_T_2280, UInt<1>(0h0))
when _T_2281 :
node _T_2282 = eq(_T_2279, UInt<1>(0h0))
when _T_2282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172
node _T_2283 = eq(io.in.a.bits.size, size)
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
node _T_2286 = eq(_T_2283, UInt<1>(0h0))
when _T_2286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173
node _T_2287 = eq(io.in.a.bits.source, source)
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
node _T_2290 = eq(_T_2287, UInt<1>(0h0))
when _T_2290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174
node _T_2291 = eq(io.in.a.bits.address, address)
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
node _T_2294 = eq(_T_2291, UInt<1>(0h0))
when _T_2294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175
node _T_2295 = and(io.in.a.ready, io.in.a.valid)
node _T_2296 = and(_T_2295, a_first)
when _T_2296 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2297 = eq(d_first, UInt<1>(0h0))
node _T_2298 = and(io.in.d.valid, _T_2297)
when _T_2298 :
node _T_2299 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176
node _T_2303 = eq(io.in.d.bits.param, param_1)
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
node _T_2306 = eq(_T_2303, UInt<1>(0h0))
when _T_2306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177
node _T_2307 = eq(io.in.d.bits.size, size_1)
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
node _T_2310 = eq(_T_2307, UInt<1>(0h0))
when _T_2310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178
node _T_2311 = eq(io.in.d.bits.source, source_1)
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
node _T_2314 = eq(_T_2311, UInt<1>(0h0))
when _T_2314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179
node _T_2315 = eq(io.in.d.bits.sink, sink)
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
node _T_2318 = eq(_T_2315, UInt<1>(0h0))
when _T_2318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180
node _T_2319 = eq(io.in.d.bits.denied, denied)
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
node _T_2322 = eq(_T_2319, UInt<1>(0h0))
when _T_2322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181
node _T_2323 = and(io.in.d.ready, io.in.d.valid)
node _T_2324 = and(_T_2323, d_first)
when _T_2324 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2325 = eq(b_first, UInt<1>(0h0))
node _T_2326 = and(io.in.b.valid, _T_2325)
when _T_2326 :
node _T_2327 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2328 = asUInt(reset)
node _T_2329 = eq(_T_2328, UInt<1>(0h0))
when _T_2329 :
node _T_2330 = eq(_T_2327, UInt<1>(0h0))
when _T_2330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182
node _T_2331 = eq(io.in.b.bits.param, param_2)
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(_T_2331, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183
node _T_2335 = eq(io.in.b.bits.size, size_2)
node _T_2336 = asUInt(reset)
node _T_2337 = eq(_T_2336, UInt<1>(0h0))
when _T_2337 :
node _T_2338 = eq(_T_2335, UInt<1>(0h0))
when _T_2338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184
node _T_2339 = eq(io.in.b.bits.source, source_2)
node _T_2340 = asUInt(reset)
node _T_2341 = eq(_T_2340, UInt<1>(0h0))
when _T_2341 :
node _T_2342 = eq(_T_2339, UInt<1>(0h0))
when _T_2342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185
node _T_2343 = eq(io.in.b.bits.address, address_1)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186
node _T_2347 = and(io.in.b.ready, io.in.b.valid)
node _T_2348 = and(_T_2347, b_first)
when _T_2348 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2349 = eq(c_first, UInt<1>(0h0))
node _T_2350 = and(io.in.c.valid, _T_2349)
when _T_2350 :
node _T_2351 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2352 = asUInt(reset)
node _T_2353 = eq(_T_2352, UInt<1>(0h0))
when _T_2353 :
node _T_2354 = eq(_T_2351, UInt<1>(0h0))
when _T_2354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187
node _T_2355 = eq(io.in.c.bits.param, param_3)
node _T_2356 = asUInt(reset)
node _T_2357 = eq(_T_2356, UInt<1>(0h0))
when _T_2357 :
node _T_2358 = eq(_T_2355, UInt<1>(0h0))
when _T_2358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188
node _T_2359 = eq(io.in.c.bits.size, size_3)
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(_T_2359, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189
node _T_2363 = eq(io.in.c.bits.source, source_3)
node _T_2364 = asUInt(reset)
node _T_2365 = eq(_T_2364, UInt<1>(0h0))
when _T_2365 :
node _T_2366 = eq(_T_2363, UInt<1>(0h0))
when _T_2366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190
node _T_2367 = eq(io.in.c.bits.address, address_2)
node _T_2368 = asUInt(reset)
node _T_2369 = eq(_T_2368, UInt<1>(0h0))
when _T_2369 :
node _T_2370 = eq(_T_2367, UInt<1>(0h0))
when _T_2370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191
node _T_2371 = and(io.in.c.ready, io.in.c.valid)
node _T_2372 = and(_T_2371, c_first)
when _T_2372 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<3>
connect a_set, UInt<3>(0h0)
wire a_set_wo_ready : UInt<3>
connect a_set_wo_ready, UInt<3>(0h0)
wire a_opcodes_set : UInt<12>
connect a_opcodes_set, UInt<12>(0h0)
wire a_sizes_set : UInt<24>
connect a_sizes_set, UInt<24>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2373 = and(io.in.a.valid, a_first_1)
node _T_2374 = and(_T_2373, UInt<1>(0h1))
when _T_2374 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2375 = and(io.in.a.ready, io.in.a.valid)
node _T_2376 = and(_T_2375, a_first_1)
node _T_2377 = and(_T_2376, UInt<1>(0h1))
when _T_2377 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2378 = dshr(inflight, io.in.a.bits.source)
node _T_2379 = bits(_T_2378, 0, 0)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
node _T_2381 = asUInt(reset)
node _T_2382 = eq(_T_2381, UInt<1>(0h0))
when _T_2382 :
node _T_2383 = eq(_T_2380, UInt<1>(0h0))
when _T_2383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<3>
connect d_clr, UInt<3>(0h0)
wire d_clr_wo_ready : UInt<3>
connect d_clr_wo_ready, UInt<3>(0h0)
wire d_opcodes_clr : UInt<12>
connect d_opcodes_clr, UInt<12>(0h0)
wire d_sizes_clr : UInt<24>
connect d_sizes_clr, UInt<24>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2384 = and(io.in.d.valid, d_first_1)
node _T_2385 = and(_T_2384, UInt<1>(0h1))
node _T_2386 = eq(d_release_ack, UInt<1>(0h0))
node _T_2387 = and(_T_2385, _T_2386)
when _T_2387 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2388 = and(io.in.d.ready, io.in.d.valid)
node _T_2389 = and(_T_2388, d_first_1)
node _T_2390 = and(_T_2389, UInt<1>(0h1))
node _T_2391 = eq(d_release_ack, UInt<1>(0h0))
node _T_2392 = and(_T_2390, _T_2391)
when _T_2392 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2393 = and(io.in.d.valid, d_first_1)
node _T_2394 = and(_T_2393, UInt<1>(0h1))
node _T_2395 = eq(d_release_ack, UInt<1>(0h0))
node _T_2396 = and(_T_2394, _T_2395)
when _T_2396 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2397 = dshr(inflight, io.in.d.bits.source)
node _T_2398 = bits(_T_2397, 0, 0)
node _T_2399 = or(_T_2398, same_cycle_resp)
node _T_2400 = asUInt(reset)
node _T_2401 = eq(_T_2400, UInt<1>(0h0))
when _T_2401 :
node _T_2402 = eq(_T_2399, UInt<1>(0h0))
when _T_2402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2405 = or(_T_2403, _T_2404)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194
node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195
else :
node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2415 = or(_T_2413, _T_2414)
node _T_2416 = asUInt(reset)
node _T_2417 = eq(_T_2416, UInt<1>(0h0))
when _T_2417 :
node _T_2418 = eq(_T_2415, UInt<1>(0h0))
when _T_2418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196
node _T_2419 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2420 = asUInt(reset)
node _T_2421 = eq(_T_2420, UInt<1>(0h0))
when _T_2421 :
node _T_2422 = eq(_T_2419, UInt<1>(0h0))
when _T_2422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197
node _T_2423 = and(io.in.d.valid, d_first_1)
node _T_2424 = and(_T_2423, a_first_1)
node _T_2425 = and(_T_2424, io.in.a.valid)
node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2427 = and(_T_2425, _T_2426)
node _T_2428 = eq(d_release_ack, UInt<1>(0h0))
node _T_2429 = and(_T_2427, _T_2428)
when _T_2429 :
node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2431 = or(_T_2430, io.in.a.ready)
node _T_2432 = asUInt(reset)
node _T_2433 = eq(_T_2432, UInt<1>(0h0))
when _T_2433 :
node _T_2434 = eq(_T_2431, UInt<1>(0h0))
when _T_2434 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198
node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2436 = orr(a_set_wo_ready)
node _T_2437 = eq(_T_2436, UInt<1>(0h0))
node _T_2438 = or(_T_2435, _T_2437)
node _T_2439 = asUInt(reset)
node _T_2440 = eq(_T_2439, UInt<1>(0h0))
when _T_2440 :
node _T_2441 = eq(_T_2438, UInt<1>(0h0))
when _T_2441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_118
node _T_2442 = orr(inflight)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2445 = or(_T_2443, _T_2444)
node _T_2446 = lt(watchdog, plusarg_reader.out)
node _T_2447 = or(_T_2445, _T_2446)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2451 = and(io.in.a.ready, io.in.a.valid)
node _T_2452 = and(io.in.d.ready, io.in.d.valid)
node _T_2453 = or(_T_2451, _T_2452)
when _T_2453 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<3>
connect c_set, UInt<3>(0h0)
wire c_set_wo_ready : UInt<3>
connect c_set_wo_ready, UInt<3>(0h0)
wire c_opcodes_set : UInt<12>
connect c_opcodes_set, UInt<12>(0h0)
wire c_sizes_set : UInt<24>
connect c_sizes_set, UInt<24>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2454 = and(io.in.c.valid, c_first_1)
node _T_2455 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2456 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2457 = and(_T_2455, _T_2456)
node _T_2458 = and(_T_2454, _T_2457)
when _T_2458 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2459 = and(io.in.c.ready, io.in.c.valid)
node _T_2460 = and(_T_2459, c_first_1)
node _T_2461 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2462 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2463 = and(_T_2461, _T_2462)
node _T_2464 = and(_T_2460, _T_2463)
when _T_2464 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2465 = dshr(inflight_1, io.in.c.bits.source)
node _T_2466 = bits(_T_2465, 0, 0)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = asUInt(reset)
node _T_2469 = eq(_T_2468, UInt<1>(0h0))
when _T_2469 :
node _T_2470 = eq(_T_2467, UInt<1>(0h0))
when _T_2470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<3>
connect d_clr_1, UInt<3>(0h0)
wire d_clr_wo_ready_1 : UInt<3>
connect d_clr_wo_ready_1, UInt<3>(0h0)
wire d_opcodes_clr_1 : UInt<12>
connect d_opcodes_clr_1, UInt<12>(0h0)
wire d_sizes_clr_1 : UInt<24>
connect d_sizes_clr_1, UInt<24>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2471 = and(io.in.d.valid, d_first_2)
node _T_2472 = and(_T_2471, UInt<1>(0h1))
node _T_2473 = and(_T_2472, d_release_ack_1)
when _T_2473 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2474 = and(io.in.d.ready, io.in.d.valid)
node _T_2475 = and(_T_2474, d_first_2)
node _T_2476 = and(_T_2475, UInt<1>(0h1))
node _T_2477 = and(_T_2476, d_release_ack_1)
when _T_2477 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2478 = and(io.in.d.valid, d_first_2)
node _T_2479 = and(_T_2478, UInt<1>(0h1))
node _T_2480 = and(_T_2479, d_release_ack_1)
when _T_2480 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2481 = dshr(inflight_1, io.in.d.bits.source)
node _T_2482 = bits(_T_2481, 0, 0)
node _T_2483 = or(_T_2482, same_cycle_resp_1)
node _T_2484 = asUInt(reset)
node _T_2485 = eq(_T_2484, UInt<1>(0h0))
when _T_2485 :
node _T_2486 = eq(_T_2483, UInt<1>(0h0))
when _T_2486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2488 = asUInt(reset)
node _T_2489 = eq(_T_2488, UInt<1>(0h0))
when _T_2489 :
node _T_2490 = eq(_T_2487, UInt<1>(0h0))
when _T_2490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203
else :
node _T_2491 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2492 = asUInt(reset)
node _T_2493 = eq(_T_2492, UInt<1>(0h0))
when _T_2493 :
node _T_2494 = eq(_T_2491, UInt<1>(0h0))
when _T_2494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204
node _T_2495 = and(io.in.d.valid, d_first_2)
node _T_2496 = and(_T_2495, c_first_1)
node _T_2497 = and(_T_2496, io.in.c.valid)
node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2499 = and(_T_2497, _T_2498)
node _T_2500 = and(_T_2499, d_release_ack_1)
node _T_2501 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2502 = and(_T_2500, _T_2501)
when _T_2502 :
node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2504 = or(_T_2503, io.in.c.ready)
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(_T_2504, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205
node _T_2508 = orr(c_set_wo_ready)
when _T_2508 :
node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_119
node _T_2513 = orr(inflight_1)
node _T_2514 = eq(_T_2513, UInt<1>(0h0))
node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2516 = or(_T_2514, _T_2515)
node _T_2517 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2518 = or(_T_2516, _T_2517)
node _T_2519 = asUInt(reset)
node _T_2520 = eq(_T_2519, UInt<1>(0h0))
when _T_2520 :
node _T_2521 = eq(_T_2518, UInt<1>(0h0))
when _T_2521 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2522 = and(io.in.c.ready, io.in.c.valid)
node _T_2523 = and(io.in.d.ready, io.in.d.valid)
node _T_2524 = or(_T_2522, _T_2523)
when _T_2524 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2525 = and(io.in.d.ready, io.in.d.valid)
node _T_2526 = and(_T_2525, d_first_3)
node _T_2527 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2528 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
node _T_2530 = and(_T_2527, _T_2529)
node _T_2531 = and(_T_2526, _T_2530)
when _T_2531 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2532 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2533 = bits(_T_2532, 0, 0)
node _T_2534 = eq(_T_2533, UInt<1>(0h0))
node _T_2535 = asUInt(reset)
node _T_2536 = eq(_T_2535, UInt<1>(0h0))
when _T_2536 :
node _T_2537 = eq(_T_2534, UInt<1>(0h0))
when _T_2537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2538 = and(io.in.e.ready, io.in.e.valid)
node _T_2539 = and(_T_2538, UInt<1>(0h1))
node _T_2540 = and(_T_2539, UInt<1>(0h1))
when _T_2540 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2541 = or(d_set, inflight_2)
node _T_2542 = dshr(_T_2541, io.in.e.bits.sink)
node _T_2543 = bits(_T_2542, 0, 0)
node _T_2544 = asUInt(reset)
node _T_2545 = eq(_T_2544, UInt<1>(0h0))
when _T_2545 :
node _T_2546 = eq(_T_2543, UInt<1>(0h0))
when _T_2546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_120 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_121 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_57( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71]
assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71]
assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31]
wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73]
wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31]
wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31]
wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31]
wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [1:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [1:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [2:0] inflight; // @[Monitor.scala:614:27]
reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [23:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] a_set; // @[Monitor.scala:626:34]
wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [23:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69]
wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101]
wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69]
wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65]
wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99]
wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67]
wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99]
wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35]
wire [3:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2:0] d_clr; // @[Monitor.scala:664:34]
wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46]
wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2:0] inflight_1; // @[Monitor.scala:726:35]
reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] c_set; // @[Monitor.scala:738:34]
wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [23:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35]
wire [3:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [2:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35]
assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module AMOALU :
input clock : Clock
input reset : Reset
output io : { flip mask : UInt<8>, flip cmd : UInt<5>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>, out_unmasked : UInt<64>}
node _max_T = eq(io.cmd, UInt<4>(0hd))
node _max_T_1 = eq(io.cmd, UInt<4>(0hf))
node max = or(_max_T, _max_T_1)
node _min_T = eq(io.cmd, UInt<4>(0hc))
node _min_T_1 = eq(io.cmd, UInt<4>(0he))
node min = or(_min_T, _min_T_1)
node add = eq(io.cmd, UInt<4>(0h8))
node _logic_and_T = eq(io.cmd, UInt<4>(0ha))
node _logic_and_T_1 = eq(io.cmd, UInt<4>(0hb))
node logic_and = or(_logic_and_T, _logic_and_T_1)
node _logic_xor_T = eq(io.cmd, UInt<4>(0h9))
node _logic_xor_T_1 = eq(io.cmd, UInt<4>(0ha))
node logic_xor = or(_logic_xor_T, _logic_xor_T_1)
node _adder_out_mask_T = bits(io.mask, 3, 3)
node _adder_out_mask_T_1 = eq(_adder_out_mask_T, UInt<1>(0h0))
node _adder_out_mask_T_2 = shl(_adder_out_mask_T_1, 31)
node _adder_out_mask_T_3 = or(UInt<64>(0h0), _adder_out_mask_T_2)
node adder_out_mask = not(_adder_out_mask_T_3)
node _adder_out_T = and(io.lhs, adder_out_mask)
node _adder_out_T_1 = and(io.rhs, adder_out_mask)
node _adder_out_T_2 = add(_adder_out_T, _adder_out_T_1)
node adder_out = tail(_adder_out_T_2, 1)
node _less_T = bits(io.mask, 4, 4)
node less_signed_mask = xor(UInt<4>(0hc), UInt<4>(0he))
node _less_signed_T = and(io.cmd, less_signed_mask)
node _less_signed_T_1 = and(UInt<4>(0hc), less_signed_mask)
node less_signed = eq(_less_signed_T, _less_signed_T_1)
node _less_T_1 = bits(io.lhs, 63, 63)
node _less_T_2 = bits(io.rhs, 63, 63)
node _less_T_3 = eq(_less_T_1, _less_T_2)
node _less_T_4 = bits(io.lhs, 63, 32)
node _less_T_5 = bits(io.rhs, 63, 32)
node _less_T_6 = lt(_less_T_4, _less_T_5)
node _less_T_7 = bits(io.lhs, 63, 32)
node _less_T_8 = bits(io.rhs, 63, 32)
node _less_T_9 = eq(_less_T_7, _less_T_8)
node _less_T_10 = bits(io.lhs, 31, 0)
node _less_T_11 = bits(io.rhs, 31, 0)
node _less_T_12 = lt(_less_T_10, _less_T_11)
node _less_T_13 = and(_less_T_9, _less_T_12)
node _less_T_14 = or(_less_T_6, _less_T_13)
node _less_T_15 = bits(io.lhs, 63, 63)
node _less_T_16 = bits(io.rhs, 63, 63)
node _less_T_17 = mux(less_signed, _less_T_15, _less_T_16)
node _less_T_18 = mux(_less_T_3, _less_T_14, _less_T_17)
node _less_T_19 = bits(io.mask, 2, 2)
node less_signed_mask_1 = xor(UInt<4>(0hc), UInt<4>(0he))
node _less_signed_T_2 = and(io.cmd, less_signed_mask_1)
node _less_signed_T_3 = and(UInt<4>(0hc), less_signed_mask_1)
node less_signed_1 = eq(_less_signed_T_2, _less_signed_T_3)
node _less_T_20 = bits(io.lhs, 31, 31)
node _less_T_21 = bits(io.rhs, 31, 31)
node _less_T_22 = eq(_less_T_20, _less_T_21)
node _less_T_23 = bits(io.lhs, 31, 0)
node _less_T_24 = bits(io.rhs, 31, 0)
node _less_T_25 = lt(_less_T_23, _less_T_24)
node _less_T_26 = bits(io.lhs, 31, 31)
node _less_T_27 = bits(io.rhs, 31, 31)
node _less_T_28 = mux(less_signed_1, _less_T_26, _less_T_27)
node _less_T_29 = mux(_less_T_22, _less_T_25, _less_T_28)
node less = mux(_less_T, _less_T_18, _less_T_29)
node _minmax_T = mux(less, min, max)
node minmax = mux(_minmax_T, io.lhs, io.rhs)
node _logic_T = and(io.lhs, io.rhs)
node _logic_T_1 = mux(logic_and, _logic_T, UInt<1>(0h0))
node _logic_T_2 = xor(io.lhs, io.rhs)
node _logic_T_3 = mux(logic_xor, _logic_T_2, UInt<1>(0h0))
node logic = or(_logic_T_1, _logic_T_3)
node _out_T = or(logic_and, logic_xor)
node _out_T_1 = mux(_out_T, logic, minmax)
node out = mux(add, adder_out, _out_T_1)
node _wmask_T = bits(io.mask, 0, 0)
node _wmask_T_1 = bits(io.mask, 1, 1)
node _wmask_T_2 = bits(io.mask, 2, 2)
node _wmask_T_3 = bits(io.mask, 3, 3)
node _wmask_T_4 = bits(io.mask, 4, 4)
node _wmask_T_5 = bits(io.mask, 5, 5)
node _wmask_T_6 = bits(io.mask, 6, 6)
node _wmask_T_7 = bits(io.mask, 7, 7)
node _wmask_T_8 = mux(_wmask_T, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_9 = mux(_wmask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_10 = mux(_wmask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_11 = mux(_wmask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_12 = mux(_wmask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_13 = mux(_wmask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_14 = mux(_wmask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _wmask_T_15 = mux(_wmask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node wmask_lo_lo = cat(_wmask_T_9, _wmask_T_8)
node wmask_lo_hi = cat(_wmask_T_11, _wmask_T_10)
node wmask_lo = cat(wmask_lo_hi, wmask_lo_lo)
node wmask_hi_lo = cat(_wmask_T_13, _wmask_T_12)
node wmask_hi_hi = cat(_wmask_T_15, _wmask_T_14)
node wmask_hi = cat(wmask_hi_hi, wmask_hi_lo)
node wmask = cat(wmask_hi, wmask_lo)
node _io_out_T = and(wmask, out)
node _io_out_T_1 = not(wmask)
node _io_out_T_2 = and(_io_out_T_1, io.lhs)
node _io_out_T_3 = or(_io_out_T, _io_out_T_2)
connect io.out, _io_out_T_3
connect io.out_unmasked, out | module AMOALU( // @[AMOALU.scala:54:7]
input clock, // @[AMOALU.scala:54:7]
input reset, // @[AMOALU.scala:54:7]
input [7:0] io_mask, // @[AMOALU.scala:58:14]
input [4:0] io_cmd, // @[AMOALU.scala:58:14]
input [63:0] io_lhs, // @[AMOALU.scala:58:14]
input [63:0] io_rhs, // @[AMOALU.scala:58:14]
output [63:0] io_out // @[AMOALU.scala:58:14]
);
wire [7:0] io_mask_0 = io_mask; // @[AMOALU.scala:54:7]
wire [4:0] io_cmd_0 = io_cmd; // @[AMOALU.scala:54:7]
wire [63:0] io_lhs_0 = io_lhs; // @[AMOALU.scala:54:7]
wire [63:0] io_rhs_0 = io_rhs; // @[AMOALU.scala:54:7]
wire [3:0] less_signed_mask = 4'h2; // @[AMOALU.scala:88:29]
wire [3:0] less_signed_mask_1 = 4'h2; // @[AMOALU.scala:88:29]
wire [3:0] _less_signed_T_1 = 4'h0; // @[AMOALU.scala:89:39]
wire [3:0] _less_signed_T_3 = 4'h0; // @[AMOALU.scala:89:39]
wire [63:0] _io_out_T_3; // @[AMOALU.scala:107:25]
wire [63:0] out; // @[AMOALU.scala:102:8]
wire [63:0] io_out_0; // @[AMOALU.scala:54:7]
wire [63:0] io_out_unmasked; // @[AMOALU.scala:54:7]
wire _max_T = io_cmd_0 == 5'hD; // @[AMOALU.scala:54:7, :67:20]
wire _max_T_1 = io_cmd_0 == 5'hF; // @[AMOALU.scala:54:7, :67:43]
wire max = _max_T | _max_T_1; // @[AMOALU.scala:67:{20,33,43}]
wire _min_T = io_cmd_0 == 5'hC; // @[AMOALU.scala:54:7, :68:20]
wire _min_T_1 = io_cmd_0 == 5'hE; // @[AMOALU.scala:54:7, :68:43]
wire min = _min_T | _min_T_1; // @[AMOALU.scala:68:{20,33,43}]
wire add = io_cmd_0 == 5'h8; // @[AMOALU.scala:54:7, :69:20]
wire _GEN = io_cmd_0 == 5'hA; // @[AMOALU.scala:54:7, :70:26]
wire _logic_and_T; // @[AMOALU.scala:70:26]
assign _logic_and_T = _GEN; // @[AMOALU.scala:70:26]
wire _logic_xor_T_1; // @[AMOALU.scala:71:49]
assign _logic_xor_T_1 = _GEN; // @[AMOALU.scala:70:26, :71:49]
wire _logic_and_T_1 = io_cmd_0 == 5'hB; // @[AMOALU.scala:54:7, :70:48]
wire logic_and = _logic_and_T | _logic_and_T_1; // @[AMOALU.scala:70:{26,38,48}]
wire _logic_xor_T = io_cmd_0 == 5'h9; // @[AMOALU.scala:54:7, :71:26]
wire logic_xor = _logic_xor_T | _logic_xor_T_1; // @[AMOALU.scala:71:{26,39,49}]
wire _adder_out_mask_T = io_mask_0[3]; // @[AMOALU.scala:54:7, :75:69]
wire _wmask_T_3 = io_mask_0[3]; // @[AMOALU.scala:54:7, :75:69, :106:30]
wire _adder_out_mask_T_1 = ~_adder_out_mask_T; // @[AMOALU.scala:75:{61,69}]
wire [31:0] _adder_out_mask_T_2 = {_adder_out_mask_T_1, 31'h0}; // @[AMOALU.scala:75:{61,77}]
wire [63:0] _adder_out_mask_T_3 = {32'h0, _adder_out_mask_T_2}; // @[AMOALU.scala:75:{77,96}]
wire [63:0] adder_out_mask = ~_adder_out_mask_T_3; // @[AMOALU.scala:75:{16,96}]
wire [63:0] _adder_out_T = io_lhs_0 & adder_out_mask; // @[AMOALU.scala:54:7, :75:16, :76:13]
wire [63:0] _adder_out_T_1 = io_rhs_0 & adder_out_mask; // @[AMOALU.scala:54:7, :75:16, :76:31]
wire [64:0] _adder_out_T_2 = {1'h0, _adder_out_T} + {1'h0, _adder_out_T_1}; // @[AMOALU.scala:76:{13,21,31}]
wire [63:0] adder_out = _adder_out_T_2[63:0]; // @[AMOALU.scala:76:21]
wire _less_T = io_mask_0[4]; // @[AMOALU.scala:54:7, :94:49]
wire _wmask_T_4 = io_mask_0[4]; // @[AMOALU.scala:54:7, :94:49, :106:30]
wire [4:0] _GEN_0 = {3'h0, io_cmd_0[1], 1'h0}; // @[AMOALU.scala:54:7, :89:17]
wire [4:0] _less_signed_T; // @[AMOALU.scala:89:17]
assign _less_signed_T = _GEN_0; // @[AMOALU.scala:89:17]
wire [4:0] _less_signed_T_2; // @[AMOALU.scala:89:17]
assign _less_signed_T_2 = _GEN_0; // @[AMOALU.scala:89:17]
wire less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala:89:{17,25}]
wire _less_T_1 = io_lhs_0[63]; // @[AMOALU.scala:54:7, :91:12]
wire _less_T_15 = io_lhs_0[63]; // @[AMOALU.scala:54:7, :91:{12,68}]
wire _less_T_2 = io_rhs_0[63]; // @[AMOALU.scala:54:7, :91:23]
wire _less_T_16 = io_rhs_0[63]; // @[AMOALU.scala:54:7, :91:{23,76}]
wire _less_T_3 = _less_T_1 == _less_T_2; // @[AMOALU.scala:91:{12,18,23}]
wire [31:0] _less_T_4 = io_lhs_0[63:32]; // @[AMOALU.scala:54:7, :83:13]
wire [31:0] _less_T_7 = io_lhs_0[63:32]; // @[AMOALU.scala:54:7, :83:{13,42}]
wire [31:0] _less_T_5 = io_rhs_0[63:32]; // @[AMOALU.scala:54:7, :83:27]
wire [31:0] _less_T_8 = io_rhs_0[63:32]; // @[AMOALU.scala:54:7, :83:{27,58}]
wire _less_T_6 = _less_T_4 < _less_T_5; // @[AMOALU.scala:83:{13,24,27}]
wire _less_T_9 = _less_T_7 == _less_T_8; // @[AMOALU.scala:83:{42,53,58}]
wire [31:0] _less_T_10 = io_lhs_0[31:0]; // @[AMOALU.scala:54:7, :82:26]
wire [31:0] _less_T_23 = io_lhs_0[31:0]; // @[AMOALU.scala:54:7, :82:26]
wire [31:0] _less_T_11 = io_rhs_0[31:0]; // @[AMOALU.scala:54:7, :82:38]
wire [31:0] _less_T_24 = io_rhs_0[31:0]; // @[AMOALU.scala:54:7, :82:38]
wire _less_T_12 = _less_T_10 < _less_T_11; // @[AMOALU.scala:82:{26,35,38}]
wire _less_T_13 = _less_T_9 & _less_T_12; // @[AMOALU.scala:82:35, :83:{53,69}]
wire _less_T_14 = _less_T_6 | _less_T_13; // @[AMOALU.scala:83:{24,38,69}]
wire _less_T_17 = less_signed ? _less_T_15 : _less_T_16; // @[AMOALU.scala:89:25, :91:{58,68,76}]
wire _less_T_18 = _less_T_3 ? _less_T_14 : _less_T_17; // @[AMOALU.scala:83:38, :91:{10,18,58}]
wire _less_T_19 = io_mask_0[2]; // @[AMOALU.scala:54:7, :94:49]
wire _wmask_T_2 = io_mask_0[2]; // @[AMOALU.scala:54:7, :94:49, :106:30]
wire less_signed_1 = _less_signed_T_2 == 5'h0; // @[AMOALU.scala:89:{17,25}]
wire _less_T_20 = io_lhs_0[31]; // @[AMOALU.scala:54:7, :91:12]
wire _less_T_26 = io_lhs_0[31]; // @[AMOALU.scala:54:7, :91:{12,68}]
wire _less_T_21 = io_rhs_0[31]; // @[AMOALU.scala:54:7, :91:23]
wire _less_T_27 = io_rhs_0[31]; // @[AMOALU.scala:54:7, :91:{23,76}]
wire _less_T_22 = _less_T_20 == _less_T_21; // @[AMOALU.scala:91:{12,18,23}]
wire _less_T_25 = _less_T_23 < _less_T_24; // @[AMOALU.scala:82:{26,35,38}]
wire _less_T_28 = less_signed_1 ? _less_T_26 : _less_T_27; // @[AMOALU.scala:89:25, :91:{58,68,76}]
wire _less_T_29 = _less_T_22 ? _less_T_25 : _less_T_28; // @[AMOALU.scala:82:35, :91:{10,18,58}]
wire less = _less_T ? _less_T_18 : _less_T_29; // @[Mux.scala:50:70]
wire _minmax_T = less ? min : max; // @[Mux.scala:50:70]
wire [63:0] minmax = _minmax_T ? io_lhs_0 : io_rhs_0; // @[AMOALU.scala:54:7, :97:{19,23}]
wire [63:0] _logic_T = io_lhs_0 & io_rhs_0; // @[AMOALU.scala:54:7, :99:27]
wire [63:0] _logic_T_1 = logic_and ? _logic_T : 64'h0; // @[AMOALU.scala:70:38, :99:{8,27}]
wire [63:0] _logic_T_2 = io_lhs_0 ^ io_rhs_0; // @[AMOALU.scala:54:7, :100:27]
wire [63:0] _logic_T_3 = logic_xor ? _logic_T_2 : 64'h0; // @[AMOALU.scala:71:39, :100:{8,27}]
wire [63:0] logic_0 = _logic_T_1 | _logic_T_3; // @[AMOALU.scala:99:{8,42}, :100:8]
wire _out_T = logic_and | logic_xor; // @[AMOALU.scala:70:38, :71:39, :103:19]
wire [63:0] _out_T_1 = _out_T ? logic_0 : minmax; // @[AMOALU.scala:97:19, :99:42, :103:{8,19}]
assign out = add ? adder_out : _out_T_1; // @[AMOALU.scala:69:20, :76:21, :102:8, :103:8]
assign io_out_unmasked = out; // @[AMOALU.scala:54:7, :102:8]
wire _wmask_T = io_mask_0[0]; // @[AMOALU.scala:54:7, :106:30]
wire _wmask_T_1 = io_mask_0[1]; // @[AMOALU.scala:54:7, :106:30]
wire _wmask_T_5 = io_mask_0[5]; // @[AMOALU.scala:54:7, :106:30]
wire _wmask_T_6 = io_mask_0[6]; // @[AMOALU.scala:54:7, :106:30]
wire _wmask_T_7 = io_mask_0[7]; // @[AMOALU.scala:54:7, :106:30]
wire [7:0] _wmask_T_8 = {8{_wmask_T}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_9 = {8{_wmask_T_1}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_10 = {8{_wmask_T_2}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_11 = {8{_wmask_T_3}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_12 = {8{_wmask_T_4}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_13 = {8{_wmask_T_5}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_14 = {8{_wmask_T_6}}; // @[AMOALU.scala:106:30]
wire [7:0] _wmask_T_15 = {8{_wmask_T_7}}; // @[AMOALU.scala:106:30]
wire [15:0] wmask_lo_lo = {_wmask_T_9, _wmask_T_8}; // @[AMOALU.scala:106:30]
wire [15:0] wmask_lo_hi = {_wmask_T_11, _wmask_T_10}; // @[AMOALU.scala:106:30]
wire [31:0] wmask_lo = {wmask_lo_hi, wmask_lo_lo}; // @[AMOALU.scala:106:30]
wire [15:0] wmask_hi_lo = {_wmask_T_13, _wmask_T_12}; // @[AMOALU.scala:106:30]
wire [15:0] wmask_hi_hi = {_wmask_T_15, _wmask_T_14}; // @[AMOALU.scala:106:30]
wire [31:0] wmask_hi = {wmask_hi_hi, wmask_hi_lo}; // @[AMOALU.scala:106:30]
wire [63:0] wmask = {wmask_hi, wmask_lo}; // @[AMOALU.scala:106:30]
wire [63:0] _io_out_T = wmask & out; // @[AMOALU.scala:102:8, :106:30, :107:19]
wire [63:0] _io_out_T_1 = ~wmask; // @[AMOALU.scala:106:30, :107:27]
wire [63:0] _io_out_T_2 = _io_out_T_1 & io_lhs_0; // @[AMOALU.scala:54:7, :107:{27,34}]
assign _io_out_T_3 = _io_out_T | _io_out_T_2; // @[AMOALU.scala:107:{19,25,34}]
assign io_out_0 = _io_out_T_3; // @[AMOALU.scala:54:7, :107:25]
assign io_out = io_out_0; // @[AMOALU.scala:54:7]
endmodule |
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